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1.1 General description

The BF1208D is a combination of two dual gate MOSFET ampliﬁers with shared source and gate2 leads and an integrated switch. The integrated switch is operated by the gate1 bias of ampliﬁer B. The source and substrate are interconnected. Internal bias circuits enable DC stabilization and a very good cross modulation performance during Automatic Gain Control (AGC). Integrated diodes between the gates and source protect against excessive input voltage surges. The transistor has a SOT666 micro-miniature plastic package.

1.2 Features

n Two low noise gain controlled ampliﬁers in a single package. One with a fully integrated bias and one with a partly integrated bias n Internal switch to save external components n Superior cross modulation performance during AGC n High forward transfer admittance n High forward transfer admittance to input capacitance ratio

1.3 Applications

n Gain controlled low noise ampliﬁers for VHF and UHF applications with 5 V supply voltage u digital and analog television tuners u professional communication equipment BF1208D Dual N-channel dual gate MOSFET Rev. 01 — 16 May 2007 Product data sheet CAUTION This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken during transport and handling.

1.4 Quick reference data

[1] Tsp is the temperature at the soldering point of the source lead. [2] Calculated from S-parameters. [4] Measured inFigure34 test circuit. Table 1. Quick reference data Per MOSFET unless otherwise speciﬁed. Table 2. Discrete pinning

BF1208D_1 © NXP B.V. 2007. All rights reserved. [1] Tsp is the temperature at the soldering point of the source lead. Table 3. Ordering information Table 4. Marking codes Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).

BF1208D_1 © NXP B.V. 2007. All rights reserved. [1] R G1 connects gate1 (B) to VGG = 0 V (seeFigure3). [2] R G1 connects gate1 (B) to VGG = 5 V (seeFigure3). Table 6. Thermal characteristics Table 7. Static characteristics Tj=2 5°C; unless otherwise speciﬁed.

8.1 Dynamic characteristics for ampliﬁer A

VGG = 5 V: ampliﬁer A is off; ampliﬁer B is on. VGG = 0 V: ampliﬁer A is on; ampliﬁer B is off. Table 8. Dynamic characteristics for ampliﬁer A[1] Common source; Tamb =2 5°C; VG2-S =4V ; VDS =5V ; ID = 19 mA; unless otherwise speciﬁed.

8.1.1 Graphics for ampliﬁer A

Table 8. Dynamic characteristics for ampliﬁer A[1] …continued Common source; Tamb =2 5°C; VG2-S =4V ; VDS =5V ; ID = 19 mA; unless otherwise speciﬁed.

BF1208D_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 16 May 2007 7 of 22 NXP Semiconductors BF1208D Dual N-channel dual gate MOSFET (1) VG2-S =4V . (2) VG2-S = 3.5 V. (3) VG2-S =3V . (4) VG2-S = 2.5 V. (5) VG2-S =2V . (6) VG2-S = 1.5 V. VDS(A) =5V ; VG1-S(B) =V DS(B) =0V ; Tj=2 5°C. VDS(A) =5V ; VG2-S =4V ; VDS(B) =5V ; VG1-S(B) =0V ; Tj=2 5°C. ID(B) = internal gate1 current = current in pin drain (AMP B) if MOSFET (B) is switched off. Fig 6. Ampliﬁer A: forward transfer admittance as a function of drain current; typical values Fig 7. Ampliﬁer A: drain current as a function of internal gate1 current; typical values ID (mA) 03 2 2481 6 001aaa556 yfs (mS) (1) (2) (3) (4) (5) (6) 001aac206 ID(B) (µA) 06 0 4020 ID(A) (mA)

BF1208D_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 16 May 2007 8 of 22 NXP Semiconductors BF1208D Dual N-channel dual gate MOSFET VDS(A) =V DS(B) =V sup; VG2-S =4V ; Tj=2 5°C; R G1 =8 6kΩ (connected to ground); seeFigure3. (1) VDS(B) =5V . (2) VDS(B) = 4.5 V. (3) VDS(B) =4V . (4) VDS(B) = 3.5 V. (5) VDS(B) =3V . (6) VDS(B) = 2.5 V. VDS(A) =5V ; VG1-S(B) = 0 V; gate1 (AMP A) is open; Tj=2 5°C. Fig 8. Ampliﬁer A: drain current of ampliﬁer A as a function of supply voltage of A and B ampliﬁer; typical values Fig 9. Ampliﬁer A: drain current as a function of gate2 voltage; typical values VDS(A) =V DS(B) =5V ; VG1-S(B) =0V ; fw = 50 MHz; funw = 60 MHz; Tamb =2 5°C; seeFigure33. VDS(A) =V DS(B) =5V ; VG1-S(B) = 0 V; f = 50 MHz; see Figure33. Fig 10. Ampliﬁer A: unwanted voltage for 1 % cross modulation as a function of gain reduction; typical values Fig 11. Ampliﬁer A: gain reduction as a function of AGC voltage; typical values Vsup (V) 05 4231 001aaa558 ID (mA) 001aaa559 VG2-S (V) 06 42 ID (mA) (1) (2) (3) (4) (5) (6) gain reduction (dB) 05 0 4020 3010 001aac195 100 110 120 Vunw (dBmV) VAGC (V) 04 312 001aac196 gain reduction (dB)

BF1208D_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 16 May 2007 9 of 22 NXP Semiconductors BF1208D Dual N-channel dual gate MOSFET VDS(A) =V DS(B) =5V ; VG1-S(B) = 0 V; f = 50 MHz; Tamb =2 5°C; seeFigure33. VDS(A) =5V ; VG2-S =4V ; VDS(B) =V G1-S(B) =0V ; ID(A) =1 9m A Fig 12. Ampliﬁer A: drain current as a function of gain reduction; typical values Fig 13. Ampliﬁer A: input admittance as a function of frequency; typical values VDS(A) =5V ; VG2-S =4V ; VDS(B) =V G1-S(B) =0V ; ID(A) =1 9m A VDS(A) =5V ; VG2-S =4V ; VDS(B) =V G1-S(B) =0V ; ID(A) =1 9m A Fig 14. Ampliﬁer A: forward transfer admittance and phase as a function of frequency; typical values Fig 15. Ampliﬁer A: reverse transfer admittance and phase as a function of frequency; typical values gain reduction (dB) 05 0 4020 3010 001aac197 I D (mA) 001aag357 f (MHz) 10 10 3102 10−1 102 bis, gis (mS) 10−2 bis gis 001aag358 102 Yfs (mS) 10−1 −10 −102 ϕfs (deg) −10−1 f (MHz) 10 10 3102 Yfs ϕfs 001aag359 102 103 Yrs (µS) −102 −10 −103 ϕrs (deg) f (MHz) 10 10 3102 Yrs ϕrs

8.1.2 Scattering parameters for ampliﬁer A

8.1.3 Noise data for ampliﬁer A

Table 9. Scattering parameters for ampliﬁer A Table 10. Noise data for ampliﬁer A

8.2 Dynamic characteristics for ampliﬁer B

[1] For the MOSFET not in use: VG1-S(A) = 0 V; VDS(A) =0 V . [2] Calculated from S-parameters. Table 11. Dynamic characteristics for ampliﬁer B[1] Common source; Tamb =2 5°C; VG2-S =4V ; VDS =5V ; ID = 15 mA; unless otherwise speciﬁed.

8.2.1 Graphics for ampliﬁer B

(1) VG2-S =4V . (2) VG2-S = 3.5 V. (3) VG2-S =3V . (4) VG2-S = 2.5 V. (5) VG2-S =2V . (6) VG2-S = 1.5 V. (7) VG2-S =1V . VDS(B) =5V ; VDS(A) =V G1-S(A) =0V ; Tj=2 5°C. (7) VG1-S(B) =1V . VG2-S =4V ; VDS(A) =V G1-S(A) =0V ; Tj=2 5°C. Fig 17. Ampliﬁer B: transfer characteristics; typical values Fig 18. Ampliﬁer B: output characteristics; typical values VG1-S (V) 001aag361 I D (mA) (4) (5) (6) (7) (1) (2) (3) VDS (V) 06 42 001aag362 I D (mA) (7) (6) (5) (4) (3) (2) (1)

BF1208D_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 16 May 2007 13 of 22 NXP Semiconductors BF1208D Dual N-channel dual gate MOSFET (1) VG2-S =4V . (2) VG2-S = 3.5 V. (3) VG2-S =3V . (4) VG2-S = 2.5 V. (5) VG2-S =2V . (6) VG2-S = 1.5 V. (7) VG2-S =1V . VDS(B) =5V ; VDS(A) =V G1-S(A) =0V ; Tj=2 5°C. (1) VG2-S =4V . (2) VG2-S = 3.5 V. (3) VG2-S =3V . (4) VG2-S = 2.5 V. (5) VG2-S =2V . (6) VG2-S = 1.5 V. (7) VG2-S =1V . VDS(B) =5V ; VDS(A) =V G1-S(A) =0V ; Tj=2 5°C. Fig 19. Ampliﬁer B: gate1 current as a function of gate1 voltage; typical values Fig 20. Ampliﬁer B: forward transfer admittance as a function of drain current; typical values VDS(B) =5V ; VG2-S =4V ; VDS(A) =V G1-S(A) =0V ; Tj=2 5°C. VDS(B) =5V ; VG2-S =4V ; VDS(A) =V G1-S(A) =0V ; Tj=2 5°C; RG1 =8 6kΩ (connected to VGG ); see Figure3. Fig 21. Ampliﬁer B: drain current as a function of gate1 current; typical values Fig 22. Ampliﬁer B: drain current as a function of gate1 supply voltage; typical values VG1-S (V) 001aag363 100 IG1 (µA) (1) (2) (5) (7) (3) (4) (6) ID (mA) 03 2 2481 6 001aag364 Yfs (mS) (1) (2) (3) (4) (5) (7) (6) IG1 (µA) 05 0 4020 3010 001aag365 ID (mA) VGG (V) 05 4231 001aag366 ID (mA)

BF1208D_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 16 May 2007 14 of 22 NXP Semiconductors BF1208D Dual N-channel dual gate MOSFET (1) RG1 =4 7kΩ . (2) RG1 =5 6kΩ . (3) RG1 =6 8kΩ . (4) RG1 =8 2kΩ . (5) RG1 =8 6kΩ . (6) RG1 = 100 kΩ . (7) RG1 = 120 kΩ . (8) RG1 = 150 kΩ . (9) RG1 = 180 kΩ . VG2-S =4V ; VDS(A) =V G1-S(A) =0V ; Tj=2 5°C; R G1 is connected to VGG ; seeFigure3. (1) VGG = 5.0 V. (2) VGG = 4.5 V. (3) VGG = 4.0 V. (4) VGG = 3.5 V. (5) VGG = 3.0 V. VDS(B) =5V ; VDS(A) =V G1-S(A) =0V ; Tj=2 5°C; R G1 =8 6kΩ (connected to VGG ); seeFigure3. Fig 23. Ampliﬁer B: drain current as a function of gate1 supply voltage and drain supply voltage; typical values Fig 24. Ampliﬁer B: drain current as a function of gate2 voltage; typical values VGG = VDS (V) 05 4231 001aag367 ID (mA) (1) (4) (5) (6) (7) (8) (9) (3) (2) VG2-S (V) 06 42 001aag368 I D (mA) (5) (3) (2) (1) (4)

BF1208D_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 16 May 2007 15 of 22 NXP Semiconductors BF1208D Dual N-channel dual gate MOSFET (1) VGG = 5.0 V. (2) VGG = 4.5 V. (3) VGG = 4.0 V. (4) VGG = 3.5 V. (5) VGG = 3.0 V. VDS(B) =5V ; VDS(A) =V G1-S(A) =0V ; Tj=2 5°C; R G1 =8 6kΩ (connected to VGG ); seeFigure3. VDS(B) =5V ; VGG =5V ; VDS(A) =V G1-S(A) =0V ; R G1 =8 6kΩ (connected to VGG ); fw = 50 MHz; funw = 60 MHz; Tamb =2 5°C; seeFigure34. Fig 25. Ampliﬁer B: gate1 current as a function of gate2 voltage; typical values Fig 26. Ampliﬁer B: unwanted voltage for 1 % cross modulation as a function of gain reduction; typical values VDS(B) =5V ; VGG =5V ; VDS(A) =V G1-S(A) =0V ; R G1 =8 6kΩ (connected to VGG ); f = 50 MHz; Tamb =2 5°C; seeFigure34. VDS(B) =5V ; VGG =5V ; VDS(A) =V G1-S(A) =0V ; R G1 =8 6kΩ (connected to VGG ); f = 50 MHz; Tamb =2 5°C; seeFigure34. Fig 27. Ampliﬁer B: gain reduction as a function of AGC voltage; typical values Fig 28. Ampliﬁer B: drain current as a function of gain reduction; typical values 001aag369 VG2-S (V) 06 42 IG1 (µA) (5) (3) (2) (1) (4) 001aag370 gain reduction (dB) 06 0 4020 100 110 120 Vunw (dBµV) VAGC (V) 04 312 001aag371 gain reduction (dB) 001aag372 gain reduction (dB) 06 0 4020 ID (mA)

BF1208D_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 16 May 2007 16 of 22 NXP Semiconductors BF1208D Dual N-channel dual gate MOSFET VDS(B) =5V ; VG2-S =4V ; VDS(A) =V G1-S(A) =0V ; ID(B) =1 5m A VDS(B) =5V ; VG2-S =4V ; VDS(A) =V G1-S(A) =0V ; ID(B) =1 5m A Fig 29. Ampliﬁer B: input admittance as a function of frequency; typical values Fig 30. Ampliﬁer B: forward transfer admittance and phase as a function of frequency; typical values VDS(B) =5V ; VG2-S =4V ; VDS(A) =V G1-S(A) =0V ; ID(B) =1 5m A VDS(B) =5V ; VG2-S =4V ; VDS(A) =V G1-S(A) =0V ; ID(B) =1 5m A Fig 31. Ampliﬁer B: reverse transfer admittance and phase as a function of frequency; typical values Fig 32. Ampliﬁer B: output admittance as a function of frequency; typical values 001aag373 102 bis, gis (mS) 10−1 f (MHz) 10 10 3102 bis gis f (MHz) 10 10 3102 001aag374 −10 −102 ϕfs (deg) 102 Yfs (mS) Yfs ϕfs 001aag375 102 103 Yrs (µS) −102 −10 −103 ϕrs (deg) f (MHz) 10 10 3102 Yrs ϕrs 001aag376 10−1 bos, gos (mS) 10−2 f (MHz) 10 10 3102 bos gos

8.2.2 Scattering parameters for ampliﬁer B

8.2.3 Noise data for ampliﬁer B

Table 12. Scattering parameters for ampliﬁer B Table 13. Noise data for ampliﬁer B

BF1208D_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 16 May 2007 18 of 22 NXP Semiconductors BF1208D Dual N-channel dual gate MOSFET 9. Test information Fig 33. Cross modulation test set-up for ampliﬁer A Fig 34. Cross modulation test set-up for ampliﬁer B 50 Ω 10 kΩ R GEN 50 Ω R L 50 Ω50 Ω R G1 4.7 nF 4.7 nF 4.7 nF G2 S G1B DB DA 4.7 nF 4.7 nF 4.7 nFG1A BF1208D VGG VDS(B) VDS(A) VAGC 2.2 µH 2.2 µH 001aag398 Vi 50 Ω 10 kΩ R GEN 50 Ω 50 Ω R G1 4.7 nF 4.7 nF 4.7 nF G2 S G1B DB DA 4.7 nF 4.7 nF 4.7 nF G1A BF1208D VGG VDS(B) VDS(A) VAGC 2.2 µH 2.2 µH R L 50 Ω 001aag399 Vi

BF1208D_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 16 May 2007 19 of 22 NXP Semiconductors BF1208D Dual N-channel dual gate MOSFET 10. Package outline Fig 35. Package outline SOT666 UNIT b p cD E e1 H E Lp w REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE 04-11-08 06-03-16 IEC JEDEC JEITA mm 0.27 0.17 0.18 0.08 1.7 1.5 1.3 1.1 0.5 e 1.0 1.7 1.5 0.1 y 0.1 DIMENSIONS (mm are the original dimensions) 0.3 0.1 SOT666 bp pin 1 index D e A Lp detail X H E EA S 0 1 2 mm scale A 0.6 0.5 c X 123 456 Plastic surface-mounted package; 6 leads SOT666 YS w M A

13.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Deﬁnitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

13.2 Deﬁnitions

Draft —The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modiﬁcations or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet —A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the full data sheet shall prevail.

13.3 Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes —NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation speciﬁcations and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use —NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications —Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the speciﬁed use without further testing or modiﬁcation. Limiting values —Stress above one or more limiting values (as deﬁned in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale —NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/proﬁle/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conﬂict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license —Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

13.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 14. Contact information For additional information, please visit:http://www.nxp.com For sales ofﬁce addresses, send an email to:salesaddresses@nxp.com Document status[1][2] Product status[3] Deﬁnition Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development. Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation. Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors BF1208D Dual N-channel dual gate MOSFET © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 16 May 2007 Document identifier: BF1208D_1 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 15. Contents

Product Information

BF1208D specifications and overview.

Summary

Dual N-channel dual gate MOSFET

Description

Dual N-channel dual gate MOSFET

Source title BF1208D Datasheet(PDF) - Quanzhou Jinmei Electronic Co.,Ltd.

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