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BF1205

Quanzhou Jinmei Electro...

Dual N-channel dual gate MOS-FET

Manufacturer: Quanzhou Jinmei Electro...

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Product speciﬁcation 2003 Sep 30 DISCRETE SEMICONDUCTORS BF1205 Dual N-channel dual gate MOS-FET andbook, halfpage MBD128

2003 Sep 30 2

Philips Semiconductors Product speciﬁcation Dual N-channel dual gate MOS-FET BF1205

FEATURES

Two low noise gain controlled amplifiers in a single package. One with a fully integrated bias and one with a partly integrated bias
Internal switch reduces the number of external components
Superior cross-modulation performance during AGC
High forward transfer admittance
High forward transfer admittance to input capacitance ratio.

APPLICATIONS

Gain controlled low noise amplifiers for VHF and UHF applications with 5 V supply voltage, such as digital and analog television tuners and professional communications equipment.

DESCRIPTION

The BF1205 is a combination of two equal dual gate MOS-FET amplifiers with shared source and gate 2 leads and an integrated switch. The integrated switch is operated by the gate 1 bias of amplifier b. The source and substrate are interconnected. Internal bias circuits enable DC stabilization and a very good cross-modulation performance during AGC. Integrated diodes between the gates and source protect against excessive input voltage surges. The transistor is encapsulated in SOT363 micro-miniature plastic package. PINNING - SOT363 PIN DESCRIPTION 1 gate 1 (a) 2 gate 2 3 gate 1 (b) 4 drain (b) 5 source 6 drain (a) handbook, halfpage 123 654 Top view MGX429 AMP a d (a) s d (b) g1 (a) g2 g1 (b) AMP b Fig.1 Simplified outline and symbol. Marking code: L4-.

ORDERING INFORMATION

BF1205 − Plastic surface mounted package; 6 leads SOT363

2003 Sep 30 3

Philips Semiconductors Product speciﬁcation Dual N-channel dual gate MOS-FET BF1205 QUICK REFERENCE DATA LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). Note 1. Ts is the temperature at the soldering point of the source lead. THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Per MOS-FET; unless otherwise speciﬁed VDS drain-source voltage −− 10 V ID drain current (DC) −− 30 mA Ptot total power dissipation T s ≤ 102 °C; temperature at the soldering point of the source lead −− 200 mW yfs forward transfer admittance I D = 1 2 m A 2 63 14 0 m S C ig1-ss input capacitance at gate 1 amp. a: f = 1 MHz − 1.8 2.3 pF amp. b: f = 1 MHz − 2.0 2.5 pF C rss reverse transfer capacitance f = 1 MHz − 20 − fF NF noise ﬁgure amp. a: f = 800 MHz − 1.2 1.9 dB amp. b: f = 800 MHz − 1.4 2.1 dB Xmod cross-modulation amp. a: input level for k = 1% at 40 dB AGC 98 102 − dBµV amp. b: input level for k = 1% at 40 dB AGC 100 105 − dBµV Tj junction temperature −− 150 °C CAUTION This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Per MOS-FET; unless otherwise speciﬁed VDS drain-source voltage − 10 V ID drain current (DC) − 30 mA IG1 gate 1 current −± 10 mA IG2 gate 2 current −± 10 mA Ptot total power dissipation T s ≤ 102 °C; note − 200 mW Tstg storage temperature −65 +150 °C Tj junction temperature − 150 °C SYMBOL PARAMETER VALUE UNIT R th j-s thermal resistance from junction to soldering point 240 K/W

2003 Sep 30 4

Philips Semiconductors Product speciﬁcation Dual N-channel dual gate MOS-FET BF1205 handbook, halfpage 0 50 100 200 250 200 MGS359 150 150 100 Ts (°C) Ptot (mW) Fig.2 Power derating curve. STATIC CHARACTERISTICS Tj=2 5°C; per MOS-FET; unless otherwise speciﬁed. Note 1. R G1 connects gate 1 (b) to VGG = 0 V (see Fig.4). 2. R G1 connects gate 1 (b) to VGG = 5 V (see Fig.4). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V(BR)DSS drain-source breakdown voltage amp. a: VG1-S =V G2-S =0V ; ID =1 0µA1 0 − V amp. b: VG1-S =V G2-S =0V ; ID =1 0µA7 − V V(BR)G1-SS gate-source breakdown voltage V GS =V DS =0V ; IG1-S = 10 mA 6 10 V V(BR)G2-SS gate-source breakdown voltage V GS =V DS =0V ; IG2-S = 10 mA 6 10 V V(F)S-G1 forward source-gate voltage V G2-S =V DS =0V ; IS-G1 = 10 mA 0.5 1.5 V V(F)S-G2 forward source-gate voltage V G1-S =V DS =0V ; IS-G2 = 10 mA 0.5 1.5 V VG1-S(th) gate-source threshold voltage V DS =5V ; VG2-S =4V ; ID = 100µA 0.3 1 V VG2-S(th) gate-source threshold voltage V DS =5V ; VG1-S =5V ; ID = 100µA 0.4 1.0 V IDSX drain-source current amp. a: V G2-S =4V ; VDS =5V ; R G1 = 150 kΩ ; note 1 81 6m A amp. b: VG2-S =4V ; VDS =5V ; R G1 = 150 kΩ ; note 2 81 6m A IG1-S gate cut-off current amp. a: V G1-S =5V ; VG2-S =V DS =0V − 50 nA amp. b: VG1-S =5V ; VG2-S =V DS =0V − 50 nA IG2-S gate cut-off current V G2-S =4V ; VG1-S =V DS =0V − 20 nA

2003 Sep 30 5

Philips Semiconductors Product speciﬁcation Dual N-channel dual gate MOS-FET BF1205 handbook, halfpage VGG (V) 2314 MGX430 ID (mA) (1) (2) (3) (4) (5) (6) Fig.3 Drain currents of MOS-FET a and b as functions of VGG (see Fig.4). (1) ID (b); RG1 = 120 kΩ . (2) ID (b); RG1 = 150 kΩ . (3) ID (b); RG1 = 180 kΩ . (4) ID (a); RG1 = 180 kΩ . (5) ID (a); RG1 = 150 kΩ . (6) ID (a); RG1 = 120 kΩ . handbook, halfpage MGX431VGG R G1 d (a) s d (b) g1 (a) g1 (b) Fig.4 Functional diagram VGG = 5 V: amplifier a is OFF; amplifier b is ON. VGG = 0 V: amplifier a is ON; amplifier b is OFF.

2003 Sep 30 6

Philips Semiconductors Product speciﬁcation Dual N-channel dual gate MOS-FET BF1205 DYNAMIC CHARACTERISTICS AMPLIFIER a Common source; Tamb =2 5°C; VG2-S =4V ; VDS =5V ; ID = 12 mA; note 1 Notes 1. For the MOS-FET not in use: VG1-S (b) = 0 V; VDS (b) = 0 V. 2. Measured in Fig.13 test circuit. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT yfs forward transfer admittance Tj=2 5°C 2 63 14 0m S C ig1-ss input capacitance at gate 1 f = 1 MHz − 1.8 2.3 pF C ig2-ss input capacitance at gate 2 f = 1 MHz − 3.3 − pF C oss output capacitance f = 1 MHz − 0.75 − pF C rss reverse transfer capacitance f = 1 MHz − 20 − fF G tr power gain f = 200 MHz; G S = 2 mS; BS =B S(opt); G L = 0.5 mS; BL =B L(opt) 31 35 39 dB f = 400 MHz; GS = 2 mS; BS =B S(opt); G L = 1 mS; BL =B L(opt) 27 31 35 dB f = 800 MHz; GS = 3.3 mS; BS =B S(opt); G L = 1 mS; BL =B L(opt) 22 26 30 dB NF noise ﬁgure f = 10.7 MHz; G S = 20 mS; BS =0 − 4 − dB f = 400 MHz; YS =Y S(opt) − 1.1 1.7 dB f = 800 MHz; YS =Y S(opt) − 1.2 1.9 dB Xmod cross-modulation input level for k = 1% at 0 dB AGC; fw = 50 MHz; funw = 60 MHz; note 2 90 −− dBµV input level for k = 1% at 10 dB AGC; fw = 50 MHz; funw = 60 MHz; note 2 − 90 − dBµV input level for k = 1% at 40 dB AGC; fw = 50 MHz; funw = 60 MHz; note 2 98 102 − dBµV

2003 Sep 30 7

Philips Semiconductors Product speciﬁcation Dual N-channel dual gate MOS-FET BF1205 GRAPHS FOR AMPLIFIER a handbook, halfpage 0.4 0.8 1.2 1.6 VG1-S (V) ID (mA) MGX432 (7) (6) (5)(4) (1) (2) (3) Fig.5 Transfer characteristics; typical values; amplifier a. VDS (a) = 5 V; VG1-S (b) = VDS (b) = 0 V; Tj=2 5°C. (1) VG2-S =4V . (2) VG2-S = 3.5 V. (3) VG2-S =3V . (4) VG2-S = 2.5 V. (5) VG2-S =2V . (6) VG2-S = 1.5 V. (7) VG2-S =1V . handbook, halfpage 01 0 VDS (V) ID (mA) 648 MGX433 (7) (6) (5) (4) (3) (2) (1) Fig.6 Output characteristics; typical values; amplifier a. VG2-S = 4 V; VG1-S ( b )=VDS (b) = 0 V; Tj=2 5°C. (5) VG1-S (a) = 1 V.

2003 Sep 30 8

Philips Semiconductors Product speciﬁcation Dual N-channel dual gate MOS-FET BF1205 handbook, halfpage ID (mA) 42 0 81 21 6 MGX434 yfs (mS) (5) (4) (3) (2)(1) Fig.7 Forward transfer admittance as a function of drain current; typical values; amplifier a. VDS (a) = 5 V; VG1-S (b) = VDS (b) = 0 V; Tj=2 5°C. (1) VG2-S =4V . (2) VG2-S = 3.5 V. (3) VG2-S =3V . (4) VG2-S = 2.5 V. (5) VG2-S =2V . handbook, halfpage 01 0 2 0 4 0 ID (b) (mA) ID (a) (mA) MGX435 Fig.8 Drain current as a function of internal G1 current (current in pin drain (b) if MOS-FET (b) is switched off); typical values; amplifier a. VDS (a) = 5 V; VG2-S = 4 V; VDS (b) = 5 V; VG1-S (b) = 0 V; Tj=2 5°C.

2003 Sep 30 9

Philips Semiconductors Product speciﬁcation Dual N-channel dual gate MOS-FET BF1205 handbook, halfpage 246 VGG = VDS (V) ID (mA) MGX436 (5) (4) (3) (2)(1) Fig.9 Drain current as a function of gate 2 and drain supply voltage; typical values; amplifier a. VDS (a) = 5 V; VG1-S (b) = 0 V; Gate 1 (a) = open; Tj=2 5°C. (1) VDS (b) = 5 V. (2) VDS (b) = 4.5 V. (3) VDS (b) = 4 V. (4) VDS (b) = 3.5 V. (5) VDS (b) = 3 V. handbook, halfpage gain reduction (dB) 120 110 100 20 40 MGX437 Vunw (dBmV) Fig.10 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; amplifier a. VDS ( a )=VDS (b) = 5 V; VG1-S (b) = 0 V; fw = 50 MHz; funw = 60 MHz; Tamb =2 5°C; see Fig.13.

2003 Sep 30 10

Philips Semiconductors Product speciﬁcation Dual N-channel dual gate MOS-FET BF1205 handbook, halfpage 012 4 VAGC (V) gain reduction (dB) MGX438 Fig.11 Gain reduction as a function of AGC voltage; typical values; amplifier a. VDS ( a )=VDS (b) = 5 V; VG1-S (b) = 0 V; f = 50 MHz; see Fig.13. handbook, halfpage gain reduction (dB) 20 40 MGX439 ID (mA) Fig.12 Drain current as a function of gain reduction; typical values; amplifier a. VDS ( a )=VDS (b) = 5 V; VG1-S (b) = 0 V; f = 50 MHz; Tamb =2 5°C; see Fig.13. handbook, full pagewidth 2.2 mHR G1 150 kW 10 kW R GEN 50 W Vi 2.2 mH MGX440 d (a) s d (b) g1 (a) g1 (b) 4.7 nF 4.7 nF 4.7 nF 4.7 nF 4.7 nF BF1205 4.7 nF R L 50 W 50 W 50 W VDS (a) 5 V VDS (b) 5 V VGG 0 V VAGC Fig.13 Cross-modulation test set-up for amplifier a.

2003 Sep 30 11

Philips Semiconductors Product speciﬁcation Dual N-channel dual gate MOS-FET BF1205 handbook, halfpage MGX441 102 10 102 103 f (MHz) 10-2 10-1 yis (mS) gis bis Fig.14 Input admittance as a function of frequency; typical values; amplifier a. VDS (a) = 5 V; VG2-S (a) = 4 V; VDS ( b )=VG1-S (b) = 0 V; ID (a) = 12 mA. handbook, halfpage MGX442 102 -102 -10 10 10 2 103 f (MHz) |yfs| (mS) j fs (deg) j fs |yfs| Fig.15 Forward transfer admittance and phase as a function of frequency; typical values; amplifier a. VDS (a) = 5 V; VG2-S (a) = 4 V; VDS ( b )=VG1-S (b) = 0 V; ID (a) = 12 mA. handbook, halfpage MGX443 103 102 10 102 103 f (MHz) -102 -10 j rs (deg) -103 |yrs| (mS) jrs |yrs| Fig.16 Reverse transfer admittance and phase as a function of frequency; typical values; amplifier a. VDS (a) = 5 V; VG2-S (a) = 4 V; VDS ( b )=VG1-S (b) = 0 V; ID (a) = 12 mA. handbook, halfpage MGX444 10 102 103 f (MHz) 10-2 10-1 yos (mS) gos bos Fig.17 Output admittance as a function of frequency; typical values; amplifier a. VDS (a) = 5 V; VG2-S (a) = 4 V; VDS ( b )=VG1-S (b) = 0 V; ID (a) = 12 mA.

2003 Sep 30 12

Philips Semiconductors Product speciﬁcation Dual N-channel dual gate MOS-FET BF1205 Scattering parameters: ampliﬁer a VDS (a) = 5 V; VG2-S =4V ; ID (a) = 12 mA; VDS (b) = 0 V; VG-1S (b) = 0 V; Tamb =2 5°C Noise data VDS (a) = 5 V; VG2-S =4V ; ID (a) = 12 mA; VDS (b) = 0 V; VG-1S (b) = 0 V; Tamb =2 5°C DYNAMIC CHARACTERISTICS AMPLIFIER b Common source; Tamb =2 5°C; VG2-S =4V ; VDS =5V ; ID =1 2m A f (MHz) s11 s21 s12 s22 MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) f (MHz) F MIN (dB) GAMMA OPT Rn (Ω )(ratio) (deg) 400 1.1 0.719 16.16 31.18 800 1.2 0.628 32.7 29.74 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT yfs forward transfer admittance Tj=2 5°C 2 63 14 0m S C ig1-ss input capacitance at gate 1 f = 1 MHz − 2.0 2.5 pF C ig2-ss input capacitance at gate 2 f = 1 MHz − 3.3 − pF C oss output capacitance f = 1 MHz − 0.85 − pF C rss reverse transfer capacitance f = 1 MHz − 20 − fF G tr power gain f = 200 MHz; G S = 2 mS; BS =B S(opt); G L = 0.5 mS; BL =B L(opt); note 1 30 34 38 dB f = 400 MHz; GS = 2 mS; BS =B S(opt); G L = 1 mS; BL =B L(opt); note 1 27 31 35 dB f = 800 MHz; GS = 3.3 mS; BS =B S(opt); G L = 1 mS; BL =B L(opt); note 1 22 26 30 dB NF noise ﬁgure f = 10.7 MHz; G S = 20 mS; BS =0 − 4 − dB f = 400 MHz; YS =Y S(opt) − 1.3 1.9 dB f = 800 MHz; YS =Y S(opt) − 1.4 2.1 dB

2003 Sep 30 13

Philips Semiconductors Product speciﬁcation Dual N-channel dual gate MOS-FET BF1205 Notes 1. For the MOS-FET not in use: VG1-S (a) = 0; VDS (a) = 0. 2. Measured in test circuit Fig.30. Xmod cross-modulation input level for k = 1% at 0 dB AGC; fw = 50 MHz; funw = 60 MHz; note 2 90 −− dBµV input level for k = 1% at 10 dB AGC; fw = 50 MHz; funw = 60 MHz; note 2 − 92 − dBµV input level for k = 1% at 40 dB AGC; fw = 50 MHz; funw = 60 MHz; note 2 100 105 − dBµV SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT GRAPHS FOR AMPLIFIER b handbook, halfpage 0.4 0.8 1.2 1.6 VG1-S (V) ID (mA) MGX445 (6) (7) (5)(4) (1) (2) (3) Fig.18 Transfer characteristics; typical values; amplifier b. VDS (b) = 5 V; VDS ( a )=VG1-S (a) = 0 V; Tj=2 5°C. (1) VG2-S =4V . (2) VG2-S = 3.5 V. (3) VG2-S =3V . (4) VG2-S = 2.5 V. (5) VG2-S =2V . (6) VG2-S = 1.5 V. (7) VG2-S =1V . handbook, halfpage 01 0 VDS (V) ID (mA) 648 MGX446 (6) (7) (5) (4) (3) (2) (1) Fig.19 Output characteristics; typical values; amplifier b. VG2-S = 4 V; VDS (a) = VG1-S (a) = 0 V; Tj=2 5°C. (5) VG1-S (b) = 1 V.

2003 Sep 30 14

Philips Semiconductors Product speciﬁcation Dual N-channel dual gate MOS-FET BF1205 handbook, halfpage 0 0.8 0.4 1.6 1.2 2 MGX447 VG1-S (V) IG1 (mA) (7) (5) (4) (6) (3)(2) (1) Fig.20 Gate 1 current as a function of gate 1 voltage; typical values; amplifier b. VDS (b) = 5 V; VDS ( a )=VG1-S (a) = 0 V; Tj=2 5°C. (1) VG2-S =4V . (2) VG2-S = 3.5 V. (3) VG2-S =3V . (4) VG2-S = 2.5 V. (5) VG2-S =2V . (6) VG2-S = 1.5 V. (7) VG2-S =1V . handbook, halfpage ID (mA) 42 0 81 21 6 MGX448 yfs (mS) (5) (4) (3) (2)(1) Fig.21 Forward transfer admittance as a function of drain current; typical values; amplifier b. VDS (b) = 5 V; VDS ( a )=VG1-S (a) = 0 V; Tj=2 5°C. (1) VG2-S =4V . (2) VG2-S = 3.5 V. (3) VG2-S =3V . (4) VG2-S = 2.5 V. (5) VG2-S =2V .

2003 Sep 30 15

Philips Semiconductors Product speciﬁcation Dual N-channel dual gate MOS-FET BF1205 handbook, halfpage 05 0 10 20 30 40 IG1 (mA) ID (mA) MGX449 Fig.22 Drain current as a function of gate 1 current; typical values; amplifier b. VDS (b) = 5 V; VG2-S = 4 V; VDS ( a )=VG1-S (a) = 0 V; Tj=2 5°C. handbook, halfpage VGG (V) 23 4 MGX450 ID (mA) Fig.23 Drain current as a function of gate 1 supply voltage (VGG ); typical values; amplifier b. VDS (b) = 5 V; VG2-S = 4 V; VDS ( a )=VG1-S (a) = 0 V; Tj=2 5°C; RG1 (b) = 150 kΩ (connected to VGG ); see Fig.4.

2003 Sep 30 16

Philips Semiconductors Product speciﬁcation Dual N-channel dual gate MOS-FET BF1205 handbook, halfpage 0246 VGG = VDS (V) ID (mA) MGX451 (6) (7) (8) (5) (4) (3) (2) (1) Fig.24 Drain current as a function of gate 1 (VGG ) and drain supply voltage; typical values; amplifier b. VG2-S = 4 V; VDS (a) = VG1-S (a) = 0 V; Tj=2 5°C; R G1 (b) = 150 kΩ (connected to VGG ); see Fig.4. handbook, halfpage 0246 MGX452 VG2-S (V) ID (mA) (5) (4) (3) (2) (1) Fig.25 Drain current as a function of gate 2 voltage; typical values; amplifier b. VDS (b) = 5 V; VDS ( a )=VG1-S (a) = 0 V; Tj=2 5°C; R G1 (b) = 150 kΩ (connected to VGG ); see Fig.4. (1) VGG = 5.0 V. (2) VGG = 4.5 V. (3) VGG = 4.0 V. (4) VGG = 3.5 V. (5) VGG = 3.0 V.

2003 Sep 30 17

Philips Semiconductors Product speciﬁcation Dual N-channel dual gate MOS-FET BF1205 handbook, halfpage 0246 MGX453 VG2-S (V) IG1 (mA) (5) (4) (3) (2) (1) Fig.26 Gate 1 current as a function of gate 2 voltage; typical values; amplifier b. VDS (b) = 5 V; VDS ( a )=VG1-S (a) = 0 V; Tj=2 5°C; R G1 (b) = 150 kΩ (connected to VGG ); see Fig.4. (1) VGG = 5.0 V. (2) VGG = 4.5 V. (3) VGG = 4.0 V. (4) VGG = 3.5 V. (5) VGG = 3.0 V. handbook, halfpage gain reduction (dB) 120 110 100 20 40 MGX454 Vunw (dBmV) Fig.27 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; amplifier b. VDS (b) = 5 V; VGG = 5 V; VDS ( a )=VG1-S (a) = 0 V; R G1 (b) = 150 kΩ (connected to VGG ); fw = 50 MHz; funw = 60 MHz; Tamb =2 5°C; see Fig.30.

2003 Sep 30 18

Philips Semiconductors Product speciﬁcation Dual N-channel dual gate MOS-FET BF1205 handbook, halfpage 012 4 VAGC (V) gain reduction (dB) MGX455 Fig.28 Typical gain reduction as a function of AGC voltage; amplifier b. VDS (b) = 5 V; VGG = 5 V; VDS ( a )=VG1-S (a) = 0 V; R G1 (b) = 150 kΩ (connected to VGG ); f = 50 MHz; Tamb =2 5°C; see Fig.30. handbook, halfpage gain reduction (dB) 20 40 MGX456 ID (mA) Fig.29 Drain current as a function of gain reduction; typical values; amplifier b. VDS (b) = 5 V; VGG = 5 V; VDS ( a )=VG1-S (a) = 0 V; R G1 (b) = 150 kΩ (connected to VGG ); f = 50 MHz; Tamb =2 5°C; see Fig.30.

2003 Sep 30 19

Philips Semiconductors Product speciﬁcation Dual N-channel dual gate MOS-FET BF1205 handbook, full pagewidth 2.2 mHR G1 150 kW 10 kW L1 2.2 mH MDB813 d (a) s d (b) g1 (a) g1 (b) 4.7 nF 4.7 nF 4.7 nF 4.7 nF BF1205 4.7 nF R L

50 W50 WR GEN

VDS (a) 5 V VDS (b) 5 V VGG 5 V VAGC Fig.30 Cross-modulation test set-up for amplifier b. handbook, halfpage MGX457 102 10 102 103 f (MHz) 10-1 yis (mS) gis bis Fig.31 Input admittance as a function of frequency; typical values; amplifier b. VDS (b) = 5 V; VG2-S = 4 V; VDS ( a )=VG1-S (a) = 0 V; ID (b)= 12 mA. handbook, halfpage MGX458 102 -102 -10 10 10 2 103 f (MHz) |yfs| (mS) j fs (deg) j fs |yfs| Fig.32 Forward transfer admittance and phase as a function of frequency; typical values; amplifier b. VDS (b) = 5 V; VG2-S = 4 V; VDS ( a )=VG1-S (a) = 0 V; ID (b) = 12 mA.

2003 Sep 30 20

Philips Semiconductors Product speciﬁcation Dual N-channel dual gate MOS-FET BF1205 handbook, halfpage MGX459 103 102 10 102 103 f (MHz) -102 -10 j rs (deg) -103 |yrs| (mS) |yrs| jrs Fig.33 Reverse transfer admittance and phase as a function of frequency; typical values; amplifier b. VDS (b) = 5 V; VG2-S = 4 V; VDS ( a )=VG1-S (a) = 0 V; ID (b) = 12 mA. handbook, halfpage MGX460 10 102 103 f (MHz) 10-2 10-1 yos (mS) gos bos Fig.34 Output admittance as a function of frequency; typical values; amplifier b. VDS (b) = 5 V; VG2-S = 4 V; VDS ( a )=VG1-S (a) = 0 V; ID (b) = 12 mA.

2003 Sep 30 21

Philips Semiconductors Product speciﬁcation Dual N-channel dual gate MOS-FET BF1205 Scattering parameters: ampliﬁer b VDS (b) = 5 V; VG2-S =4V ; ID (b) = 12 mA; VDS (a) = 0 V; VG1-S (a) = 0 V; Tamb =2 5°C Noise data VDS (b) = 5 V; VG2-S =4V ; ID (b) = 12 mA; VDS (a) = 0 V; VG1-S (a) = 0 V; Tamb =2 5°C f (MHz) s11 s21 s12 s22 MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) f (MHz) F MIN (dB) F MIN (dB) R n (Ω ) (ratio) (deg) 400 1.3 0.662 16.76 31.55 800 1.4 0.578 33.97 30.53

2003 Sep 30 22

Philips Semiconductors Product speciﬁcation Dual N-channel dual gate MOS-FET BF1205 PACKAGE OUTLINE REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ SOT363 SC-88 wB Mbp D e pin 1 index A Lp Q detail X H E E v M A AB y 0 1 2 mm scale c X 13 2 456 Plastic surface mounted package; 6 leads SOT363 UNIT A 1 max bp cD E e1 H E Lp Qy wv mm 0.1 0.30 0.20 2.2 1.8 0.25 0.10 1.35 1.15 0.65 e 1.3 2.2 2.0 0.2 0.10.2 DIMENSIONS (mm are the original dimensions) 0.45 0.15 0.25 0.15 A 1.1 0.8 97-02-28

2003 Sep 30 23

Philips Semiconductors Product speciﬁcation Dual N-channel dual gate MOS-FET BF1205 DATA SHEET STATUS Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. LEVEL DATA SHEET STATUS (1) PRODUCT STATUS (2)(3) DEFINITION I Objective data Development This data sheet contains data from the objective speciﬁcation for product development. Philips Semiconductors reserves the right to change the speciﬁcation in any manner without notice. II Preliminary data Qualiﬁcation This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN). DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

© Koninklijke Philips Electronics N.V. 2003 SCA75 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 Printed in The Netherlands R77/01/pp24 Date of release:2003 Sep 30 Document order number: 9397 750 11784

Product Information

BF1205 specifications and overview.

Summary

Dual N-channel dual gate MOS-FET

Description

Dual N-channel dual gate MOS-FET

Source title BF1205 Datasheet(PDF) - Quanzhou Jinmei Electronic Co.,Ltd.

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