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Product speciﬁcation Supersedes data of 1999 Dec 01

2000 Mar 29

BF1202; BF1202R; BF1202WR N-channel dual-gate PoLo MOS-FETs

2000 Mar 29 2

Philips Semiconductors Product speciﬁcation N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR

FEATURES

Short channel transistor with high forward transfer admittance to input capacitance ratio
Low noise gain controlled amplifier
Partly internal self-biasing circuit to ensure good cross-modulation performance during AGC and good DC stabilization.

APPLICATIONS

VHF and UHF applications with 3 to 9 V supply voltage, such as digital and analogue television tuners and professional communications equipment.

DESCRIPTION

Enhancement type N-channel field-effect transistor with source and substrate interconnected. Integrated diodes between gates and source protect against excessive input voltage surges. The BF1202, BF1202R and BF1202WR are encapsulated in the SOT143B, SOT143R and SOT343R plastic packages respectively. PINNING PIN DESCRIPTION 1 source 2 drain 3 gate 2 4 gate 1 handbook, 2 columns Top view MSB014 Fig.1 Simplified outline (SOT143B). BF1202 marking code: LDp handbook, 2 columns Top view MSB035 Fig.2 Simplified outline (SOT143R). BF1202R marking code: LEp page Top view MSB842 Fig.3 Simplified outline (SOT343R). BF1202WR marking code: LE QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDS drain-source voltage −− 10 V ID drain current −− 30 mA Ptot total power dissipation −− 200 mW yfs forward transfer admittance 25 30 40 mS C ig1-ss input capacitance at gate 1 − 1.7 2.2 pF C rss reverse transfer capacitance f = 1 MHz − 15 30 fF F noise ﬁgure f = 800 MHz − 1.1 1.8 dB Xmod cross-modulation input level for k = 1% at 40 dB AGC 100 105 − dBµV Tj operating junction temperature −− 150 °C CAUTION This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B.

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Philips Semiconductors Product speciﬁcation N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). Note 1. Ts is the temperature of the soldering point of the source lead. THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS drain-source voltage − 10 V ID drain current − 30 mA IG1 gate 1 current −± 10 mA IG2 gate 2 current −± 10 mA Ptot total power dissipation BF1202; BF1202R T s ≤ 113 °C; note 1 − 200 mW BF1202WR T s ≤ 119 °C; note 1 − 200 mW Tstg storage temperature −65 +150 °C Tj operating junction temperature − 150 °C SYMBOL PARAMETER VALUE UNIT R th j-s thermal resistance from junction to soldering point BF1202; BF1202R 185 K/W BF1202WR 155 K/W handbook, halfpage 05 0 (1)(2) Ts (°C) Ptot (mW) 100 200 250 200 150 150 100 MCD951 Fig.4 Power derating curve. (1) BF1202WR. (2) BF1202; BF1202R.

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Philips Semiconductors Product speciﬁcation N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR STATIC CHARACTERISTICS Tj=2 5°C unless otherwise speciﬁed. Note 1. R G1 connects G1 to VGG =5V . DYNAMIC CHARACTERISTICS Common source; Tamb =2 5°C; VG2-S =4V ; VDS =5V ; ID = 12 mA; unless otherwise speciﬁed. Note 1. Measured in Fig.21 test circuit. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V(BR)DSS drain-source breakdown voltage VG1-S =V G2-S = 0; ID =1 0µA1 0 − V V(BR)G1-SS gate 1-source breakdown voltage VG2-S =V DS = 0; IG1-S =1 0m A 6 − V V(BR)G2-SS gate 2-source breakdown voltage VG1-S =V DS = 0; IG2-S =1 0m A 6 − V V(F)S-G1 forward source-gate 1 voltage V G2-S =V DS = 0; IS-G1 = 10 mA 0.5 1.5 V V(F)S-G2 forward source-gate 2 voltage V G1-S =V DS = 0; IS-G2 = 10 mA 0.5 1.5 V VG1-S(th) gate 1-source threshold voltage VG2-S =4V ; VDS =5V ; ID = 100µA 0.3 1.0 V VG2-S(th) gate 2-source threshold voltage VG1-S =5V ; VDS =5V ; ID = 100µA 0.3 1.2 V IDSX drain-source current V G2-S =4V ; VDS =5V ; RG1 = 120 kΩ ; note 1 81 6 m A IG1-SS gate 1 cut-off current V G2-S =V DS = 0; VG1-S =5V − 50 nA IG2-SS gate 2 cut-off current V G1-S =V DS = 0; VG2-S =4V − 20 nA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT yfs forward transfer admittance pulsed; Tj=2 5°C 2 53 04 0m S C ig1-ss input capacitance at gate 1 f = 1 MHz − 1.7 2.2 pF C ig2-ss input capacitance at gate 2 f = 1 MHz − 1 − pF C oss output capacitance f = 1 MHz − 0.85 − pF C rss reverse transfer capacitance f = 1 MHz − 15 30 fF F noise ﬁgure f = 10.7 MHz; G S = 20 mS; BS =0 − 91 1 d B f = 400 MHz; YS =Y S opt − 0.9 1.5 dB f = 800 MHz; YS =Y S opt − 1.1 1.8 dB G tr power gain f = 200 MHz; G S = 2 mS; BS =B S opt; G L = 0.5 mS; BL =B L opt − 34.5 − dB f = 400 MHz; GS = 2 mS; BS =B S opt; G L = 1 mS; BL =B L opt − 30.5 − dB f = 800 MHz; GS = 3.3 mS; BS =B S opt; G L = 1 mS; BL =B L opt − 26.5 − dB Xmod cross-modulation input level for k = 1%; f w = 50 MHz; funw = 60 MHz; note 1 at 0 dB AGC 90 −− dBµV at 10 dB AGC − 92 − dBµV at 40 dB AGC 100 105 − dBµV

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Philips Semiconductors Product speciﬁcation N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR handbook, halfpage 0.4 0.8 1.2 1.6 VG1-S (V) ID (mA) MCD952 VG2-S = 4 V 2.5 V 3.5 V

3 V 2 V

1.5 V 1 V Fig.5 Transfer characteristics; typical values. VDS =5V . Tj=2 5°C. handbook, halfpage 01 0 VDS (V) ID (mA) 648 MCD953 VG1-S = 1.5 V 1.4 V 1.2 V 1.3 V 1.1 V 1 V 0.9 V Fig.6 Output characteristics; typical values. VG2-S =4V . Tj=2 5°C. handbook, halfpage 0 2.5 100 0.5 1 1.5 2 VG1-S (V) IG1 (µA) MCD954 VG2-S = 4 V 3.5 V 3 V 2.5 V 2 V 1.5 V 1 V Fig.7 Gate 1 current as a function of gate 1 voltage; typical values. VDS =5V . Tj=2 5°C. VDS =5V . Tj=2 5°C. handbook, halfpage ID (mA) 42 0 81 21 6 MCD955 yfs (mS) 3.5 V 2.5 V 3 V 2 V VG2-S = 4 V Fig.8 Forward transfer admittance as a function of drain current; typical values. VDS =5V . Tj=2 5°C.

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Philips Semiconductors Product speciﬁcation N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR handbook, halfpage 05 0 10 20 30 40 IG1 (µA) ID (mA) MCD956 Fig.9 Drain current as a function of gate 1 current; typical values. VDS = 5 V; VG2-S =4V . Tj=2 5°C. handbook, halfpage VGG (V) 23 4 MCD957 ID (mA) Fig.10 Drain current as a function of gate 1 supply voltage (= VGG ); typical values. VDS = 5 V; VG2-S = 4 V; Tj=2 5°C. R G1 = 120 kΩ (connected to VGG ); see Fig.21. handbook, halfpage 0246 VGG = VDS (V) ID (mA) MCD958 R G1 = 68 kΩ 82 kΩ 100 kΩ 120 kΩ 150 kΩ 220 kΩ 180 kΩ Fig.11 Drain current as a function of gate 1 (= VGG ) and drain supply voltage; typical values. VG2-S = 4 V; Tj=2 5°C. R G1 connected to VGG ; see Fig.21. handbook, halfpage 0246 MCD959 VG2-S (V) ID (mA) 4.5 V 4 V 3 V VGG = 5 V 3.5 V VDS = 5 V; Tj=2 5°C. R G1 = 120 kΩ (connected to VGG ); see Fig.21. Fig.12 Drain current as a function of gate 2 voltage; typical values.

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Philips Semiconductors Product speciﬁcation N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR handbook, halfpage 0246 MCD960 VG2-S (V) IG1 (µA) 4 V 3.5 V 3 V 4.5 V VGG = 5 V Fig.13 Gate 1 current as a function of gate 2 voltage; typical values. VDS = 5 V; Tj=2 5°C. R G1 = 120 kΩ (connected to VGG ); see Fig.21. handbook, halfpage 012 4 −50 −10

3 VAGC (V)

(dB) −20 −30 −40 MCD961 Fig.14 Typical gain reduction as a function of the AGC voltage; see Fig.21. VDS = 5 V; VGG = 5 V; RG1 = 120 kΩ ; f = 50 MHz; Tamb =2 5°C. handbook, halfpage gain reduction (dB) 10 50 120 110 100 20 30 40 MCD962 Vunw (dBµV) Fig.15 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; Fig.21. VDS = 5 V; VGG = 5 V; RG1 = 120 kΩ ; f= 50 MHz; funw = 60 MHz; Tamb =2 5°C. handbook, halfpage gain reduction (dB) 10 50 20 30 40 MCD963 ID (mA) Fig.16 Drain current as a function of gain reduction; typical values; see Fig.21. VDS = 5 V; VGG = 5 V; RG1 = 120 kΩ ; f = 50 MHz; Tamb =2 5°C.

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Philips Semiconductors Product speciﬁcation N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR handbook, halfpage MCD964 f (GHz) Yis (mS) 102 103 102 10−1 bis gis Fig.17 Input admittance as a function of frequency; typical values. VDS = 5 V; VG2 =4V . ID = 12 mA; Tamb =2 5°C. handbook, halfpage MCD965 f (MHz) 102 103 103 102 −103 −102 −10 yrs (µS) ϕrs (deg) ϕrs yrs Fig.18 Reverse transfer admittance and phase as a function of frequency; typical values. VDS = 5 V; VG2 =4V . ID = 12 mA; Tamb =2 5°C. handbook, halfpage 102 −102 −10 MCD966 10 10 2 103 f (MHz) yfs (mS) ϕfs (deg)yfs ϕfs Fig.19 Forward transfer admittance and phase as a function of frequency; typical values. VDS = 5 V; VG2 =4V . ID = 12 mA; Tamb =2 5°C. handbook, halfpage MCD967 bos f (MHz) Yos (mS) 102 103 10−2 10−1 gos Fig.20 Output admittance as a function of frequency; typical values. VDS = 5 V; VG2 =4V . ID = 12 mA; Tamb =2 5°C.

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Philips Semiconductors Product speciﬁcation N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR handbook, full pagewidth DUT 4.7 nF 10 kΩ MGS315 4.7 nF ≈ 2.2 µH 4.7 nF R L 50 Ω VGG VAGC VDS R GEN 50 Ω VI 50 Ω 4.7 nF R G1 Fig.21 Cross-modulation test set-up. Table 1 Scattering parameters: VDS =5V ; VG2-S =4V ; ID = 12 mA; Tamb =2 5°C Table 2 Noise data: VDS =5V ; VG2-S =4V ; ID = 12 mA; Tamb =2 5°C f (MHz) s11 s21 s12 s22 MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) f (MHz) Fmin (dB) Γopt R n (Ω )(ratio) (deg) 400 0.9 0.805 28.5 50 800 1.1 0.725 47.2 40

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Philips Semiconductors Product speciﬁcation N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR PACKAGE OUTLINES UNIT A REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm 1.1 0.9 A 1 max 0.1 0.88 0.78 c 0.15 0.09 D 3.0 2.8 E 1.4 1.2 H E ywvQ 2.5 2.1 0.45 0.15 0.55 0.45 e 1.9 1.7 Lp 0.1 0.10.2 bp 0.48 0.38 DIMENSIONS (mm are the original dimensions) SOT143B 97-02-28 0 1 2 mm scale Plastic surface mounted package; 4 leads SOT143B D H E E AB v M A X A Lp Q detail X c y w M e B bp

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Philips Semiconductors Product speciﬁcation N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR UNIT A REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm 1.1 0.9 A 1 max 0.1 0.88 0.78 c 0.15 0.09 D 3.0 2.8 E 1.4 1.2 H E ywvQ 2.5 2.1 0.55 0.25 0.45 0.25 e 1.9 1.7 Lp 0.1 0.10.2 bp 0.48 0.38 DIMENSIONS (mm are the original dimensions) SOT143R SC-61B 97-03-10 99-09-13 0 1 2 mm scale Plastic surface mounted package; reverse pinning; 4 leads SOT143R D H E E AB v M A X A Lp Q detail X c y w M e B bp

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Philips Semiconductors Product speciﬁcation N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ SOT343R D A Lp Q detail X c H E E v M A AB 0 1 2 mm scale X Plastic surface mounted package; reverse pinning; 4 leads SOT343R w M B 97-05-21 bp UNIT A 1 max bp cD Eb1 H E Lp Qw v mm 0.11.1 0.8 0.4 0.3 0.25 0.10 0.7 0.5 2.2 1.8 1.35 1.15 e 2.2 2.01.3 0.2 y 0.10.21.15 DIMENSIONS (mm are the original dimensions) 0.45 0.15 0.23 0.13 A e y

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Philips Semiconductors Product speciﬁcation N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR DATA SHEET STATUS Note 1. Please consult the most recently issued data sheet before initiating or completing a design. DATA SHEET STATUS PRODUCT STATUS DEFINITIONS (1) Objective speciﬁcation Development This data sheet contains the design target or goal speciﬁcations for product development. Speciﬁcation may change in any manner without notice. Preliminary speciﬁcation Qualiﬁcation This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product speciﬁcation Production This data sheet contains ﬁnal speciﬁcations. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

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Philips Semiconductors Product speciﬁcation N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR NOTES

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Philips Semiconductors Product speciﬁcation N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR NOTES

© Philips Electronics N.V. SCA All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Internet: http://www.semiconductors.philips.com 2000 69 Philips Semiconductors – a worldwide company For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria:Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil:see South America Bulgaria:Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre,

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Product Information

BF1202 specifications and overview.

Summary

N-channel dual-gate PoLo MOS-FETs

Description

N-channel dual-gate PoLo MOS-FETs

Source title BF1202_15 Datasheet(PDF) - Quanzhou Jinmei Electronic Co.,Ltd.

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