BF1109_15 JMNIC | Alldatasheet
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Technical content
Product specification Supersedes data of 1997 Sep 03 File under Discrete Semiconductors, SC07
1997 Dec 08
BF1109; BF1109R; BF1109WR N-channel dual-gate MOS-FETs
1997 Dec 08 2
Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR
FEATURES
- Short channel transistor with high forward transfer admittance to input capacitance ratio
- Low noise gain controlled amplifier up to 1 GHz
- Internal self-biasing circuit to ensure good cross-modulation performance during AGC and good DC stabilization.
APPLICATIONS
- VHF and UHF applications with 9 V supply voltage, such as television tuners and professional communications equipment.
DESCRIPTION
Enhancement type N-channel field-effect transistor with source and substrate interconnected. Integrated diodes between gates and source protect against excessive input voltage surges. The BF1109, BF1109R and BF1109WR are encapsulated in the SOT143B, SOT143R and SOT343R plastic packages respectively. PINNING PIN DESCRIPTION 1 source 2 drain 3 gate 2 4 gate 1 Fig.1 Simplified outline (SOT143B). BF1109 marking code: NFp. Top view MSB014 Fig.2 Simplified outline (SOT143R). BF1109R marking code: NBp. handbook, 2 columns Top view MSB035 Fig.3 Simplified outline (SOT343R). BF1109WR marking code: NB. fpage Top view MSB842 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDS drain-source voltage −− 11 V ID drain current (DC) −− 30 mA Ptot total power dissipation T amb ≤ 80 °C −− 200 mW yfs forward transfer admittance − 30 − mS C ig1-ss input capacitance at gate 1 − 2.2 2.7 pF C rss reverse transfer capacitance f = 1 MHz − 25 40 fF F noise figure f = 800 MHz − 1.5 2.5 dB Xmod cross-modulation input level for k = 1% at 40 dB AGC 100 −− dBµV Tj operating junction temperature −− 150 °C CAUTION This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B.
1997 Dec 08 3
Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). Note 1. Device mounted on a printed-circuit board. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS drain-source voltage − 11 V ID drain current (DC) − 30 mA IG1 gate 1 current −± 10 mA IG2 gate 2 current −± 10 mA Ptot total power dissipation T amb ≤ 80 °C; note 1 − 200 mW Tstg storage temperature −65 +150 °C Tj operating junction temperature − +150 °C Fig.4 Power derating curve. handbook, halfpage 0 40 80 160 250 200 MGM243 120 150 100 Ptot (mW) Tamb (°C)
1997 Dec 08 4
Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR THERMAL CHARACTERISTICS Note 1. Device mounted on a printed-circuit board. STATIC CHARACTERISTICS Tj=2 5°C unless otherwise specified. DYNAMIC CHARACTERISTICS Common source; Tamb =2 5°C; VG2-S = 4 V; VDS = 9 V; self-biasing current; unless otherwise specified. SYMBOL PARAMETER CONDITIONS VALUE UNIT R th j-a thermal resistance from junction to ambient in free air note 1 350 K/W R th j-s thermal resistance from junction to soldering point 200 K/W SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V(BR)DSS drain-source breakdown voltage VG1-S =V G2-S = 0; ID =1 0µA1 1 − V V(BR)G1-SS gate 1-source breakdown voltage VG2-S = 0; IG1-S =1 0µA; ID =0 1 1 − V V(BR)G2-SS gate 2-source breakdown voltage VG1-S =V DS = 0; IG2-S =1 0µA1 1 − V VG2-S (th) gate 2-source threshold voltage VG1-S =9V ; VDS =9V ; ID =2 0µA 0.3 1.2 V IDSX self-biasing drain current V G2-S =4V ; VDS = 9 V 8 16 mA IG1-SS gate 1 cut-off current V G1-S =9V ; VG2-S = 0; ID =0 − 20 nA IG2-SS gate 2 cut-off current V G1-S =V DS = 0; VG2-S =9V − 20 nA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT yfs forward transfer admittance pulsed; Tj=2 5°C2 4 3 0 − mS C ig1-ss input capacitance at gate 1 f = 1 MHz − 2.2 2.7 pF C ig2-ss input capacitance at gate 2 f = 1 MHz − 1.5 − pF C oss output capacitance f = 1 MHz − 1.3 − pF C rss reverse transfer capacitance f = 1 MHz − 25 40 fF F noise figure f = 800 MHz; Y S =Y S opt − 1.5 2.5 dB G p power gain G S = 2 mS; BS =B S opt; GL = 0.5 mS; BL =B L opt; f = 200 MHz; see Fig.16 − 38 − dB G S = 3.3 mS; BS =B S opt; GL = 1 mS; BL =B L opt; f = 800 MHz; see Fig.17 − 20 − dB Xmod cross-modulation input level for k = 1% at 0 dB AGC; fw = 50 MHz; funw = 60 MHz; see Fig.18 85 −− dBµV input level for k = 1% at 40 dB AGC; fw = 50 MHz; funw = 60 MHz; see Fig.18 100 −− dBµV
1997 Dec 08 5
Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR Fig.5 Output characteristics; typical values. VG2-S =4V . Tj=2 5°C. handbook, halfpage 01 0 24 6 8 MDA613 ID (mA) VDS (V) VG1 = 1.6 V 1.3 V 1.2 V 1.1 V 1.5 V 1.4 V 1 V Fig.6 Transfer characteristics; typical values. VDS =9V . Tj=2 5°C. handbook, halfpage 0.5 2.5 MDA614 1 1.5 2 VG1 (V) ID (mA) 2 V 1 V VG2-S = 4 V 3.5 V 2.5 V 1.5 V 3 V Fig.7 Forward transfer admittance as a function of drain current; typical values. VDS =9V . Tj=2 5°C. handbook, halfpage 0 1 02 03 0 MDA615 ID (mA) yfs (mS) 3.5 V 3 V
2.5 V2 V
VG2-S = 4 V Fig.8 Drain current as a function of gate 2 voltage; typical values. (1) VDS =9V . (2) VDS =7V . (3) VDS =5V . (4) VDS =3V . handbook, halfpage MDA616 234 ID (mA) VG2-S (V) (1) (4) (3)(2)
1997 Dec 08 6
Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR Fig.9 Drain current as a function of drain-source voltage; typical values. VG2-S =4V . Tj=2 5°C. handbook, halfpage 02 1 0 46 8 MDA617 ID (mA) VDS (V) Fig.10 Drain current as a function of gate 1 current; typical values. VDS = 9 V; VG2-S = 4 V; Tj=2 5°C. handbook, halfpage −8 −6 −40 MDA618 ID (mA) IG1 (µA) VDS = 9 V; VG2nom = 4 V; IDnom = 12 mA; fw = 50 MHz; funw = 60 MHz; Tamb =2 5°C. Fig.11 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values (see Fig.18). handbook, halfpage 02 0 Vunw (dBµV) gain reduction (dB) 40 60 120 110 100 MDA619
1997 Dec 08 7
Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR Fig.12 Input admittance as a function of frequency; typical values. VDS = 9 V; VG2-S =4V . ID = 12 mA; Tamb =2 5°C. handbook, halfpage MDA620 102 10−2 10 102 103 10−1 f (MHz) yis (mS) gis bis Fig.13 Reverse transfer admittance and phase as a function of frequency; typical values. VDS = 9 V; VG2-S =4V . ID = 12 mA; Tamb =2 5°C. handbook, halfpage MDA621 103 102 10 102 103 f (MHz) |yrs| (mS) ϕrs (deg) −103 −10 −102 ϕrs |yrs| Fig.14 Forward transfer admittance and phase as a function of frequency; typical values. VDS = 9 V; VG2-S =4V . ID = 12 mA; Tamb =2 5°C. handbook, halfpage MDA622 102 ϕfs (deg) −102 −1010 10 10 2 103 f (MHz) |yfs| (mS) ϕfs |yfs| Fig.15 Output admittance as a function of frequency; typical values. VDS = 9 V; VG2-S =4V . ID = 12 mA; Tamb =2 5°C. handbook, halfpage MDA623 10−1 10−2 10 102 103 f (MHz) yos (mS) bos gos
1997 Dec 08 8
Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR Fig.16 Gain test circuit. VDS = 9 V, GS = 2 mS, GL = 0.5 mS, f = 200 MHz. L1 = 45 nH, 4 turns, internal diameter = 4 mm, 0.8 mm copper wire. L2 = 160 nH, 3 turns, internal diameter = 8 mm, 0.8 mm copper wire; tapped at approximately half a turn from the cold side, to set G L = 0.5 mS. C1 adjusted for GS = 2 mS. handbook, full pagewidth BF1109 BF1109R BF1109WR MDA624 330 kΩ 47 kΩ pF 5.5 pF 1 nF 1 nF 1 nF 1 nF 1 nF 1 nF VAGC VDS S D 1 nF 330 kΩ 1 nF BB405 10 pF BB405 input 50 Ω Vtun input output 50 Ω Vtun output 2 µH Fig.17 Gain test circuit. VDS = 9 V, GS = 3.3 mS, GL = 1 mS, f = 800 MHz. L1 = 2 cm, silvered 0.8 mm copper wire 4 mm above ground plane. L2 = 2 cm, silvered 0.8 mm copper wire 4 mm above ground plane. L3 = 11 turns 0.5 mm copper wire without spacing, internal diameter = 3 mm, L = approx. 200 nH. handbook, full pagewidth input 50 Ω output 50 ΩBF1109 BF1109R BF1109WR MDA625 47 kΩ 0.5 to 3.5 pF 1 nF 1 nF1 nF 1 nF VAGC VDS S D /,/,/, 2 to 18 pF 4 to 40 pF /,/,/,/, /,/,/,/, 0.5 to 3.5 pF 1 nF
1997 Dec 08 9
Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR Fig.18 Cross-modulation test set-up. handbook, full pagewidth BF1109 BF1109R BF1109WR MDA626 R gen 50 Ω 50 Ω R1 = 50 Ω 10 kΩ D S10 nF Vi 10 nF4.7 nF 47 µH 4.7 nF VG2 VDS Table 1 Scattering parameters: VDS = 9 V; VG2-S = 4 V; ID =1 2m A Table 2 Noise data: VDS = 9 V; VG2-S = 4 V; ID =1 2m A f (MHz) S11 S21 S12 S22 MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) f (MHz) Fmin (dB) Γopt R n (Ω )(ratio) (deg) 800 1.5 0.684 40.94 40.4
1997 Dec 08 10
Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR PACKAGE OUTLINES UNIT A REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm 1.1 0.9 A 1 max 0.1 0.88 0.78 c 0.15 0.09 D 3.0 2.8 E 1.4 1.2 H E ywvQ 2.5 2.1 0.45 0.15 0.55 0.45 e 1.9 1.7 Lp 0.1 0.10.2 bp 0.48 0.38 DIMENSIONS (mm are the original dimensions) SOT143B 97-02-28 0 1 2 mm scale Plastic surface mounted package; 4 leads SOT143B D H E E AB v M A X A Lp Q detail X c y w M e B bp
1997 Dec 08 11
Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR UNIT A REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm 1.1 0.9 A 1 max 0.1 0.88 0.78 c 0.15 0.09 D 3.0 2.8 E 1.4 1.2 H E ywvQ 2.5 2.1 0.55 0.25 0.45 0.25 e 1.9 1.7 Lp 0.1 0.10.2 bp 0.48 0.38 DIMENSIONS (mm are the original dimensions) SOT143R 97-03-10 0 1 2 mm scale Plastic surface mounted package; reverse pinning; 4 leads SOT143R D H E E AB v M A X A Lp Q detail X c y w M e B bp
1997 Dec 08 12
Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ SOT343R D A Lp Q detail X c H E E v M A AB 0 1 2 mm scale X Plastic surface mounted package; reverse pinning; 4 leads SOT343R w M B 97-05-21 bp UNIT A 1 max bp cD Eb1 H E Lp Qw v mm 0.11.1 0.8 0.4 0.3 0.25 0.10 0.7 0.5 2.2 1.8 1.35 1.15 e 2.2 2.01.3 0.2 y 0.10.21.15 DIMENSIONS (mm are the original dimensions) 0.45 0.15 0.23 0.13 A e y
1997 Dec 08 13
Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR DEFINITIONS LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. Data Sheet Status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
1997 Dec 08 14
Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR NOTES
1997 Dec 08 15
Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR NOTES
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