BF1101_15 JMNIC | Alldatasheet
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Technical content
Product specification Supersedes data of 1999 Feb 01
1999 May 14
BF1101; BF1101R; BF1101WR N-channel dual-gate MOS-FETs
1999 May 14 2
Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR
FEATURES
- Short channel transistor with high forward transfer admittance to input capacitance ratio
- Low noise gain controlled amplifier up to 1 GHz
- Partly internal self-biasing circuit to ensure good cross-modulation performance during AGC and good DC stabilization.
APPLICATIONS
- VHF and UHF applications with 3 to 7 V supply voltage, such as television tuners and professional communications equipment.
DESCRIPTION
Enhancement type N-channel field-effect transistor with source and substrate interconnected. Integrated diodes between gates and source protect against excessive input voltage surges. The BF1101, BF1101R and BF1101WR are encapsulated in the SOT143B, SOT143R and SOT343R plastic packages respectively. PINNING PIN DESCRIPTION 1 source 2 drain 3 gate 2 4 gate 1 Fig.1 Simplified outline (SOT143B). BF1101 marking code: NDp. handbook, 2 columns Top view MSB014 Fig.2 Simplified outline (SOT143R). BF1101R marking code: NCp. handbook, 2 columns Top view MSB035 Fig.3 Simplified outline (SOT343R). BF1101WR marking code: NC. fpage Top view MSB842 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDS drain-source voltage −− 7V ID drain current −− 30 mA Ptot total power dissipation −− 200 mW yfs forward transfer admittance 25 30 − mS C ig1-ss input capacitance at gate 1 − 2.2 2.7 pF C rss reverse transfer capacitance f = 1 MHz − 25 35 fF F noise figure f = 800 MHz − 1.7 2.5 dB Xmod cross-modulation input level for k = 1% at 40 dB AGC 100 −− dBµV Tj operating junction temperature −− 150 °C CAUTION This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B.
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Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). Note 1. Ts is the temperature of the soldering point of the source lead. THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS drain-source voltage − 7V ID drain current − 30 mA IG1 gate 1 current −± 10 mA IG2 gate 2 current −± 10 mA Ptot total power dissipation T s ≤ 110 °C; note 1 − 200 mW Tstg storage temperature −65 +150 °C Tj operating junction temperature − +150 °C SYMBOL PARAMETER VALUE UNIT R th j-s thermal resistance from junction to soldering point 200 K/W Fig.4 Power derating curve. handbook, halfpage 0 50 100 200 250 200 MGL615 150 150 100 Ptot (mW) Ts (°C)
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Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR STATIC CHARACTERISTICS Tj=2 5°C unless otherwise specified. Note 1. R G1 connects G1 to VGG = 5 V; see Fig.21. DYNAMIC CHARACTERISTICS Common source; Tamb =2 5°C; VG2-S = 4 V; VDS = 5 V; ID = 12 mA; unless otherwise specified. Note 1. Measured in test circuit of Fig.21. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V(BR)DSS drain-source breakdown voltage VG1-S =V G2-S = 0; ID =1 0µA7 − V V(BR)G1-SS gate 1-source breakdown voltage VG2-S =V DS = 0; IG1-S = 10 mA 7 16 V V(BR)G2-SS gate 2-source breakdown voltage VG1-S =V DS = 0; IG2-S = 10 mA 7 16 V V(F)S-G1 forward source-gate 1 voltage V G2-S =V DS = 0; IS-G1 = 10 mA 0.5 1.5 V V(F)S-G2 forward source-gate 2 voltage V G1-S =V DS = 0; IS-G2 = 10 mA 0.5 1.5 V VG1-S (th) gate 1-source threshold voltage VG2-S =4V ; VDS =5V ; ID = 100µA 0.3 1.0 V VG2-S (th) gate 2-source threshold voltage VG1-S =5V ; VDS =5V ; ID = 100µA 0.3 1.2 V IDSX drain-source current V G2-S =4V ; VDS =5V ; RG1 = 120 kΩ ; note 1 81 6 m A IG1-SS gate 1 cut-off current V G2-S =V DS = 0; VG1-S =5V − 50 nA IG2-SS gate 2 cut-off current V G1-S =V DS = 0; VG2-S =4V − 20 nA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT yfs forward transfer admittance pulsed; Tj=2 5°C 2 53 04 0m S C ig1-ss input capacitance at gate 1 f = 1 MHz − 2.2 2.7 pF C ig2-ss input capacitance at gate 2 f = 1 MHz − 1.6 − pF C oss output capacitance f = 1 MHz − 1.2 − pF C rss reverse transfer capacitance f = 1 MHz − 25 35 fF F noise figure f = 800 MHz; Y S =Y S opt − 1.7 2.5 dB Xmod cross-modulation input level for k = 1% at 0 dB AGC; fw = 50 MHz; funw = 60 MHz; note 1 85 −− dBµV input level for k = 1% at 40 dB AGC; fw = 50 MHz; funw = 60 MHz; note 1 100 −− dBµV
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Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR Fig.5 Transfer characteristics; typical values. VDS =5V . Tj=2 5°C. handbook, halfpage 0.4 MGS299 0.8 1.2 1.6 2 ID (mA) VG1-S (V) 3.5 V 3 V 2.5 V 2 V 1 V 1.5 V VG2-S = 4 V Fig.6 Output characteristics; typical values. VG2-S =4V . Tj=2 5°C. handbook, halfpage MGS300 468 ID (mA) VDS (V) 1.5 V 1.4 V 1.3 V 1.2 V 1.1 V 1 V VG1-S = 1.6 V Fig.7 Gate 1 current as a function of gate 1 voltage; typical values. VDS =5V . Tj=2 5°C. handbook, halfpage 100 0.5 MGS301 1 1.5 2 2.5 IG1 (µA) VG1-S (V) 3.5 V 3 V 2.5 V 2 V VG2-S = 4 V Fig.8 Forward transfer admittance as a function of drain current; typical values. VDS =5V . Tj=2 5°C. handbook, halfpage 81 641 2 2 0 MGS302 ID (mA) yfs (mS) 3 V 2.5 V 2 V VG2-S = 4 V 3.5 V
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Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR Fig.9 Drain current as a function of gate 1 current; typical values. VDS =5V . VG2-S =4V . Tj=2 5°C. handbook, halfpage MGS303 20 30 40 50 ID (mA) IG1 (µA) Fig.10 Drain current as a function of gate 1 supply voltage (= VGG ); typical values. VDS = 5 V; VG2-S = 4 V; Tj=2 5°C. R G1 = 120 kΩ (connected to VGG ); see Fig.21. handbook, halfpage MGS304 23 5 4 ID (mA) VGG (V) Fig.11 Drain current as a function of gate 1 (= VGG ) and drain supply voltage; typical values. VG2-S = 4 V; Tj=2 5°C. R G1 connected to VGG ; see Fig.21. handbook, halfpage 468 ID (mA) VGG = VDS (V) R G1 = 47 kΩ 68 kΩ 82 kΩ 100 kΩ 120 kΩ 150 kΩ 180 kΩ 220 kΩ MGS305 VDS = 5 V; Tj=2 5°C. R G1 = 120 kΩ (connected to VGG ); see Fig.21. Fig.12 Drain current as a function of gate 2 voltage; typical values. handbook, halfpage MGS306 ID (mA) VG2-S (V) 4.5 V 4 V 3.5 V 3 V VGG = 5 V
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Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR Fig.13 Gate 1 current as a function of gate 2 voltage; typical values. VDS = 5 V; Tj=2 5°C. R G1 = 120 kΩ (connected to VGG ); see Fig.21. handbook, halfpage MGS307 26 4 IG1 (µA) VG2-S (V) 4.5 V 4 V 3.5 V 3 V VGG = 5 V Fig.14 Typical gain reduction as a function of the AGC voltage; see Fig.21. handbook, halfpage −30 −20 −10 −40 −50 MGS308 234 gain reduction (dB) VAGC (V) (2) (1)(3) VDS = 5 V; VGG = 5 V; f = 50 MHz; Tamb =2 5°C. (1) RG1 =6 8kΩ . (2) RG1 = 120 kΩ . (3) RG1 = 180 kΩ . Fig.15 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; see Fig.21. handbook, halfpage 120 100 110 MGS309 20 30 40 50 Vunw (dBµV) gain reduction (dB) (2) (3) (1) VDS = 5 V; VGG = 5 V; f = 50 MHz; funw = 60 MHz; Tamb =2 5°C. (1) RG1 =6 8kΩ . (2) RG1 = 120 kΩ . (3) RG1 = 180 kΩ . Fig.16 Drain current as a function of gain reduction; typical values; see Fig.21. handbook, halfpage MGS310 20 30 40 50 ID (mA) gain reduction (dB) (2) (3) (1) VDS = 5 V; VGG = 5 V; f = 50 MHz; Tamb =2 5°C. (1) RG1 =6 8kΩ . (2) RG1 = 120 kΩ . (3) RG1 = 180 kΩ .
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Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR Fig.17 Input admittance as a function of frequency; typical values. VDS = 5 V; VG2 =4V . ID = 12 mA; Tamb =2 5°C. handbook, halfpage MGS311 102 10−1 10 10 2 103 f (MHz) yis (mS) bis gis Fig.18 Reverse transfer admittance and phase as a function of frequency; typical values. VDS = 5 V; VG2 =4V . ID = 12 mA; Tamb =2 5°C. handbook, halfpage MGS312 102 ϕ rs (deg) −102 −1010 10 10 2 103 f (MHz) |yrs| (mS) |yrs| ϕ rs Fig.19 Forward transfer admittance and phase as a function of frequency; typical values. VDS = 5 V; VG2 =4V . ID = 12 mA; Tamb =2 5°C. handbook, halfpage MGS313 102 ϕ fs (deg) −102 −1010 10 10 2 103 f (MHz) |yfs| (mS) ϕ fs |yfs| Fig.20 Output admittance as a function of frequency; typical values. VDS = 5 V; VG2 =4V . ID = 12 mA; Tamb =2 5°C. handbook, halfpage MGS314 10−1 10 10 2 103 f (MHz) yos (mS) bos gos
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Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR Table 1 Scattering parameters: VDS = 5 V; VG2-S = 4 V; ID = 12 mA; Tamb =2 5°C Table 2 Noise data: VDS = 5 V; VG2-S = 4 V; ID = 12 mA; Tamb =2 5°C f (MHz) S11 S21 S12 S22 MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) f (MHz) Fmin (dB) Γopt R n (Ω )(ratio) (deg) 800 1.5 0.715 58.3 37.85 Fig.21 Cross-modulation test set-up. handbook, full pagewidth DUT 4.7 nF 10 kΩ MGS315 4.7 nF ≈ 2.2 µH 4.7 nF R L 50 Ω VGG VAGC VDS R GEN 50 Ω VI 50 Ω 4.7 nF R G1
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Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR PACKAGE OUTLINES UNIT A REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm 1.1 0.9 A 1 max 0.1 0.88 0.78 c 0.15 0.09 D 3.0 2.8 E 1.4 1.2 H E ywvQ 2.5 2.1 0.45 0.15 0.55 0.45 e 1.9 1.7 Lp 0.1 0.10.2 bp 0.48 0.38 DIMENSIONS (mm are the original dimensions) SOT143B 97-02-28 0 1 2 mm scale Plastic surface mounted package; 4 leads SOT143B D H E E AB v M A X A Lp Q detail X c y w M e B bp
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Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR UNIT A REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm 1.1 0.9 A 1 max 0.1 0.88 0.78 c 0.15 0.09 D 3.0 2.8 E 1.4 1.2 H E ywvQ 2.5 2.1 0.55 0.25 0.45 0.25 e 1.9 1.7 Lp 0.1 0.10.2 bp 0.48 0.38 DIMENSIONS (mm are the original dimensions) SOT143R 97-03-10 0 1 2 mm scale Plastic surface mounted package; reverse pinning; 4 leads SOT143R D H E E AB v M A X A Lp Q detail X c y w M e B bp
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Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ SOT343R D A Lp Q detail X c H E E v M A AB 0 1 2 mm scale X Plastic surface mounted package; reverse pinning; 4 leads SOT343R w M B 97-05-21 bp UNIT A 1 max bp cD Eb1 H E Lp Qw v mm 0.11.1 0.8 0.4 0.3 0.25 0.10 0.7 0.5 2.2 1.8 1.35 1.15 e 2.2 2.01.3 0.2 y 0.10.21.15 DIMENSIONS (mm are the original dimensions) 0.45 0.15 0.23 0.13 A e y
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Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR DEFINITIONS LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. Data Sheet Status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
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Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR NOTES
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Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR NOTES
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