AN901 SILABS | Alldatasheet
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Figure 3. Inductor Currents
4 Rev. 0.1 2.1. S1 Closed VIN is applied to the primary inductance Lm. As a result, current flows through inductance Lm and energy is stored in the magnetic field of the transformer T1: Equation 1. Im,RIPPLE is the magnetizing current ramp during t S1, and t S1 is the time that S1 is closed. In Discontinuous Conduction Mode (DCM), I m,RIPPLE is equal to I m,PK as primary and secondary currents returning to zero before the next cycle. In Continuous Conduction Mode (CCM), the currents do not reach zero before the next switching cycle. 2.2. S1 Open The instant S1 opens, current can no longer flow through the primary and the magnetic field collapses, transferring energy to the secondary, causing current to flow out of the dot of the ideal transformer. The energy stored in the leakage inductance is not transferred and it must be dissipated in the primary through the snubber network. The voltage at the secondary will be impressed on the primary. The governing current equation is: Equation 2. where n and t S2 are primary to secondary turns ratio and time that S1 is open, respectively. VIN Lm ImR I P P L E tS1 Im RIPPLE nV OUT tS2 Lm
Rev. 0.1 5 2.3. Voltage Transfer Let duty cycle D be defined as the ratio of time S1 is closed over the complete switching period Tsw: Equation 3. Now tS1 and tS2 can be expressed in terms of D and switching period as: Equation 4. Equation 5. and assume diode D1 has no voltage drop when conducting the volt-second balance equation for L m, which in CCM operation can be written as: Equation 6. Equation 6 simplifies to: Equation 7. For DCM, current does not flow out of the secondary over the entire (1-D) portion, which changes the voltage transfer function shown in Equation 7. Unlike CCM, the voltage transfer characteristics in DCM are dependent on factors such as R LOAD and switching period. The governing equation is: Equation 8. D tS1 tS1 DTsw= tS2 1D– Tsw= VIN DTsw nVOUT 1D– Tsw– 0= VOUT VIN D VOUT VIN D RLOAD Tsw 2Lm
6 Rev. 0.1 2.4. Magnetizing Current Substituting Equation 4 into Equation 1, the ripple magnetizing current is: Equation 9. The average magnetizing current is related to the output current as: Equation 10. When a flyback converter is operating in CCM, the peak magnetizing current is given by the average current plus one half of the ripple current: Equation 11. When a flyback converter is operating in DCM, the peak magnetizing current is equal to the ripple current: Equation 12. Si884xx/Si886xx controller limits the peak magnetizing current by comparing the voltage across the current sense resistor R12 to an internal reference voltage of approximately 100 mV. If more than 100 mV is developed across R12 during S1 closed, the controller immediately switches S1 open. The controller maintains the same switching period, but reduces the duty cycle D to limit peak current. The cycle by cycle current limit is given by: Equation 13. ImR I P P L E VIN tS1 Lm Lm Im AVE ILOAD ImP KC C M Im AVE VIN DTsw 2Lm ImP KD C M ImR I P P L E= Im LIMIT 100mV
Rev. 0.1 7 2.5. Optional Primary Snubber Snubbers are used for two purposes in a flyback converter: to limit the peak voltage on the drain of the Q1, and to attenuate high frequency ringing that leads to emissions. There are several methods to create a primary side flyback snubber. The RC snubber is presented here. The energy stored in the leakage inductance L lkg does not transfer to the secondary and must be dissipated in the primary. The power dissipated in the leakage inductance is given by: Equation 14. When S1 opens, the current flowing in the primary will charge the drain-source capacitance of Q1 causing the voltage at the drain to increase rapidly. When this voltage exceeds V IN + nVOUT, a ringing occurs with frequency dependent on the inductance leakage L lkg and C ds. The RC snubber presents a load for which to dissipate the power stored in the inductance leakage. This load limits the switching speed of Q1, which limits the peak voltage across the drain-source. A first order approximation for determining R16 and C19 is to set them to the characteristic impedance of the ringing caused by L lkg of T1 and Cds of Q1. Equation 15. R16 can be determined by measuring Llkg and ringing frequency: Equation 16. C19 can be set to the same impedance using: Equation 17. 2.6. Input Capacitor The purpose of C2 input capacitor is to provide filtering for VIN during the switching cycle and reduce voltage ripple at the converter input. Operating in CCM, during tS1 portion of the cycle C2 current is given by: Equation 18. The voltage ripple on C2 can be written as: Equation 19. Plkg Llkg ImP K 2Tsw R16 Z C19 Llkg Cds R16 2 fring Llkg C19 1 IC2 IIN ImA V E– D1– ILOAD VIN RIPPLE IC2 DTsw ILOAD DTsw
primary side is above 5.5 V, Si884xx/Si886xx provides a voltage reference for an external regulator circuit. Q2 and the emitter outputs approximately a 4.3 V supply suitable to power VDDA. Figure 4. External Regulator Circuit
Rev. 0.1 9 2.8. Diode and Output Capacitor In CCM, current flows through D1 only during the (1-D)T sw portion of the steady state cycle. During the DT sw portion of the cycle, I LOAD is sourced solely by the output capacitor C10. Output voltage ripple on C10 can be calculated by: Equation 23. Applying the charge balance of C10, Equation 24. Equation 25. When D1 is reversed biased, it must withstand: Equation 26. 2.9. Optional Secondary Snubber At the instant S1 closes, this reverse voltage applied to D1 can overshoot and ring before settling to V D1,REV(D) as given by Equation 26. A RC snubber can be used to limit the voltage stress across D1. Like the design of the optional primary snubber, a first order approximation for determining R8 and C8 is to set them to the characteristic impedance of the ringing caused by secondary side L lkg of T1 and parasitic capacitance of D1. Equation 27. R8 can be determined by measuring Llkg and ringing frequency: Equation 28. C8 can be set to the same impedance using: Equation 29. VOUT RIPPLE ILOAD DTsw ID1 AVE 1 D– ILOAD VD1 REV D VIN R8 Z C8 Llkg sec CD1 R8 2 fring Llkg sec C8 1
IN, and VOUT of the dc-dc converter. Figure 5. Simplified VOUT Gain Model large R5 could reduce the output voltage accuracy.
Figure 6. VOUT During Start Up
12 Rev. 0.1 3.1. External Soft-Start and Switching Frequency Calibration The Si886xx has two additional external pins compared to Si884xx for setting switching frequency and adjusting soft start time, SH_FC and SS. The capacitor C6 is connected between pin SS and GNDA and sets the soft start time. The resistor R13 is connected between pin SH_FC and GNDA when the dc-dc is operating. Si886xx supports switching frequencies from 200 kHz to 900 kHz, and is set by: Equation 31. A practical C6 value for soft start is: Equation 32. With C6 = 470 nF, R13 range to set acceptable T sw is 2.42 kΩ to 10.9 kΩ. For any given Tsw, soft start time may be increased or decreased by increasing or decreasing C6 while adjusting R13 to maintain the same R13 x C6 time constant. The time spent in calibration mode is approximately the time constant created by R13 and C6. 3.2. Soft Start In soft start mode, the dc-dc peak current limit is gradually increased to limit the sudden demand of current needed from the primary supply. This mode of operation guarantees that VOUT monotonically increases and minimizes the probability of a voltage overshoot. Once 90% of the final V OUT is reached, soft start mode ends, and Proportional (P) Mode starts. The total duration of soft start is load dependent as it affects how many switching cycles are required for V OUT to reach 90% of final value. In this mode of operation, the voltage feedback loop is inactive, and hence, loop stability is not a concern. Tsw R13 C6 C6 470nF=
14 Rev. 0.1 Equation 36. gmea is the error amplifier transconductance. For the Si884xx/Si886xx, gm ea 1x10-3, R INT 100 kΩ, and RO,gmfb » RINT. If R5 and R6 are chosen such that their parallel resistance is sufficiently larger than 1⁄ gmea, Equation 36 simplifies to: Equation 37. gmp is given by: Equation 38. Typically, RLOAD « (R5 + R6) and the DC gain in P-mode simplifies to: Equation 39. Notice that the DC gain of P mode is proportional to RLOAD and inversely proportional to R5. At heavy loads (small RLOAD), a very large R5 could significantly increase the output voltage error as the DC gain reduces. Conversely, a very small R5 increases power consumption and gm fb variability due to higher dependency on gm ea, which can significantly vary more than 1/(R5||R6) over temperature or from part to part. The total duration of this mode is approximately 7 ms. gmfb gmea gmfb gmp n ADC P 10 310 n RLOAD
Rev. 0.1 15 3.4. Proportional Integral Mode After P-mode, the controller switches to PI-mode, the steady state and final operation mode. During this mode of operation, the error amplifier drives an impedance that consists of the series combination of resistor R7 and capacitor C11. To achieve a smooth transition between P and PI modes, it is recommended to set R7 to match R INT. Equation 40. In PI-mode, the loop transfer is given by: Equation 41. where: Equation 42. Equation 43. Equation 44. Equation 45. Notice that the loop transfer function in PI-Mode has an additional pole-zero pair when compared with P-Mode. In addition, the loop DC-gain is much higher in PI-Mode than in P-Mode due to RO,gmfb » RINT. R7 R INT 100 310= HPI S ADC PI 1 S z1 1 S p1 1 S p2 p1 z1 p2 ADC PI ROg m f b gmpRLOAD
Consider the desired requirements listed in Table 1. Table 1. Design Requirements
18 Rev. 0.1 4.1. Transformer Design For this example, operating in CCM was chosen. Equation 7 establishes the relationship between turns ratio n and duty cycle D. Accounting for forward voltage drop across D1 of 0.5 V and targeting a duty cycle of 40%, Equation 7 can be solved for transformer turns ratio n: Equation 46. A 3:1 turns ratio was chosen. The next parameters to choose are the switching period and primary inductance. The Si886xx has externally set switching frequency range of 200 kHz to 900 kHz. 500 kHz was chosen for this example. C6 is set to 470 nF and R13 is calculated by rearranging Equation 31: Equation 47. R13 was set to 4.32 kΩ as that is the closest 1% resistor value. To determine L m, consider at what minimum load should the converter operate in CCM. For this design, it was targeted to operate in CCM between 70% and full load. At the cross-over point between DCM and CCM: Equation 48. Substituting, Equation 49. And solving for Lm: Equation 50. A transformer with turns ratio of 3:1 and primary inductance of 25 μH was chosen. n VIN D R13 1025.5 T sw 470 9–10 ImAVE ImRIPPLE
0.7 I LOAD
nVIN D1 D– Tsw
20 Rev. 0.1 4.3. Q1 Selection The instant S1 opens, Q1’s drain voltage increases rapidly from nearly 0 V and settles to: Equation 54. However, energy stored in Llkg must be dissipated in the secondary which causes Vds,(D) to spike a higher voltage. Q1 must be able to tolerate this voltage spike between drain and source. A N-channel MOSFET with 100 V rating was chosen to accommodate the expected voltage stress caused by Llkg 4.4. D1 Selection Equation 25 and 26 define the requirements for D1. Substituting into Equation 25, Equation 55. Diode current capacities are specified in rms. Assuming a linear current through D1, consider the translation of average to rms: Equation 56. Substituting into Equation 26: Equation 57. Equation 26 and 57 do not include the voltage spike due to the interaction of the diode capacitance and secondary side leakage inductance, and as a result, a diode with a larger withstanding voltage is required in practice. When selecting D1, diodes with low Vf are the preferred choice as it minimizes the associated power loss. Equation 58. Several diodes were tested in the circuit. A 5 A, 50 V diode was chosen for its tolerance to high operating temperatures at which diode leakage and package heat transfer characteristics affect overall performance and efficiency. 4.5. External Regulator Circuit For this design, an external regulator circuit was designed to work with the VREGA voltage reference to create a regulated supply for VDDA. R14 was selected for a 950 μA sink current. Equation 59. R14 was set to 19.6 kΩ and C14 to the recommended 0.1 μF. MMBT2222 was selected for Q1. Vds 1 D– VIN nV OUT VfD1++ 24 16.5+ 40.5V== = ID1 AVE 1 D– ILOAD 1.84A== VD1 REV D VIN R14 VIN VREGA– IR
Rev. 0.1 21 4.6. C10 Selection C10 is inversely proportional to output voltage ripple and sets the crossover frequency of control loop gain. Solving Equation 23, Equation 60. A 22 μF X7R capacitor in 1210 package was chosen. 4.7. C2 Selection In most applications, V IN also supplies the VDDA pin that powers the dc-dc controller and left side digital isolator circuitry. It is recommended to minimize voltage ripple at VDDA. Solving Equation 19: Equation 61. A 10 μF X7R capacitor in 1210 package was chosen. 4.8. R5 and R6 Selection The ratios of R5 and R6 are determined by the 5 V output voltage requirement. To reduce the dependence of feedback gain on the internal error amplifier transconductance, it is recommended to have the parallel combination resistance to be ≥10 kΩ. Higher values of R5 and R6 reduce power loss through the divider, but at the expense of increasing output voltage error due to I VSNS, which varies part to part. So R5 and R6 are chosen to target 10 k Ω parallel resistance. Equation 62. Equation 63. Substituting Equation 52 into Equation 53 and solving for R6, Equation 64. exactly 5 V as well as other 1% resistor pairs. A better match was found with R6 = 13.3 kΩ and R5 = 49.9 kΩ. C10 ILOAD DTsw VOUT RIPPLE C2 ILOAD DTsw 10 310 R5 R6 5 1.05 R5 = 10 310 3.76R6
A 1.5 nF capacitor was chosen. Figure 10. Undamped Vds Ringing
Table 2 shows the component selection that meets design requirements. Table 2. Ordering Guide
3.7 A, 3 W, Switching, SOT223
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