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Rev. 0.1 3 2.1. S1 Closed, S2 Open VIN is applied to the series combination of C1 and inductance L m + L lkg. As a result, current flows through inductance Lm + Llkg in a linear fashion. Equation 1. Where Im,RIPPLEis the magnetizing current ramp during tS1 and tS1 is the time that S1 is closed. 2.2. S1 Open, S2 Closed In this mode, a resonant tank circuit formed by C1, Lm, and Llkg, and -VC1 is applied across Lm + Llkg. The resonant tank causes the current through leakage inductance to rise as a sinusoid while the voltage at the secondary impressed on the primary causes the current through the primary to reduce in a linear fashion. When l lkg lm, the difference current (Im-Ilkg) flows out of the dot on the primary side of the ideal transformer. Therefore current must flow into the dot on the secondary side and through the diode. Governing current equations are Equation 2. Equation 3. Equation 4. where N and tS2 are primary to secondary turns ratio an d time that S2 is closed respectively. r is the resonance tank frequency in rads/s. The current through the diode in the secondary can be written as the difference of l lkg and l m scaled by the transformer turns ratio. Equation 5. As the sinusoidal current returns to match the magnet izing current, the resonance ceases and consequently no current will flow from the dot on the primary or through the secondary into the diode. 2.3. Voltage Transfer Let duty cycle D be defined as the ratio of time S1 is closed over the complete switching period TSW: Equation 6. VIN VC1– Lm Llkg+ lmR I P P L E tS1 lm RIPPLE tS2 Llkg C1 ID1 llm Ilkg– D tS1
4 Rev. 0.1 Now tS1 and tS2 can be expressed in terms of D and switching period as: Equation 7. Equation 8. and assume diode D1 has no voltage drop when conducting, the volt-second balance equation for L lkg can be written as: Equation 9. With the condition that Llkg << Lm, Equation 9 simplifies to: Equation 10. The volt-second balance equation for Lm is: Equation 11. With the condition that Llkg<<Lm, Equation 11 simplifies to: Equation 12. Substituting Equation 10 into Equation 12 yields the following relationships: Equation 13. Equation 14. tS1 DTSW= tS2 1D– TSW= Llkg VOUT VC1 VOUT VOUT Lm VOUT VOUT VC1 VIN D
Rev. 0.1 5 2.4. Magnetizing Current If during the tS1 portion of the cycle (S1 closed, S2 open), VIN charges C1 in a linear fashion. Rearranging Equation 1 and substituting Equation 7 and Equation 14, ripple magnetizing current is: Equation 15. The average magnetizing current is related to the output current as Equation 16. The peak magnetizing current is given by: Equation 17. Si882xx/Si883xx controller limited the peak magnetizing cu rrent to approximately 3A. If more current than 3A is sensed during S1 on and S2 off mode, the controller immediately switches to the S1 off and S2 on mode. The controller maintains the same switching period, but reduces the duty cycle D to limit peak current. 2.5. Input Capacitor The purpose of C2 input capacitor is to provide current during switching cycles. During S1 closed, S2 open, C2 provides current to C1 in series with Lm + Llkg. Equation 18. During the tS1 portion of the cycle (S1 closed, S2 open), VIN recharges C2. The voltage ripple on C2 can be written as: Equation 19. Substituting Equation 18 into 19: Equation 20. ImR I P P L E VIN VC1– tS1 lmA V E ILOAD N= lmP K lmA V E VIN D1 D– TSW lIN ImA V E DI LOAD DN== VIN RIPPLE IC2 1D– TSW VIN RIPPLE ILOAD D1 D– TSW N
6 Rev. 0.1 2.6. Diode and Output Capacitor Current flows through D1 only during the (1–D)T SW portion of the steady state cycle. During the DT SW portion of the cycle, lLOAD is sourced solely by the output capacitor C10. Output voltage ripple on C10 can be calculated by Equation 21. Applying the charge balance of C10, Equation 22. Equation 23. When D1 is reversed biased, it must withstand Equation 24. VOUT RIPPLE ILOAD DTSW I– LOAD DTSW 1D– TSW+ 0= ID1 AVE 1D– ILOAD VD1 REV D VIN 1D– NV OUT+=
of the amplifier correspond to the internal 1.05V reference, VIN, and VOUT of the dc-dc converter. Figure 4. Simplified VOUT Gain Model large R5 could reduce the output voltage accuracy.
Figure 6. Simplified Voltage Sense Feedback Loop
10 Rev. 0.1 Typically, RLOAD << (R5 + R6) and gmp is approximately 3/N. The DC gain in P-mode simplifies to: Equation 31. Notice that the DC gain of P mode is proportional to RLOAD and inversely proportional to R5. At heavy loads (small RLOAD), a very large R5 could significantly increase the output voltage error as the DC gain reduces. Conversely, a very small R5 increases power consumption and gm fb variability due to hi gher dependency on gm ea, which can significantly vary more than 1/(R5||R6) over temperature or from part to part. The total duration of this mode is approximately 7ms. 3.3. Proportional Integral Mode After P-mode, the controller switches to PI-mode, the ste ady state and final operation mode. During this mode of operation, the error amplifier drives an impedance that consists of the series comb ination of resistor R7 and capacitor C11. To achieve a smooth transition between P and PI modes, it is recommended to set R7 to match RINT R7 and C11 are connected to the COMP pin. Equation 32. In PI-mode, the loop transfer is given by: Equation 33. where Equation 34. Equation 35. Equation 36. Equation 37. Notice that the loop transfer function in PI-Mode has an additional pole-zero pair when compared with P-Mode. In addition, the loop DC-gain is much higher in PI-Mode than in P-Mode due to Ro,gmfb>>RINT. ADC· P 50x10 3 3RLOAD R7 R INT 50x10 3= HPI s ADC PI 1 s z1 1 s p1 1 s p2 p1 z1 p2 ADC PI Rog m f b gmpRLOAD
A 1:4 turns ratio was chosen. The next parameter to choose is the primary inductance. Equation 16 gives the average magnetizing current. cycle that S1 is closed and S2 is open. Figure 8. Magnetizing Current
Rev. 0.1 13 4.2. C1 Selection When S2 is closed, a resonant current in the primary is developed with frequency given by Equation 4. To ensure zero current switching of the diode by the time S1 closed, S2 open mode begins, C1 should be chosen so that at least half of the resonant period is completed in (1–D)T sw time. Equation 41. Combining Equation 4 and Equation 41 and solving for C1: Equation 42. The next standard size capacitor 10 F was chosen. 4.3. D1 Selection Equations 23 and 24 define the requirements for selecting D1. Substituting into Equation 23, Equation 43. Diode current capacities are usually specified in rms. Assuming a half wave sinusoid current through D1, consider the translation of average to rms: Equation 44. Substituting into Equation 24, consider using the maximum expected VIN as the worst case requirement for reverse biasing: Equation 45. Equations 24 and 45 do not include the voltage spike due to the interaction of the diode capacitance and leakage inductance and as a result, a diode with a larger withstandi ng voltage is required in pr actice. When selecting D1, Schottky diodes are the preferred choice due to their low forward voltage as it minimizes the associated power loss. A 1A, 40V Schottky diode was selected. 4.4. C10 Selection C10 is inversely proportional to output voltage ripple an d sets the crossover frequency of control loop gain. It is suggested to use the minimum size capacitor to meet ou tput voltage ripple requirements. Rearranging Equation 21, Equation 46. 1D– Tsw C1 1 Llkg 9.1uF ID1 AVE 1 D – ILOAD 0.4 1 0.533A== = 0.592A== VD1 REV D VIN MAX 1 D– NV OUT+ 5.5 0.75 45+ 21.5v== = C10 ILOAD DTsw VOUT RIPPLE
14 Rev. 0.1 A 10uF capacitor was chosen. 4.5. C2 Selection In most applications, VIN also supplies the VDDA pin that powers the dc—dc controller and left side digital isolator circuitry. It is recommended to minimize voltage ripple at VDDA. Solving Equation 20: Equation 47. A 10F capacitor was chosen. 4.6. R5 and R6 The ratio of R5 and R6 is determined by the 5 V output voltage requirement. To reduce the dependence of feedback gain on the internal error amplifier transconductance, it is recommended to have the parallel combination resistance to be 10 k. Higher values of R5 + R6 reduce power loss through the divider, but at the expense of increasing output voltage error due to l VSNS which varies part to part. So R5 and R6 are chosen to target 10k parallel resistance. Equation 48. Equation 49. Substituting Equation 48 into Equation 49 and solving for R6, Equation 50. exactly 5V as well as other 1% resistor pairs. A better match was found with R6=13.3 k and R5=49.9 k. 4.7. Compensation Network The compensation network is comprised of R7 and C11. R7 is fixed to match R INT and 49.9 k is the nearest 1% resistor value. The C11 places the compensation zero in re lationship to the crossover frequency. The equation for crossover frequency can be had by multiplying the P-mode gain (Equation 31) by the frequency of the pole created by RLOAD and C10 (Equation 36): Equation 51. ILOAD D1 D– TSW N VIN RIPPLE 10x10 3 R5 R6 51 . 0 5 R5 = 10x10 3 3.76R6 fc 50x10 3 3RLOAD
crossover frequency. The zero placement was chosen to lead the crossover frequency by a factor of 6. A 1.5 nF capacitor was chosen. Table 2 shows the component selection that meet the design requirements. Table 2. Design Summary
1 TAP, SMT
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