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  1. Si468x QFN Schematic and Layout

output, and to operate the Si468x with crystal. Figure 1. Si468x QFN Schematic Design

400 West Cesar Chavez

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2 Rev. 0.2 3. EMI Mitigation Due to a high frequency (2880–3840 MHz) on-chip VCO, there is some conductive and magnetic coupling from the VCO to the adjacent traces. The VCO fundamental spur level can be reduced by adding external filtering and using the proper layout. 3.1. External filtering Add filter network comprising of L4 and C15 on the RF input trace (VHFI) for filtering the VCO spur (2880–3840 MHz). The capacitance C15 provides a low impedance path to ground, and inductor L4 provides high impedance to the VCO spur. The inductor L4 also helps in protecting the chip from an external ESD event by providing high impedance path to the ESD event. The two component network attenuates the VCO spur from reaching external antenna port and radiating out. The values of these components are selected to achieve the balance between the sensitivity and the emission levels. Add low pass network C13 & FB5 and C12 & FB6 on the audio lines Right and Left respectively for attenuating the VCO coupling Add high Self Resonant Frequency (>3 GHz) capacitors C2, C6, C7 and C8 on the supply lines to decouple the VCO leakage currents. 3.2. Front-End Matching The components (C1, L1, L2, and L4) are used for maximizing the voltage gain on the VHFI pin. For the FM and DAB band, the matching components C1, L1, L2, and L4 will re quire optimization to maximize the voltage gain on the VHFI pin. The inductor L2 can be engaged or disengaged using a VHFSW switch. Refer to property “0x1712” of AN649 for information on how to handle the VHFSW switch. The voltage gain is maximized by forming a high Q parallel LC resonant tank circuit. The induc tor of the tank circuit is the parallel combination of L1 and L2. And the tank capacitance includes the antenna capacitance, capacitance of the external front end network, PCB parasitic, internal chip parasitic and internal variable capacitance provided by on-chip varactor tuning. With a given antenna source impedance and the parasitics (pcb and chip internal), the resonant peak of the LC tank circuit across the FM and DAB band can be maximized by finding the right combination of C1, L1, L2, and L4, and the internal varactor capacitance. Refer to Appendix A for additional details on using internal varactor tuning. Note that the procedure outlined in Appendix A for inte rnal varactor tuning is considering the signal generator source impedance (50 ) but the same procedure can be used with different antenna source impedance. Refer to Appendix B on how to select component values for optimizing the front end.

Table 1. Application Schematic BOM

4 Rev. 0.2 3.2.1. Component Selection and Replacement The front end network components shall be placed as close as possible to the chip and as far away from noise sources such as clocks and digital circuits. L1 shall be routed to ground plane with a short trace and a via connection. The recommendations regarding C1, C2, C3, C5, C6, C7, C8, C9 and C10 are made to reduce the size of the current loop created by the bypass cap and routing, minimize impedance and return all currents to the ground. C3 and C4 (2.2 nF and 1 uF) are required bypass capacitors for VA supply pin 12. Place C2, C3 and C4 as close as possible to VA. C3 and C4 are chosen to mitigate noise in medium to VHF frequency range. Place a via connecting C2, C3, C4 and VA pins to the power rail such that the caps are closer to the Si468x VA pin than the via. Route C2, C3 and C4 only to the ABYP pin directly with a short (6-mil width) low inductance trace. C9 and C22 (2.2 nF and 1 uF) are required bypass capacitors for VIO supply pin 34. C9 and C22 are chosen to mitigate noise in medium to VHF frequency range. Place C6, C9, and C22 as close as possible to VIO pin 34 and DBYP pin 36. Place a via connecting C6, C9, and C22 and VIO supply to the power ra il such that the caps are closer to the Si468x VIO pin than the via. Route C6, C9, and C22 only to DBYP pin directly with a short (6-mil width) low inductance trace. C10 and C23 (2.2nF and 1 uF) are required bypass capacitors for VMEM supply pin 35. C10 and C23 are chosen to mitigate noise in medium to VHF frequency range. Pl ace C7, C10, and C23 as close as possible to VMEM pin 35 and DBYP pin 36. Place a via connec ting C7, C10, and C23 and VMEM su pply pin to the power rail such that the caps are closer to the Si468x VMEM pin than the via. Route C7, C10, and C23 only to DBYP pin directly with a short (6-mil width) low inductance trace. C11 and C24 (2.2nF and 1 uF) are required bypass capacitors for VCORE supply pin 37. C11 and C24 are chosen to mitigate noise in medium to VHF frequency range. Place C8, C11 and C24 as close as possible to VCORE pin 37 and DBYP pin 36. Place a via connecting C8, C11 and C24 and VCORE pin 37 to th e power rail such that the caps are closer to the Si468x VCORE pin than the via. Route C8, C11 and C24 only to DBYP directly with a short (6-mil width) low inductance trace. C5 (1uF) is an optional bypass capacitor for DACREF pin 17 if cu stomer uses analog audio output. Place C4 as close as possible to DACREF pin. Customers do not need to populate this capacitor if they are using digital audio output only. C20 and C21 (1uF) are optional ac coupling capacitors for analog audio outputs. The value should be selected to work well with the customer’s choice of audio amp. X1 is an optional crystal required only when using the internal oscillator feature. Place the crystal X1 as close to XTALI (pin 15) and XTALO (pin 16) as possible to minimize current loops. 3.3. Layout Guide The following placement/layout guidelines are suggested for 4-layer PCB: PCB layer assignment: Layer 1 top side placement and routing for RF and analog traces Layer 2 ground plane Layer 3 routing for high frequency digital traces and ground plane Layer 4 bottom side placement and routing for low frequency digital traces Minimum 6-mil trace Minimum 6-mil trace spacing 6-mil drill 9-mil plating for normal vias Minimum 10-mil component spacing Power routed by trace 0402 component size or larger

  1. Antenna and Matching Network Design and Layout

headphone antenna with a length of 1.1 m suits FM/FMHD/T-DMB/DAB applications well. of a typical application is shown in Figure 3. Figure 3. A Typical HP Antenna Application

Table 2. Headphone Antenna BOM Table 3. Headphone Antenna Optional BOM

Si468x and as far from noise sources such as clocks and digital circuits as possible. should be placed between F1, F2, and F3 and the headphone amplifier to minimize antenna shunt capacitance. necessary to design for 50  transmission lines. describes how to interface the Si468x VHFI input to a cable antenna. Figure 6. A Typical Cable Antenna Application C13 (100 pF) is a dc blocking cap placed between the VHFI pin and the cable antenna ground. through the shunt ferrite rather than going through the tuning inductor and/or Si468x chip.

from the shield/ground. The choice of the ferrite is dependent upon the type of signal on each individual conductor. If the conductor is used to carry power, then a ferrite with a large dc current carrying capa bility should be used. as possible to the cable. This will minimize the parasitic capacitance seen by the VHFI pin. Table 4. Cable Antenna BOM F2 Series Ferrite bead, various types.

sources coupling to the trace. AM band. Noise sources can come from clock signals, sw itching power supply, and digital activities (e.g., MCU). chip. This will minimize capacitive coupling between the plane(s) and the antenna. To tune correctly, the total capacitance seen at the AMI input needs to be minimized and kept under a certain value. the AM input can be calculated using the formula shown in Equation 1. an AM band with 10 kHz spacing, where the highest frequency in the band is 1710 kHz. Table 5. Ferrite Loop Antenna Bill of Materials exposed pad going to the AMI pin.

Rev. 0.2 13 5.5. Ferrite Loop Antenna Design Checklist  Place the chip as close as possible to the ferrite loop antenna feedline to minimize parasitic capacitance and the possibility of noise coupling.  Place the ferrite loop stick antenna away from any sources of interference and even away from the I/O signals of the Si468x. Please make sure that the AM antenna is as far away as possible from circuits that switch at a rate which falls in the AM band (520–1720 kHz).  Place optional component D1 if the antenna is exposed.  Select ESD diode D1 with minimum capacitance.  Do Not Place any ground plane under the ferrite loop stick antenna if the ferrite loop stick antenna is mounted on the PCB. The recommended ground separation is 1/4 inch or the width of the ferrite.

Figure 10. AM Air Loop Antenna Schematic D1 is a required ESD diode since the antenna is exposed. PCB and away from even the I/O signals of the Si468x. Do not route any si gnals under or near the transformer. Use a shielded transformer if possible. Table 7. Air Loop Antenna Bill of Materials

16 Rev. 0.2 6.5. Air Loop Antenna Design Checklist  Select a shielded transformer or a toroidal shape transformer to prevent noise pickup from interfering sources  Select a high-Q transformer with coupling coefficient as close to 1 as possible  Use multiple strands Litz wire for the transformer winding  Place the transformer away from any sources of interference and even away from the I/O signals of the Si468x. Please make sure that the AM antenna is as far away as possible from circuits that switch at a rate which falls in the AM band (520–1720 kHz).  Select ESD diode D1 with minimum capacitance.

above 3 properties in each functional FW image. After the part is booted, t he 3 properties are set to 0 by default. tuning function to achieve the target of conducted sensitivity specification. by VARM/VARB settings) is bypassed and the on-chip varactor is set as the ANTCAP value as specified by users. This feature is utilized in the procedure described below for DAB. Set DAB_TUNE_FE_CFG property as 1, which closes the VHFSW.

  1. Connect the signal-generator to DUT with an SMA barrel.
  2. Set the signal-generator to frequency X with 40 dBuV rf level and FM/DAB modulation.
  3. Tune Si468x to frequency X with ANTCAP set to 1.
  4. Call Test_Get_RSSI command 5 times and get the average of the 5 RSSi measurements.
  5. Increment the ANTCAP by 1 and re-issue the tune command to Si468x.
  6. Repeat Step 4 and Step 5 until reaching the max tunable varactor range of 128.
  7. Identify the varactor value with the max RSSI reading.

Repeat the test for frequencies across the DAB band. varactor is not lower than 4. This is illustrated in the graph* below. Table 8. Varactor Tuning Properties *Note: See AN649 for detailed descriptions of these properties.

Figure 11. Varactor vs. Frequency Chart and b values into the properties: 0x1710, 0x1711 after Si468x is booted. When tuning, issue the “dab_tune_freq 0 $freq 0” to enable automatic tuning method.

Figure 14. Norton Equivalent of Antenna Interface with Module FE unknown quantity (inductor or capacitor) can be calculated.

Figure 15. Parallel RLC

  1. Measure the impedance of the antenna using network analyzer (S11 measurement). Write down the

resistive and reactance values.

  1. Measure the impedance of the cable.
  2. Convert the above circuit into a simplified parallel LC circuit (shown in previous section).
  3. Choose and fix the shunt indicator (L2 value) and then calculate the capacitance required using resonance

LC at the lowest frequency.

  1. Use the antenna graph function of Si46xx EVB GUI to measure the capacitance value required to form

resonance by engaging internal varactor. calculated by GUI minus the parasitic capacitance (PCB + Si46xx front end).

  1. Ideally, to form resonance across the entire band, the varactor capacitance required at low frequency

should be close to its maximum value 32pf (128 varactor counts).

  1. Change L2 if the varactor capacitor measured at low frequency is not close to its max value of 32pf (128

because the inductive reactance in the Norton branch (shown in the previous section) may be dominating.

  1. Change C1 or L1 and repeat steps 4 through 8.
  2. Verify that with chosen values of C1, L1, and L2 the entire range of varactor capacitor is put in use across
  3. For tuning across a different band, the inductor switch VHFSW option shall be exercised to engage L3

L3 and follow steps 2 through 9. 7-inch length of coax cable connecting the antenna and the module. Figure 18. Silicon Labs Recommended FE Network

24 Rev. 0.2 The varactor capacitor slope and intercept, and VHFSW switch API properties for the recommended network shall be set to the following: If the VHFSW switch position required for both FM and DAB band is the same (close—as in the above network) then L2 and L3 can be replaced with a single inductor equivalent to the parallel combination of L2 and L3. FW Image Slope (property 0x1710) Intercept (property 0x1711) Switch(property 0x172) FM 0xEDB5 0x01E3 1 (closed) DAB 0xF8A9 0x01C6 1 (closed)

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