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Figure 1. Transferring Data using the DMA and DTM modules Precision32 Application Notes are listed on the following website: www.silabs.com/32bit-appnotes.

controller and DMA peripheral crossbar. Figure 2. DMACTRL and DMACH Block Diagram automatically sets the ABASEPTR field based on the number of channels implemented in the module. status flags. The channels operate independently, but have a fixed arbitration order.

Rev. 0.1 3 4.1. DMA Channel Transfer Descriptors Each channel has transfer descriptors stored in memory that describe the data transfer in detail. Each descriptor is composed of four 32-bit words in memory organized as follows: 1. Source End Pointer (word 1): The address of the last source data in the transfer. 2. Destination End Pointer (word 2): The last destination address of the transfer. 3. Channel Configuration (word 3): Configuration details for the transfer. 4. Alignment padding (word 4): Not used by the DMA controller. Firmware may use this word for any purpose. Each channel can have primary, alternate, and scatter- gather descriptors. The primary and alternate descriptors are organized in contiguous blocks in memory for each of the channels. The spacing for these descriptors is fixed, so any unused channels must still be ac counted for when placing descriptor s in memory. The primary descriptors must be placed at the start of an address block sized for both the primary and alternate descriptors. For SiM3U1xx, SiM3C1xx, and SiM3L1xx devices that implement 16 or 10 DMA channels, the BASEPTR points to the start of the primary descriptors and is 23 bits wide. The valid addres ses for the BASEPTR field are multiples of 256 (0x0000_0100), and the required memory for all primary and alternate descriptors for 16 channels is 512 bytes. The scatter-gather descriptors are more flexible and can appear anywhere in memory. Channel 0’s primary descriptor begins at address offset 0x0000, Channel 1’s primary descriptor starts at offset 0x0010, and so on. The alternate descriptors begin at the next memory block (256 bytes), regardless of whether or not the primary descriptors for the channels are in use. Firmware originally sets the channe l configuration descriptor ; the DMA controller will modi fy this word as the transfer progresses, so firmware should not write to this descriptor until any active transfers for the channel are complete. Figure 3 shows the fixed memory configuration for the descriptors.

Figure 3. Channel Transfer Descriptor Memory Configuration

the primary, alternate, and scatter-gather DMA channel descriptors. Table 1. DMA0_CHx_SRCEND: Source End Pointer 31:0 SRCEND Source End Pointer. This field is the address of the last source data in the DMA transfer. Table 2. DMA0_CHx_DSTEND: Destination End Pointer 31:0 DSTEND Destination End Pointer. This field is the last destination address of the DMA transfer.

Table 3. DMA0_CHx_CONFIG: Channel Configuration 31:30 DSTAIMD Destination Address Increment Mode. This field must be set to a value that's equal to or greater than the DSTSIZE setting. 00: The destination address increments by one byte after each data transfer. 01: The destination address increments by one half-word after each data transfer. 10: The destination address increments by one word after each data transfer. 11: The destination address does not increment. 29:28 DSTSIZE Destination Data Size Select. The destination size (DSTSIZE) must equal the source size (SRCSIZE). 00: Each DMA destination data transfer writes a byte. 01: Each DMA destination data transfer writes a half-word. 10: Each DMA destination data transfer writes a word. 27:26 SRCAIMD Source Address Increment Mode. This field must be set to a value that's equal to or greater than the SRCSIZE setting. 00: The source address increments by one byte after each data transfer. 01: The source address increments by one half-word after each data transfer. 10: The source address increments by one word after each data transfer. 11: The source address does not increment. 25:24 SRCSIZE Source Data Size Select. The destination size (DSTSIZE) must equal the source size (SRCSIZE). 00: Each DMA source data transfer reads a byte. 01: Each DMA source data transfer reads a half-word. 10: Each DMA source data transfer reads a word. 23:18 Reserved Must write 0 to this field.

Rev. 0.1 7 17:14 RPOWER Transfer Size Select. This field determines the number of data transfers between each DMA channel re-arbi- tration. The number of data transfers is given by: This field is ignored for peripherals that support single data requests only. A value of 0 for RPOWER should be used for channels interfacing with these types of peripherals. 13:4 NCOUNT Transfer Total. This field is the total number of transfers for the DMA channel. The total number is NCOUNT + 1, so software requiring a total of 4 transfers would set the NCOUNT field to 3. The DMA controller decrements this field as transfers are made. 3 Reserved Must write 0 to this bit. 2:0 TMD Transfer Mode. 000: Stop the DMA channel. 001: Use the Basic transfer type (single descriptor only). 010: Use the Auto-Request transfer type (single descriptor only). 011: Use the Ping-Pong transfer type (primary and alternate descriptors). 100: Use the Memory Scatter-Gather Primary transfer type (primary, alternate, and scattered descriptors). 101: Use the Memory Scatter-Gather Alternate transfer type (primary, alternate, and scattered descriptors). 110: Use the Peripheral Scatter-Gather Primary transfer type (primary, alternate, and scattered descriptors). 111: Use the Peripheral Scatter-Gather Alternate transfer type (primary, alternate, and scattered descriptors). Bit Name Function Number of Transfers 2 RPOWER=

particular peripheral. These assignments are shown in Table 4. Table 4. DMA Crossbar Channel Peripheral Assignments for SiM3U1xx Devices

Table 5. DMA Crossbar Channel Peripheral Assignments for SiM3C1xx Devices

Table 5. DMA Crossbar Channel Peripheral Assignments for SiM3C1xx Devices (Continued)

Table 6. DMA Crossbar Channel Peripheral Assignments for SiM3L1xx Devices

Table 6. DMA Crossbar Channel Peripheral Assignments for SiM3L1xx Devices (Continued)

peripheral scatter-gather. Table 7 shows the memory requirements for each transfer type. Any data remaining can be transferred by firmware or use an extra DMA data request.

1. The DMA channel will write the primary descriptor TMD field with 0.
2. The primary descriptor NCOUNT field will contain 0.
3. The controller automatically disables the channel (the channel bit in CHENSET will read 0).

Figure 4 illustrates the DMA memory descriptors for a basic transfer. This transfer type is recommended for peripheral-to-memory or memory-to-peripheral transfers. Table 7. Transfer Memory Requirements

10 Channels

16 Channels

Figure 4. Basic and Auto-Request Transfer Memory Configuration

1. The DMA channel will write the primary descriptor TMD field with 0.
2. The primary descriptor NCOUNT field will contain 0.
3. The controller automatically disables the channel (the channel bit in CHENSET will read 0).

The auto-request memory configuration is identical to the basic transfer shown in Figure 4.

Figure 6. Ping-Pong Transfer Memory Configuration

Rev. 0.1 17 4.3.4. Memory Scatter-Gather Transfers The memory scatter-gather transfer uses primary, alte rnate, and scatter-gather desc riptors. This transfer type allows a DMA channel to be set for multiple transfers at once without core intervention at the price of extra memory for the scatter-gather descriptors. The primary descriptor in this mode contains the numb er and location of the scatter-gather descriptors. The primary descriptor should be programmed as follows: 1. Memory scatter-gather primary mode (TMD = 4). 2. RPOWER = 2. 3. NCOUNT set to the value specified by Equation 2. 4. SRCEND is set to the location of the last word of all the scatter-gather descriptors. 5. DSTEND is set to the location of the last word in the single alternate descriptor. Equation 2. NCOUNT Value for Scatter-Gather Transfers The scatter-gather descriptors must be stacked contiguous ly in memory. The channel will copy the scatter-gather descriptors into the alternate descriptor location and execute them one by one. The scatter-gather descriptors should be programmed to memory scatter-gather alternate mode (TMD = 5), except for the last descriptor, which should use the auto-request transfer type (TMD = 2). Once started, the DMA channel execution process is as follows: 1. Copy scatter-gather 1 (SG1) to the alternate descriptor. 2. Jump to the alternate descriptor and execute. 3. Jump back to the primary descriptor. 4. Copy scatter-gather 2 (SG2) to the alternate descriptor. 5. Jump to the alternate descriptor and execute. 6. Jump back to the primary descriptor. The channel will continue in this pattern until the channel encounters a scatter-gather descriptor set to a basic or auto-request transfer. Only one data request is required to execute all of the scattered transactions. The channel interrupt will occur once the last scatter-gather descriptor (programmed to a basic transfer) executes, if enabled. Arbitration occurs every RPOWER of the scatter-gather descriptors. Figure 7 shows the memory scatter-gather memory configuration. NCOUNT Number of SG Structures 4  1–=

Figure 7. Memory and Peripheral Scatter-Gather Transfer Memory Configuration

Rev. 0.1 19 4.3.5. Peripheral Scatter-Gather Transfers The peripheral scatter-gather transfer is very similar to the memory scatter-gather transfer and uses primary, alternate, and scatter-gather descriptors. This transfer type allows a DMA channel to be set for multiple transfers at once without core intervention at the price of extra memory for the scatter-gather descriptors. A data request is required for each 2 RPOWER data move of the scatter-gather descriptor tasks. The RPOWER value can be different for each scatter-gather task. Equation 1 describes the total number of data requests required to complete a transfer. The primary descriptor in this mode contains the numb er and location of the scatter-gather descriptors. The primary descriptor should be programmed as follows: 1. Peripheral scatter-gather primary mode (TMD = 6). 2. RPOWER = 2. 3. NCOUNT set to the value specified by Equation 2. 4. SRCEND is set to the location of the last word of all the scatter-gather descriptors. 5. DSTEND is set to the location of the last word in the single alternate descriptor. The scatter-gather descriptors must be stacked contiguous ly in memory. The channel will copy the scatter-gather descriptors into the alternate descriptor location and execute them one by one. The scatter-gather descriptors should be programmed to peripheral scatter-gather alternate mode (TMD = 7), except for the last descriptor, which should use the basic transfer type (TMD = 1). Once started, the DMA channel execution process is as follows: 1. Copy scatter-gather 1 (SG1) to the alternate descriptor. 2. Jump to the alternate descriptor and execute. 3. Jump back to the primary descriptor. 4. Copy scatter-gather 2 (SG2) to the alternate descriptor. 5. Jump to the alternate descriptor and execute. 6. Jump back to the primary descriptor. The channel will continue in this pattern until the channel encounters a scatter-gather descriptor set to a basic or auto-request transfer. The channel interrupt will occur once the last scatter-gather descriptor (programmed to a basic transfer) executes, if enabled. Figure 7 shows the peripheral scatter-gather memory configuration.

request type. Table 8 and Table 9 lists the supported requests for the supported triggers and peripherals. requests, the RPOWER field is ignored and re-arbitration occurs after every single data move. Table 8. Supported Trigger or Peripheral Data Requests for SiM3U1xx/SiM3C1xx Devices

DMA module external trigger sources are routed to peripheral pins using the crossbar. CHREQMCLR register to clear the mask for a channel. initiated transfers to avoid any peripherals connected to the channel from requesting DMA transfers. Table 9. Supported Trigger or Peripheral Data Requests for SiM3L1xx Devices

1. Using the DMA for a Memory-to-Memory Transfer

peripheral. A memory-to-memory transfer can use the Auto-Request DMA transfer type. Figure 9. Memory-to-Memory DMA Transfer

1. Enable the AHB and APB clocks to the DMA controller.
2. Enable the DMA module (DMAEN = 1).
3. Set the address location of the channel transfer descriptors (BASEPTR) according to the restrictions in

section “4.1. DMA Channel Transfer Descriptors”.

1. Use the CHALTCLR register to set the channel to use the primary descriptor.
2. Create the primary descriptor in memory for the desired transfer:

a. Set the SRCEND field to the last address of the source data. b. Set the DSTEND field to the last address of the destination memory. these values should be the same. d. Set the destination and source data size (DSTSIZE and SRCSIZE) to the same value. f. Set the NCOUNT field to the total number of transfers minus 1. g. Set the transfer mode to the auto-request type (TMD = 2).

1. Disable data requests for the channel using the CHREQMSET register.
2. Set the DMA to fast mode using the FDMAEN bit in the SCONFIG module.
3. Enable the DMA channel using the CHENSET register.
4. (Optional) Enable the DMA channel interrupt.
5. Submit a request to start the transfer.

24 Rev. 0.1 For memory-to-memory transfers that do not rely on a peri pheral, the easiest way to initiate these transfers is to use the software request in the CHSWRCN register. It is recommended that firmware set the channel request mask (CHREQMSET) for channels using software-initiated transfers to avoid any peripherals connected to the channel from requesting DMA transfers. Alternate start-of-transfer triggers could be the external triggers (DMAXT0 or DMAXT1) or a timer overflow trigger. The DMA_Memory_to_Memory.c code example included in the software package demonstrates this type of DMA transfer.

26 Rev. 0.1 To configure a DMA channel for a peripheral-to-memory (receive) or memory-to-peripheral (transmit) data transfer: 1. Enable the AHB and APB clocks to the DMA controller. 2. Enable the DMA module (DMAEN = 1). 3. Set the address location of the channel transfer descriptors (BASEPTR). 4. Route the DMA signals from the peripheral function to a DMA channel. 5. Use the CHALTCLR register to set the channel to use the primary descriptor. 6. Create the primary descriptor in memory for the desired transfer: a. Set the SRCEND field to the last address of the source data. b. Set the DSTEND field to the peripheral FIFO register. c. Set the destination and source address increment modes (DSTAIMD and SRCAIMD). For peripheral- to-memory transfers, the source should be in non-incrementing mode. For peripheral-to-memory transfers, the destination should be in non-incrementing mode. d. Set the destination and source data size (DSTSIZE and SRCSIZE) to the same value. e. Set the RPOWER to the desired number of data transfers between rearbitration. See the appropriate RPOWER value for the peripheral (Table 4, Table 5, and Table 6). f. Set the NCOUNT field to the total number of transfers minus 1. g. Set the transfer mode to the basic type (TMD = 1). 7. Enable data requests for the channel (CHREQMCLR). 8. Set the DMA to fast mode using the FDMAEN bit in the SCONFIG module. 9. Enable the DMA channel using the CHENSET register. 10. (Optional) Enable the DMA channel interrupt. 11. Enable the peripheral to start the transfer. The CHALTSET register can set a DMA channel to use the alternate descriptor instead of the primary descriptor. Firmware can use the CHALTCLR register to set the channel back to the primary descriptor. The controller automatically updates the CHALTSET fields to indicate wh ich descriptor is in use during transfers that use the alternate descriptor (ping-pong and scatter-gather). The DMA_Peripheral_to_Memory.c code example included in the software package demonstrates a peripheral- to-memory DMA transfer by using the USART0 peripheral (receive only) to receive ASCII characters from the CP210x USB-to-UART bridge on the MCU Card and store them in memory. The characters can be entered using a Terminal program on the PC. The DMA_Memory_to_Peripheral.c code example included in the software package demonstrates a memory-to- peripheral DMA transfer by using the USART0 peripheral (transmit only) to transmit an ASCII table stored in memory to the CP210x USB-to-UART bridge on the MCU Ca rd. The table is displayed in a Terminal program on the PC.

1. Using the DMA for a Delayed Peripheral-to-Memory-to-Peripheral

interrupt after each ping-pong transfer completes. Figure 12. Peripheral-to-Memory-to-Peripheral DMA Transfer

1. Enable the AHB and APB clocks to the DMA controller.
2. Enable the DMA module (DMAEN = 1).
3. Set the address location of the channel transfer descriptors (BASEPTR).
4. Route the DMA signals from the peripheral function to a DMA channel.
5. Use the CHALTCLR register to set the channel to use the primary descriptor.
6. Create the primary descriptor in memory for the desired transfer:

a. Set the SRCEND field to the last address of the source data. b. Set the DSTEND field to the peripheral FIFO register. transfers, the destination should be in non-incrementing mode. d. Set the destination and source data size (DSTSIZE and SRCSIZE) to the same value. RPOWER value for the peripheral. f. Set the NCOUNT field to the total number of transfers minus 1. g. If this is the last action for the DMA channel, set the transfer mode to the basic type (TMD = 1). Otherwise, set the transfer mode to the ping-pong type (TMD = 3).

28 Rev. 0.1 7. Create the alternate descriptor in memory for the desired transfer: a. Set the SRCEND field to the last address of the source data. b. Set the DSTEND field to the peripheral FIFO register. c. Set the destination and source address increment modes (DSTAIMD and SRCAIMD). For peripheral- to-memory transfers, the source should be in non-incrementing mode. For peripheral-to-memory transfers, the destination should be in non-incrementing mode. d. Set the destination and source data size (DSTSIZE and SRCSIZE) to the same value. e. Set the RPOWER to the desired number of data transfers between rearbitration. See the appropriate RPOWER value for the peripheral. f. Set the NCOUNT field to the total number of transfers minus 1. g. If this is the last action for the DMA channel, set the transfer mode to the basic type (TMD = 1). Otherwise, set the transfer mode to the ping-pong type (TMD = 3). 8. Enable data requests for the channel. 9. Set the DMA to fast mode using the FDMAEN bit in the SCONFIG module. 10. Enable the DMA channel using the CHENSET register. 11. (Optional) Enable the DMA channel interrupt. 12. Submit a request to start the transfer. The DMA_Peri_to_Mem_to_Peri.c code example included in the software package demonstrates a ping-pong DMA transfer by using the USART0 peripheral (transmit and receive) to receive 2 10-byte character sets from a Terminal program on the PC using the CP210x USB-to -UART bridge on the MCU Card. When the second set is received, a second DMA channel displays the received ch aracters in the Terminal program on the PC. This code example uses two different DMA channels due to the DMA peripheral crossbar mapping and since both the USART0 receive and USART0 transmit features are used. 8. Using the DMA for a Simultaneous Peripheral-to-Memory-to-Peripheral Transfer A single DMA channel is unable to service more than one peripheral simultaneously. In addition, DMA channels cannot automatically start or pause a transfer in another channel without core intervention. The easiest way to perform a peripheral-to-memory-to-perip heral transfer (i.e., I2C-to-m emory-to-UART) is to set up several buffers in memory. Once the first peripheral transfers data to the first buffer, the DMA channel done interrupt will occur, if enable d. Inside this interr upt service routine, firmware ca n start the first DMA channel to transfer data from the source peripheral to a second buffer and set up a second DMA channel to transfer data from the first buffer to the end peripheral. The DTM module on SiM3L1xx devices allows these types of transfer to occur without core intervention.

Rev. 0.1 29 9. DTM Overview (SiM3L1xx Devices Only) The DTM module collects DMA request signals from various peripherals and generates a series of master DMA requests based on a state-driven configuration. This master request drives a set of DMA channels to perform functions such as assembling and transferring communication packets to external radio peripherals. This capability saves power by allowing the MCU to remain in low power modes such as PM2 during complex transfer operations. A combination of simple and peripheral-scatter-gather DMA configurations can be used to perform complex operations while limiting the memory requirements (for ex ample, by implementing direct peripherals-to-peripheral transfers). Each DTM block supports up to 15 user-configurable states. Each state can be set up to run a certain number of DMA operations from one peripheral (the source) to an other (the destination), including memory areas such as flash and RAM. Each state also has the ability to define two options for what the next state in the sequence will be, dependent on the condition of the counters and other parameters in the DTM block. Each DTM block is capable of driving up to four DMA channels (A, B, C and D), and each DTM state can be configured to drive a particular request line to the DMA. This allows basic DMA operations to replace a long sequence of peripheral-scatter-gather tasks in most applications, saving memory. 9.1. Counters The DTM modules contain three different counters: a master counter, a state counter, and a timeout counter. The 16-bit master counter, represented in the MSTCOUNT register, can be initia lized by firmware to track the number of DMA requests that have occurred. MSTCOUNT is decremented on each DMA operation unless the active state configuration specifies otherwise. The 8-bit State counter, represented by the STCOUNT field in the CONTROL register, also decrements each time a DMA request is generated. This is used to track the nu mber of requests since the active state was last entered (from 1 to 256). The STCOUNT field is automatically loaded with the value of STRELOAD in the state description when a state is entered. A 16-bit timeout counter is represented by the TOCOUNT field in the TIMEOUT register. An internal 8-bit prescaler divides the APB clock frequency and TOCOUNT is dec remented every 256 APB cloc k cycles. Each state can selectively reload TOCOUNT and enable or disable the timeout counter while the state is active. If a TOCOUNT reload is requested, the timeout counter will be reloa ded from the TORELOAD field in the TIMEOUT register, and the internal prescaler will reset. If TOCOUNT reaches 0 and the internal pr escaler overflows, a timeout error is declared and the DTM transitions to its DONE state. The TOERRI flag in the CONTROL register will be set and an interrupt will be generated if enabled. When it is used, the length of the timeout is equal to 256 x (TRELOAD + 1) APB clock cycles.

active, its information is read into the DTM block’s STATE register. Table 10. DTM Source Module Options

0000 SPI0 Receive 1000 EPCA0 Capture

0001 SPI1 Receive 1001 ENCDEC0 Output

0010 AES0 Output 1010 Reserved

0011 Reserved 1011 Reserved

0100 USART0 Receive 1100 Reserved

0101 Reserved 1101 DMA0T0

0110 I2C0 Receive 1110 DMA0T1

0111 SARADC0 Output 1111 Memory Transfer (No Source)

Table 11. DTM Destination Module Options

0000 SPI0 Transmit 1000 EPCA0 Capture

0001 SPI1 Transmit 1001 ENCDEC0 Input

0010 AES0 Data In 1010

0011 AES0 XOR In 1011 Reserved

0100 USART0 Transmit 1100 Reserved

0110 I2C0 Transmit 1110 DMA0T1

0111 IDAC0 Input 1111 Memory Transfer (No Destination)

32 Rev. 0.1 It is also possible to instruct a state to hold off any further transfer requests until an external pin input (specified by the INHSEL field in the CONTROL register) is asserted . The DTMINH and INHSPOL fields in the state structure configure this capability for the selected inhibit pin. 9.1.4. Interrupts Within a state structure, the user can selectively enable timeout interrupts and state transition interrupts. The timeout counter and its associated interrupt are e nabled using the TOERRIEN flag. If TIOERRIEN is set, TOCOUNT is loaded with the value of TORELOAD on entry into the state. If the TOCOUNT field reaches zero, the TIOERRI interrupt flag will be set, and the state machine transitions to DONE. The PRISTIEN and SECSTIEN flags enab le interrupts upon transition to the primary and secondary states, respectively. When either of these interrupts occurs, the DTMI interrupt flag will be set by hardware. 10. Using the DTM Module on SiM3L1xx Devices for Peripheral-to-Memory- to-Peripheral Transfers The DTM allows DMA channels to automatically chain without core intervention. When creating DTM code, it is recommended to first start with the basic peripheral config uration and verify the peripheral is configured correctly before adding DMA support. Once the DMA operation is verified, add the final DTM piece to create the full system. To set up a DTM system: 1. Enable AHB and APB clocks to the DTM module. 2. Start with DTM/DMA channels disabled. 3. Configure the DMA channel or channels. Ensure the DMA crossbar maps the DMA channels to DTM channels. Wait to enable the channels until after the DTM module is completely initialized. 4. Initialize the state fields for the DTM operation. For each state: a. Set the DTM Channel for the state (A, B, C, or D). b. Set the source field (SRCMOD). c. Set the destination field (DSTMOD). d. Select the next state for the primary state transition (PRIST). e. Select the next state for the secondary state transition (SECST). f. Set the number of DMA transfers for the state using the STRELOAD field. g. Set any active interrupts or other options for the state. 5. Initialize the DTM module. 6. Clear all interrupts in the DTM module. 7. (Optional) Enable DTM module interrupts. 8. Enable the DTM module and DMA channels. The DTM_Peri_to_Mem_to_Peri.c code example included in the software package demonstrates two basic DMA transfers using the USART0 peripheral (transmit and receive) to receive and transmit a 20-byte character set from and to a Terminal program on the PC using the CP210x USB-to-UART bridge on the MCU Card. The DTM automatically starts the transmit DMA transfer after the receive DMA transfer, displaying the characters in the Terminal program on the PC. This code example uses two different DMA and DTM0 channels for the two states S0 (receive) and S1 (transmit).

Figure 14. DTM Peripheral-to-Memory-to-Peripheral Example

34 Rev. 0.1 CONTACT INFORMATION Silicon Laboratories Inc.

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