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- Si477x QFN 6x6 mm Schematic and Layout
This section describes the application schematic and layout required for optimal Si477x performance. Figure 1. Si477x FM/AM Front-End Schematic
Rev. 0.3 3 1.3. FM Front-End 1.3.1. FM Front-End ESD diode D1 protects against external antenna ESD ev ents. Place D1 close to the antenna connector. Choose diodes with minimum parasitic capacitance, such as the Tyco Electronics PESD0402-140 (0.25 pF). Series inductor L9 (10 nH) suppresses EMI. The AM loading capacitor, C10 (18 pF) ac-couples the antenna to the input network and resonates with the inductor L3 (150 nH). The FM input (FMI, Pin 7) matching network consists of L2 (47 nH), C9 (62 pF), and AGC-controlled internal resistor banks FMAGC1 (Pin 40) and FMAGC2 (Pin 39). Place these components close to the FMAGC1/2 pins to minimize trace inductance. Connect FMI using two vias and a trace on PCB Layer 2. Connect the LNA output (FMO, Pin 6) to the RF regula tor (RFREG, Pin 5) using L1 (220 nH). Place L1 and RF regulator bypass capacitor C7 (2.2 nF) close the RFREG pin. Connect the LNA output through ac-coupling capacitor C8 (1 nF) to input of T1, the external FM balun. The two outputs of the balun are connected to FM mixer inputs (FMXIP, Pin 2 and FMXIN, Pin 3). Shunt Capacitors C11,C22, C2 4, C25, and C26 are place holders for filterin g caps on the EVB. They may not be required in actual application. Components should be placed close to the IC to minimize trace lengths. All front-end ground connections should be to a common system ground. Alternatively, an RF ground plane should be connected to system ground by a shield or large copper fill. 1.3.2. AM Front-End The schematic shows two paths to the AM input (AMI, pin 10). The path originating with J33 is used on the evaluation board for conducted testing and is not needed as part of the true application circuit. The path originating from JP1 assumes a loop antenna will be used. JP1 is connected to an external AM transformer (T2). The output of the transformer is ac coupled to the AMI input pin through a 0.1 uF capacitor (C13). Ensure R5 is populated for loop antenna reception and J35 is shorted for conducted tests. The output of C13 is connected to the AMI input pin. Components should be placed close to the IC to minimize trace lengths. Shunt Capacitors C23 and C27 are plac eholders for filtering caps on the EVB. They may not be required in actual application.
Figure 4. Si477x System Interface Schematic
Figure 5. Si477x System Interface Layout (0.1 µF). Place these capacitors as close as possible to the VA pin, with the 100 pF capacitor closest to the pin. traces and vias. See Figure 6.
Figure 6. Si477x VA Supply Bypassing Layout and DACREF bypassing should be connected to the system ground plane. than the via. See Figure 7, “Si477x VD/VIO1/VIO2 Supply Bypassing Layout”. pin and the capacitor to the system VIO supply such that the capacitor is closer to the Si477x VIO pin than the via. provided by the Si477x internally. See Figure 7, “Si477x VD/VIO1/VIO2 Supply Bypassing Layout”.
Figure 7. Si477x VD/VIO1/VIO2 Supply Bypassing Layout racy must be within ±100 ppm. used instead of a crystal, route the clock through series capacitor C12 to XTAL2 and leave XTAL1 floating (NC). Route the RCLK trace as far away from digital I/O traces as possible to minimize capacitive coupling. OUT (Pin 32) and ROUT (Pin 33). For analog audio and FM MPX information, refer to the Si477x data sheet.
8 Rev. 0.3 1.5.4. Control Interface All control interface signals operate at VIO1 supply levels. Route all control interface traces on Layer 2 to minimize coupling to the RF front-end. SDA and SCL (Pins 16 and 17) are an I 2C-compatible serial port slave interface, which allows an external controller to send commands and receive responses from the Si477x. Both the SDA and SCL signals require external pull-up re sistors to VIO1. The value of pull-up resistor valu es will vary based on the number of devices, capacitance, and speed of the bus. Placement location is not critical. Refer to the I2C specifica- tion for additional design information. For I2C Control Bus information, refer to the Si477x data sheet. A0 and A1 (Pins 11 and 12) select the I2C device address. Leave each pin either floating (NC) or connected to the system ground. For I2C Device Address selection, refer to the Si477x data sheet. RSTB (Pin 15) is the global chip rese t input. Setting the RSTB pin low disables analog and digital circuitry, resets the registers to their default settings, and disables the bus. Setting the RSTB pin hi gh brings the device out of reset. For Reset, Powerup, and Powerdown information, refer to the Si477x data sheet. INTB (Pin 18) is an active low interrupt output. See “AN645:Si477x Programming Guide” for interrupt configuration. Series termination resistors may be added to the SDA, SCL, and INTB traces to mitigate system noise and control slew rate. Confirm that data sheet timi ng requirements are met with the select ed series termination resistor value. Place the series termination resistors for SDA and INTB as close to the Si477x as possible. Place the series termi- nation resistor for SCL close to the host controller. 1.5.5. Digital Audio Interface The digital audio interface includes data serial lines contai ning audio data (DOUT, Pin 27), a bit clock (DCLK, Pin 29), and a word frame for left- and right-channel data (DFS, Pin 28). For Digital Audio Interface information, refer to the Si477x data sheet. All digital audio signals operate at VIO2 supply levels. Route all digital audio traces on Layer 3 to minimize coupling to the RF front-end. Series termination resistors may be added to the DOUT, DCLK, and DFS traces to mitigate system noise and control slew rate. Confirm that data sheet timing requirements are met with the selected series termination resistor value. Place the series termination resistors for DCLK and DFS as close to the host controller as possible. Place the series termination resistor for DOUT close to the Si477x.
data (IOUT/QOUT, Pins 25/26), a bit clock (IQCLK, Pin 23), and a word frame for each data sample (IQFS, Pin 24). Connect these traces to the I/Q input of the HD Radio Demod. implementation is shown below in Figure 8. Figure 8. System Implementation of HD-Radio Reception with IBOC Blend
without RF performance degradation. Figure 9. Si477x Ground Paddle Via Placement ground fill to lower thermal resistance. PCB material is recommended for best thermal and RF performance due to its thermal conductivity.
Rev. 0.3 11 1.7. Design Checklist* Place VA bypass capacitors C1, C2, and C21 as close as possible to the Si477x supply pin. Place VD bypass capacitors C3 and C20 as close as possible to the Si477x supply and digital bypass (DBYP) pins. Place VIO1/VIO2 bypass capacitors C4 and C5 as close as possible to the Si477x supply and digital bypass pins (DBYP). Route supplies using wide, low-inductance traces. Ensure that each trace is rated to handle the required current. Route all supply connections through a via such that the bypass capacitors are closer to the Si477x supply pins than the source via. Place crystal X1 as close as possible to the Si477x XTAL1/XTAL2 pins. Select a crystal with accuracy of ±100 ppm. Place the Si477x close to the antenna connector to minimize RF front-end trace lengths and capacitance and to minimize inductive and capacitive coupling. Route all traces to minimize inductive and capacitive coupling by keeping digital traces away from analog and RF traces, minimizing trace length, minimizing parallel trace runs, and keeping current loops small. Route digital traces between ground planes for best performance. Add series termination resistors to digital signals if necessary to mitigate noise coupling. Ensure timing specifications are maintained when adding series terminations. Connect the Si477x ground pad to the ground plane using multiple vias to minimize ground potential differences and achieve optimal thermal performance. Do not route signal traces under the Si477x. Do not route digital or RF traces over breaks in the ground plane. Flood the primary and secondary routing layers with separated RF and system grounds, and connect all layers using stitching vias. PCB size should be no less than 3 x 5 cm in a two-layer module application. Use 2 oz Cu and FR4-370 PCB material for best thermal performance. Place 20-mil diameter vias at the IC ground paddle to for heat dissipation. Use NC pins and I2C address lines pins 9-10 to connect ground paddle to top layer ground. The ground area should be as large as possible with many ground vias on it. *Note: Design checklist is listed in order of importance.
Table 1. Si477x FM/AM Bill of Materials
Table 1. Si477x FM/AM Bill of Materials (Continued)
14 Rev. 0.3 DOCUMENT CHANGE LIST Revision 0.1 to Revision 0.2 Updated "1.3.1. FM Front-End" on page 3. Revision 0.2 to Revision 0.3 Updated Table 1 on page 12. Updated T1 designator part number.
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