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facilitate the straightforward implementation of a two-state, half-bridge Class D amplifier. modulator, as shown in Figure 1. Figure 1. Si8241-Based Class D Amplifier Block Diagram
2 Rev. 0.1 2. The Si8241 Audio Gate Driver Every so often, a new IC is introduced that challen ges the current technological hegemony. With features that make these products the perfect driver s for Class D amplification, the Silicon Labs Si8241/44 Au dio Gate Drivers represent a new standard for the Class D amplifier industry. Key features are outlined in the following sections. 2.1. Programmable Dead Time It is well documented that a precise dead time setting is cr itical in Class D amplifiers. During dead time, both the high-side and low-side MOSFETs are off. However, the low-side MOSFET body diode continues to conduct current, which manifests itself as output distortion. Too short a dead time causes shoot-through current that reduces system efficiency; too long a dead time increa ses THD, negatively impacting audio quality. While competing audio drivers typically have coar se, digital dead-time settings (i.e. 1 of n delay values), the Si8241/44 Audio Gate Drivers have a precise linear dead time settin g that programs with a single external resistor. This feature provides the resolution necessary to precisely set dead time for optimal system performance. The Audio Gate Driver dead time equation is shown in Equation 1. Equation 1. Audio Gate Driver Dead Time Per Equation 1, the Silicon Labs Class D amplifier uses a 2 k resistor to generate 20 ns of dead time. Changing this dead time value to 18 ns only requires changing the RDT to 1.8 k (connected from the dead-time pin (DT) input to ground). This setting mechanism allows dead time to be incrementally increased or decreased in nanosecond increments, instead of tens of nanoseconds like competitive products. 2.2. Input/Output Isolation Implementing a two-state, Class D amplifier can be diffic ult due to input level shifting requirements, and most available Class D drivers lack the capabilit y to eliminate level shifti ng. Drivers that do elim inate level shifting have other peculiarities making them less-than-ideal for Class D operation (example: driver output ground terminal referenced to the –VBUS rail, requiring the input drive sign al to be level-shifted). This is not the case with the Si8241 Audio Gate Driver where the isolation (i.e. level sh ift function) is implemented internally and is transparent to the user. The Si8241 Audio Gate Driver controlled by TTL input signal levels drives the outputs to ±VBUS, and only a single TTL PWM input signal is required to drive a two-state Class D amplifier. 2.3. High-Voltage Outputs The Si8241 is capable of switching very high voltages (up to a 1,500 Vdc peak driver-to-driver differential voltage is possible) allowing a ±750 VBUS. For practical Class D amplifier designs, a voltage of ±100 Vdc can deliver an astounding 600 W of audio power into 8 . 2.4. Output Current Drive Class D amplifier switching MOSFETs should not be "slammed" on and off by excessively high current gate drivers. With its 0.5 A peak current outputs, the Si8241 Audio Gate Driver hits the sweet spot for Class D operation up to 400 W. Power levels beyond 400 W typically require larger MOSFETs and, consequently, more gate drive. For applications of this type, the Si8244 (4A) Audio Gate Driver provides the required added gate drive, where rise and fall times can be adjusted with a series gate resistor. 2.5. High-Frequency Operation One of the best attributes of the Si8241 Audio Gate Driver is its 8 MHz maximum switching frequency, making it the fastest driver on the market for Class D operation. The Silicon Labs Class D reference design operates at approximately 500 kHz, and operating the amplifier be tween 500 kHz and 1 MHz dramatically reduces the high- frequency artifacts, resulting in a remarkably clean audio waveform. DT 10R DT where Dead Time (DT) is in ns and RDT is in k
- Reference Design Board Architecture
demonstrates the benefits of using the Si8241 Audio Gate Driver. controlled output signal C(t), where s = j. Figure 4. First Order Control Loop Model the feedback transfer function, and E(s) is the error signal (i.e., the difference between the input and output).
Rev. 0.1 5 6. Closed Loop Transfer Function The closed loop transfer function is de fined as the ratio of the controlled variable to the input variable. The controlled variables are the speaker terminals, and the in put variable is the MP3 player input, the CD input, or some other input source connected to the amplifier. Therefore, the equation for the closed-loop transfer function is given by Equation 7. Equation 7. Closed Loop Transfer Function The closed loop gain describes how the output responds over the audio bandwidth to the input regulation signal. It is understood that the output should have a specific closed loop gain with respect to the input regulation signal, and that gain should be as flat as possible over the audio bandwidth. The inductor between the controlled variable and the speaker terminals plays a crucial role in the perform ance of the amplifier as prev iously discussed. The closed loop gain of the Silicon Labs Class D reference design is impl emented such that appro ximately 1 Vpp input will yield full output power into an 8 load. 7. Open Loop Transfer Function The open-loop transfer function is obtained by breaking the loop at some arbitrary point and traversing the entire loop back to the same point. When H(s) = 1, the open loop and the forward transfer functions are identical. Therefore, the open loop transfer function is given by Equation 8. Equation 8. The open loop transfer function determines whether the loop is stable, as well as determining what the overall open loop gain of the amplifier will be over the audio bandwidth. The higher the open loop gain, the lower the error signal and, therefore, the more ea sily the control loop can keep the out put following the input command. Some early Class D amplifier designs used an integrator for the error amplifier. This produced high gain at low frequencies but low gain at high frequencies due to the pole produced by the integrator. This caused the THD to increase dramatically above 5 kHz, destroying the high-frequency resp onse of the amplifier. A better solution is to keep the open loop gain constant and as high as possible throughout the audio bandwidth. This should yield a constant THD response, and, indeed, it does, as will be shown in the performance curves in "13. Performance" on page 8. Care should be taken in designing the open loop response of the amplifier. The three key elements are the bandwidth, phase margin, and gain margin. In designing a Class D amplifier, the target is to have 45° of phase margin with a bandwidth of approximately half the switching frequency. The control loop cannot compensate for the LC filter response since the filter is outside of the loop. Th e entire LC filter is designed as a Bessel function with a load resistance of 6 . Therefore, the filter is slightly underdamped at 8 and slightly overdamped at 4 . This can be seen by placing a 100 mVpp square wave into the in put and looking at the output response with an 8 load and a 4 load. Closed_Loop_Transfer_Function G(s) Open_Loop_Transfer_Function G(s)H(s)=
6 Rev. 0.1 8. Self Oscillation The amplifier is self-oscillati ng, enabling its signal-t o-noise ratio to far exceed that of a clock driven system. The main mechanism for this is the delta-sigma effect of shifting in-band noise to a much higher out-of-band frequency. The amplifier is a basic, phase-shift type, which has significant advantage s over an amplifier running as a hysteretic oscillator. There is a pole in the forward path G(s) and a pole in the feedback path H(s). The 180 ° phase shift, coupled with the transport delay, yields an oscillation frequency of nearly 500 kHz. The transport delay is given by Equation 9, where “t” is the delay of the comparator plus the Si8241. Equation 9. Taking into consideration the delay tolerances of the comparator and Si8241 driver, the total delay can range from 90 ns to 140 ns. The frequency of oscillation occurs at the point when t he open loop transfer function phase response times the transport delay is equal to –180 °. Equation 10. The frequency of oscillation is set by capacitors in each audio channel where reducing capacitance value increases oscillation frequency. Tight tolerance capacitors are used to k eep the channel frequencie s as close to each other as possible. 9. Drive Voltage The upper and lower gate driv e voltages can be gene rated by a linear regulator (the regulator used in the Silicon Labs Class D reference design is a high-voltage regulator able to withstand a 125 V input). When referenced to the negative supply, the regulator generates a low-side MOSFET drive voltage of –38 V (i.e., 12 V of gate drive with respect to the source). Likewise, the bootstrap capacitor charges to 12 V when the phase lead swings to the negative rail. The only downside to using a linear regulator is the power dissipation, which is directly-proportional to the frequency of the switching amplifier and the bus voltag e. Alternatively, a small, high-frequency switching regulator may be used to reduce the power dissipation of the MOSFET gate drive supply, but this can add unwanted system noise. TDelay e tj –= FOSC occurs when: Arg(G(s)H(s) e ts– )1 8 0 –=
Rev. 0.1 7 10. Overcurrent Protection The Silicon Labs Class D reference desi gn has an overcu rrent protection circuit co nsisting of a low-power comparator floating off the upper and lower bus voltages. The upper rail circuit is shown in Figure 5 and is duplicated on the lower rail. It monitors the current flowing through the 0.005 resistor (RSENSE) (Zener diode D1 and resistor R5 supply power to the comparator and the Silicon Labs Si8410 digital isolator). The Si8410 performs the necessary level shifting to interface to the shutdown circuitry. The circuit is set to trip at roughly a 20 A fault, usually caused by a short-circuit across the speaker terminals or a large overdrive signal at the audio inputs. Note that the upper and lower overcurrent circuits are ORd together through a pair of diodes and sent to the reset control circ uit. The normally low Si8410 A1 input is driven high upon detection of an overcurrent condition and asserts the SHUTDOWN signal, forcing the reset controller to assert a reset signal, momentarily halting amplifier operation. The reset control circuit attempts restart after one second, and, if the fault is still pres ent, again cycles reset in "hiccup" mode with a frequency of one second. This process continues until the fault is removed.Figure 5. Overcurrent Protection Circuit 11. Undervoltage Protection The undervoltage protection comparator monitors the posi tive bus voltage and releases the undervoltage lockout when the voltage is above 37 V, and the amplifier star ts-up after a one-second delay. Note that the red LED remains lit when the amplifier is in shutdown mode and turns off when the amplifier is enabled. 12. Other Features A protection circuit jumper option is in cluded that allows the amplifier to be manually shut down. This jumper can be replaced with a switch or other control circuit, allowing the amplifier to be muted. The one-second undervoltage lockout delay allows the opamps and comparator to settle before the shutdown circuit is released, thereby preventing speaker pops. There are also individual jumper options on each channel that allow the user to enable or disable each channel independently to aid in system performance evaluation. Si8410 Digital Isolator RSENSE GND2 GND2 GND1 VDD1 VDD1 To High Side MOSFET VDD2 SHUTDOWN 50V
Rev. 0.1 11 14. Summary Class D amplification offers advantages far above traditio nal analog amplifiers, including lower total harmonic distortion (THD), smaller size, higher power efficiency, an d lower cost. The gate driver IC can impact both system architecture and performance. Silicon Labs Si824x Audio Gate Drivers offer benefits not available in co mpetitive driver solutions. These benefits include high resolution dead time setting for the lowest poss ible THD and best efficiency, no input signal level shift circuits to complicate design and increase component count, and isolated output drivers for easy two-state switcher implementation. 15. References Simple Self-Oscillating Class D Amplifier with Full Output Filter Control - Putzeys, AES convention paper, 2005 May 28 Introduction to Control Systems Design, Eveleigh - McGraw-Hill, 1972
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