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of each device. Therefore, achieving the lowest clocking jitter requires careful management of the power supply. (PSRR). For jitter, ripple rejection is more appropriate. a finite slope as shown in Figure 1. Figure 1. Changing Thresholds Due to Power Supply Noise capacitors given a constant voltage.
Rev. 0.2 3 By subtracting these signals, the supply noise is rejected. A concern here is the receiver's ability to reject common- mode noise. This is referred to as common-mode ripple re jection (CMRR). Just as in the CMOS gate, fast rise/fall times help. External filtering may be necessary for designs that do not support differential signaling. Many timing devices with CMOS/TTL interfaces fail to account for power supply ripple. System designers should verify ripple rejection on the bench. 3.2. Circuit Choices Architectural choices also play a role in ensuring good jitter performance when subjected to power supply ripple. Timing devices often rely on phase-locked loops (PLLs) to perform various functions, such as jitter filtering and frequency multiplication. One of the primary challenges in PLL design is associated with its voltage-controlled oscillator (VCO). To meet the frequency requirements for a variety of ap plications, it is often necessary to have a wide tuning range oscillator, but oscilla tor jitter is proportional to the noise at its control input (often its most sensitive port). To reduce the jitter, it is necessary to have a low-gain control input, but the lower limit for the gain is set by the range of frequenc ies required and the frequency impairments of the osc illator (e.g., process variation, temperature, strain, etc.) This gain limitation can be overcome with novel circuit techniques, such as those employed by Silicon Laboratories' DSPLL™ technology. DSPLL utilizes a digitally-controlled, variable-gain oscillator; DSPLL can provide both a large tuning range and low gain, thereb y minimizing its sensitivity during operation. Furthermore, most timing integrated circuits operate from low supply voltages (less than 5 V). As the voltage is reduced with shrinking process geometries, the control port tuning range is limited as well. To achieve all of the output frequencies, the tuning port gain must be increased. Also, as the supply voltage is reduced, the tuning signal amplitude decreases relative to the noise (i.e., reduced SNR). Higher gain and reduced SNR yields poor jitter performance. It is critical to choose timing devices, such as those employing DSPLL™ by Silicon Labs, which have solved these problems. DSPLL™ supports both low-voltage supplies and improved SNR by using a digital interface for its controlled oscillator. A digital interface allows the SNR to remain high and the gain to be set arbitrarily low regardless of the supply voltage level. The SNR remains high because the tuning range is not limited by the supply voltage. Other architecture choices also help: eliminating VCOs removes the concern over the tuning gain and interference altogether. Silicon Laborator ies MultiSynth technology provides an y-frequency synthesis simultaneously on multiple outputs using only a single VCO per IC. By employing only one VCO, Silicon Labs has increased functional density without increasing interference.
Rev. 0.2 7 NOTES:
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