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include schematic, BOM, layout, and design checklist. Table 1. Supported Devices and Antennas
2 Rev. 0.5
Rev. 0.5 3 TABLE OF C ONTENTS Section Page
4 Rev. 0.5 2. Si474x 4x4 mm QFN Schematic and Layout This section describes the minimum schematic and layo ut options required for optimal Si474x performance. Population options are provided to support layouts for different audio output options and mitigation of system noise. 2.1. Si474x 4x4 mm Design C1 (22 nF) is a required bypass capacitor for VDD supply pin 13. Place C1 as close as possible to VDD pin 13 and GND pin 14. Place a VIA connecting C1 VDD supply to the power rail such that the cap is closer to the Si474x than the VIA. Route C1 GND directly and only to GND pin 14 with a wide, low-inductance trace. These recommendations are made to reduce the size of the current loop created by the bypass cap and routing, minimize bypass cap impedance, and return all currents to the GND pad. C13 (22 nF), C17 (100 µF), and C19 (0.1 µF) are optional bypass capacitors for the VIO supply pin 12 and may be placed to mitigate supply noise. Place C13, C17, and C19 as close as possible to the VIO pin 12 and the GND pin 14. Place VIAs connecting C13, C17, and C19 VIO supply to the power rail such that the capacitors are closer to the Si474x than the VIAs. Route C13, C17, and C19 GND directly and only to GND pin 14 with wide, low- inductance traces. These recommendations are made to reduce the size of the current loop created by the bypass capacitors and routing, minimize bypass cap impedance, and return all currents to the GND pad. C2 (2 pF) is a required shunt capacitor from the DFS pin to ground when using digital audio output (Si4741/43/45 only), and is used to prevent degradation of audio quality. Place the capacitor as close as possible to the DFS pin. C6 (0.1 µF) and C18 (100 µF) are optional bypass capacitors to mitigate system noise in AM and FM frequencies. Route them the same way as C1. C8 and C9 (0.39 µF) are ac coupling capacitors for analog audio output from ROUT pin 15 and LOUT pin 16. The input resistance of the amplifier and the capacitor will set the high-pass pol e given by Equation 1. Placement location is not critical. Equation 1. High-Pass Pole Calculation R12, R14, R26, R29, and R30 (25 to 2 k) are optional series termination resistors used to mitigate system noise. The recommended value of the resistors is 2 k for optimal edge rate and no ise suppression. Confirm that timing requirements are met with the selected series te rmination resistor value. Pl ace the series termination resistors, R12, R14, R21, R24, R26, R29, and R30, as close to the host controller as possible. R21 and R24 (25 to 2 k ) are optional series termination resist ors used to mitigate system noise. The recommended value of the resistors is 2 k for optimal edge rate and noise suppression. Confirm that timing requirements are met with the selected series termination resistor value. Place the se ries termination resistors, R21 and R24 as close to the chip input as possible. R17 and R20 (22 k) are optional pull-up resistors for the RSTB and SENB lines. The size of pull-up resistor value will vary based on the number of devices, capacitance, and speed of the bus. Placement location is not critical. R27 and R28 (22 k) are optional pull-up resistors for the SCLK a nd SDIO lines required only when using an I2C bus. The size of pull-up resistor value will vary based on the number of devices, capacitance, and speed of the bus. Placement location is not critical. Refer to the I2C specification for additional design information. R16 (25 to 2 k) is a required series termination resistor when using digital audio output (Si4741/43/45 only) and is used to mitigate noise from the digital data routed from DOUT pin 17. The recommended value of the resistor is 604 for optimal edge rate and noise suppression. Confir m that timing requirements are met with the selected series termination resistor value. Place R16 as close to pin 17 as possible. R15 (25 to 2 k) is a required series termination resistor wh en using digital audio (Si4741/43/45 only) and is used to mitigate noise from the digital clock routed to GPO3/DCLK pin 19. The recommended value of the resistor is 2 k for optimal edge rate and noise suppression. Confir m that timing requirements are met with the selected series termination resistor value. Place R15 as close to the host controller as possible. Choosing a DCLK frequency that is above the AM band reduces the chances of having DCLK harmonics that fall in the AM band and create digital noise. fc
series termination resistor value. Place R11 as close to the host controller as possible. recommended RCLK and prescalar values. band. The recommended value is chosen such that DFS will still meet t he voltage and timing requirements of I2S. Place R2 and R13 as close as possible to DFS pin 18. Figure 1. Si474x 4x4 mm QFN Schematic
The required bill of materials for Figure 1 is shown in Table 2. The optional bill of materials for Figure 1 is shown in Table 3. Table 2. Required Bill of Materials Table 3. Optional Bill of Materials
Rev. 0.5 9 2.5. Si474x 4x4 mm Design Checklist The following design checklist summarizes the guidelines presented in this section: Place bypass caps C1, C6, and C18 (for VDD) and C13, C17, and C19 (for VIO) as close as possible to the supply and ground pins. Place a VIA connecting C1, C6, and C18 (for VDD) and C13, C17, and C19 (for VIO) such that the cap is between the Si47xx and the VIA. Route a wide, low-inductance return current path from the C1, C6, C13, C17, C18, and C19 to the Si47xx GND pins. Place resistor R16 as close to DOUT pin 17 as possible. Place the series termination resistors, R12, R14, R21, R24, R26, R29, and R30 as close to the host controller as possible. Place the pull-up/pull-down resistors, R2, R13, R22, and R23, as close to the DFS (pin 18) and RCLK (pin 11) as possible. Place shunt cap C2 from DFS to gnd and as close to DFS (pin 18) as possible. Place a ground plane under the device as shown in Figure 4, “Two-Layer Stackup”. Place a local ground plane directly under the device for designs in which a continuous ground plane is not possible. Route all traces to minimize inductive and capacitive coupling by keeping digital traces away from analog and RF traces, minimizing trace length, minimizing parallel trace runs, and keeping current loops small. Route digital traces on the opposite side of the chip. Place stitching VIAs around digital traces to minimize current loop areas. Route digital traces RSTb, SENb, SCLK, SDIO, RCLK, DOUT, DFS, and DCLK away from and orthogonal to RF traces to minimize digital noise coupling onto RF traces. Choose DCLK and RCLK frequencies that fall above the AM band. Ensure that timing requirements are met for both RCLK and DCLK with higher frequencies. Refer to “AN332: Si47xx Programming Guide” for timing requirements. Route all GND (including RFGND) pins to the ground pad. The ground pad should be connected to the ground plane using multiple VIAs to minimize ground potential differences. Route power to the Si474x by trace, ensuring that each trace is rated to handle the required current. Do not route signal traces on the ground layer directly under the Si474x. Do not route signal traces under the Si474x without a ground plane between the Si474x and signal trace. Do not route digital or RF traces over breaks in the ground plane. If the design is flexible to have more than two layers, put the GND plane between RF signals and digital signals. Another improvement would be to put the digital signals between two GND planes. Do not route digital signals or reference clock traces near VCO pins 22 and 23 or LOUT/ROUT output pins 15 and 16. Do not route VCO pins 22 and 23 (NC). These pins must be left floating to guarantee proper operation. Do not route pin 24 (NC). This pin must be left floating to guarantee proper operation. Do not route pin 4 (NC). This pin must be left floating to guarantee proper operation. Flood the primary and secondary layers with ground and place stitching VIAs. Place the Si474x close to the antenna(s) to minimize antenna trace length and capacitance and inductive and capacitive coupling. This recommendation must be followed for optimal device performance. Route the antenna trace over an unobstructed ground plane to minimize antenna loop area and inductive coupling. Design, Place, and Route other circuits such that radiation in the band of interest is minimized. Tie unused pin(s) to GND, but do not tie No Connect (NC) or unused GPO pins to GND.
C2 (18 pF) is the ac coupling capacitor going to the FMI pin. be changed to 33 nH to support FM band only for Si4740/41/44/45. parasitic capacitance, such as the California Micro Device CM1213. Figure 7. FM/WB Whip Antenna Schematic Model Table 5. FM/WB Whip Antenna Bill of Materials
12 Rev. 0.5 3.4. FM/WB Whip Antenna Layout Place the chip as close as possible to the whip antenna. This will minimize the trace length between the device and whip antenna, which, in turn, will mi nimize parasitic capacitance and the possibility of noise coupling. Place inductors L1, L2, and L5 and the antenna connector together and as far from potential noise sources as possible and away from the I/O signals of the Si474x. ESD diode is placed near the FMI pin in order to prevent strong input signals from clipping by the diode. 3.5. FM/WB Whip Antenna Design Checklist Maximize whip antenna length for optimal performance. Select L1, L2, and L5 inductor values to maximize signal strength across the FM and weather band. Place L1, L2, L5, and the whip antenna close together and as far from potential noise sources as possible to reduce capacitive and inductive coupling. Place the chip as close as possible to the whip antenna to minimize the antenna trace length. This reduces parasitic capacitance and hence reduces coupling into the antenna by noise sources. This recommendation must be followed for optimal device performance. Select ESD diode U1 with minimum capacitance. Place the ac coupling capacitor, C2, as close to the FMI pin as possible.
antenna connector as far from potential noise sources as possible and away from the I/O signals of the Si4749. Place ESD diode U1 as close as possible to the whip antenna input connector for maximum effectiveness. Maximize whip antenna length for optimal performance. Select matching inductor L1 with a Q of 25 or greater at 100 MHz and minimal dc resistance. Select the L1 inductor value to maximize signal strength across the FM band. must be followed for optimal device performance. Place ESD diode U1 as close as possible to the whip antenna for maximum effectiveness. Select ESD diode U1 with minimum capacitance. Table 6. Whip Antenna for RDS Receiver Bill of Materials
- Whip Antenna for AM/LW Receiver (Si4740/41/42/43/44/45 Only)
AM/LW/SW Receiver (Si4742/43/44/45 only)" on page 18. Figure 9. AM/LW Whip Antenna Schematic
16 Rev. 0.5 L6 (6.8 µH), C10 (3.9 pF), and L7 (6.8 µH) function as a filter for the FM frequency. C14 (0 , currently not used), L8 (47 mH), and R13 (10 k) act as a filter trap for the ac main line. C3 (270 pF) provides dc isolation from the ac main line trap as well as a minimum capacitance (in series with the antenna capacitance) for the switched attenuator. This minimum capacitanc e improves the "Passive" attenuator performance with lower impedance sources (even a direct 50 ), and, if max signal with active source (50 ) is below ~95 dBµV, the "Active" attenuator option is no longer required. R1 (10 M) is the bias resistor for transistor Q1. C7 (1200 pF) is used for the passive whip antenna by turning on Q3. R8 (1 ) is used for the active whip antenna by turning on Q4. The R8 value is chosen to meet and exceed 40 dB SINAD at 120 dBµV AM input from an active (50 ) antenna. Different designs mi ght have active antenna AGCs that keep the peak signal level below ~95 dBµV. In these cases, the passive-only option is adequate. If the design requirements are such that peak signal will be between 95 and 120 dBµV, R8 should be increased until the SINAD requirement at max signal level is met. The ATTN _BACKUP field in the AM_F RONTEND_AGC_CONTROL can then be optimized against the new value of R8 per the procedure described in AM_FRONTEND_AGC_CONTROL property in “AN344: Si4706/07/4x Programming Guide”. Q3 and Q4 (MMBTH10), R4 and R9 (249 ) along with U3 (74LVC02) and R5 (4.7 k) are the circuits to switch C7 for a passive whip antenna or R8 for an active whip antenna by using the GPIO1 signal. U4 is a required ESD diode since the antenna is exposed. The diode should be chosen with no more than 1 pF of parasitic capacitance, such as the California Micro Devices CM1213. Q1 and Q2 (BF862 N-FET transistors) are configured in a cascode architecture to amplify the input signal coming from the whip antenna. L4 (1 mH) provides dc bias for the cascode amplifier and has a high impedance at AM/LW. L10 (33 µH), C4 (18 nF), and Si474x AGC provide AM/LW gain control via cascode source degeneration. R15 is Not Populated for the standard Si4743 board build that supports LW. Replace R15 with a 0 resistor for the Si4741 board that does not have LW support. L3 (220 µH) sets the gain of the amplifier along with th e source degeneration load. L3, combined with the on-chip varactor, also functions as the AM tracking filter. Q > 55 at 1 MHz is required. R6 (249 ), R7 (249 ), and C9 (0.47 µF) provide the bias voltage for the cascode transistor. R3 (10 ), C8 (0.47 µF), and C12(100 µF) filter the power supply noise. C5 (0.47 µF) is an ac-coupling capacitor going to the AMI pin. L9 (2.7 mH) sets the gain of the amplifier along with the source degeneration load when the LW option is selected. L9, combined with the on-chip varactor, also functions as the LW tracking filter. Q5 (MMBTH81 pnp transistor) is a transistor to bypass L9 if the dual AM or LW support option is selected. R10 (249 ), R18 (4.7 k), Q6 (2N7002 N-FET), C15 (0.1 µF), and R19 (4.7 k) are circuits to drive the Q5 switch if the LW support option is selected.
Table 7. AM/LW Whip Antenna Bill of Materials
potential for noise coupling. Place the Q3 collector directly next to C7, and place the Q4 collector directly next to R8. Maximize whip antenna length for optimal performance. Place the LNA amplifier as close as possible to the whip antenna. Place the chip as close as possible to the LNA amplifier. SDIO, RCLK, GPO3/DCLK, DFS, and DOUT.
- Whip Antenna for AM/LW/SW Receiver (Si4742/43/44/45 only)
Please contact Silicon Labs Application Support for the recommended schematic and antenna layout. Table 7. AM/LW Whip Antenna Bill of Materials (Continued)
Rev. 0.5 19 DOCUMENT CHANGE LIST Revision 0.4 to Revision 0.5 Updated Table 1, “Supported Devices and Antennas,” on page 1. Added Section “6. Whip Antenna for AM/LW/SW Receiver (Si4742/43/44/45 only)”. Made the schematic reference designators to be the same as the EVB schematic. Added shunt capacitor C2 from DFS to ground to prevent degradation of audio quality when in digital mode. Recommended values for R2, R13, R11,R16 changed. Recommended leaving unused GPO pins floating.
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