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includes schematic, BOM, layout and design checklist. appropriate antenna selections according to the application and device used presented in Sections 3 through 10. Table 1. Supported Devices and Antennas
2 Rev. 0.8
Rev. 0.8 3 TABLE OF C ONTENTS Section Page 5. Embedded Antenna for FM Transmit on TXO and Receive on LPI (Si4704/05/06/1x/2x 6. Cable Antenna for FM Transmit on TXO and Receive on LPI
4 Rev. 0.8
Rev. 0.8 5 2. Si47xx 3x3 mm QFN Schematic and Layout This section shows the minimal schematic and layout options required for optimal Si47xx performance. Population options are provided to support a si ngle layout for all 3 x 3 mm QFN devices, mitigate system noise, operate the internal oscillator with an external crystal, and filter VCO energy. 2.1. Si47xx 3x3 mm Design C1 (22 nF) is a required bypass capacitor for VD/VDD supply pin 11. Place C1 as close as possible to the VD/VDD pin 11 and GND pin 12. Place a via connecting C1 VD/VDD supply to the power rail such that the cap is closer to the Si47xx than the via. Route C1 GND directly and only to GND pin 12 with a wide, low inductance trace. C1 GND should not be routed to GND via. These recommendations are made to reduce the size of the current loop created by the bypass cap and routing, minimize bypass cap impedance and return all currents to the GND pad. Note: For Si47xx rev D parts, C1 is required on pin 11 (VA ). The C1 design guidelines described above should be followed. For an illustration of these guidelines, refer to Figure 3. C2 (22 nF) is an optional bypass capacitor for VA/LIN/D FS supply pin 16 (Si4702/03 only) and may be placed to mitigate supply noise. Place C2 as close as possibl e to the VA/LIN/DFS pin 16 and GND pin 15. Place a via connecting C2 VA supply to the powe r rail such that the cap is closer to the Si47xx than the via. Route C2 GND directly and only to GND pin 15 with a wide, low inductance trace. Route GND/RIN/DOUT pin 15 to the GND pad if designing only for the Si4702/03. If designing for all Si47xx devices, do not route G ND/RIN/DOUT pin 15 to the GND pad. In this case the on-chip connection between pin 15 and the GN D pad will provide a ground connection. These recommendations are made to reduce the size of the current loop created by the bypass cap and routing, minimize bypass cap impedance and return all currents to the GND pad. C3 (100 nF) is an optional bypass capacitor for the VIO su pply pin 10 and may be placed to mitigate supply noise. Place C3 as close as possible to the VIO pin 10 and the GND pin 12. Place a via connecting C3 VIO supply to the power rail such that the cap is closer to the Si47xx than the via. Route C3 GND directly and only to GND pin 12 with a wide, low inductance trace. C3 GND should not be routed to GND via. These recommendations are made to reduce the size of the current loop created by the bypa ss cap and routing, minimize bypass cap impedance and return all currents to the GND pad. Note: For Si47xx rev D parts, C3 is required on pin 10 (VD) . The C3 design guidelines described above should be followed. C6 and C7 (0.39µF) are ac coupling caps for transmitter audio input to VA/LIN/DFS pin 16 and GND/RIN/DOUT pin 15 (Si471x/2x analog audio input mode only). The input resistance of the transmitter audio input and the cap will set the high pass pole given by Equation 1. The input re sistance of the audio input is programmatically selectable as 396 k, 100 k, 74 k, or 60 k (default). Placement location is not critical. Equation 1. High-Pass Pole Calculation C8 and C9 (0.39 µF.) are ac coupling caps for receiver analog audio output from ROUT/DIN pin 13 and LOUT/DFS pin 14 (Si470x/2x/3x/8x audio output mo de only). The input resistance of the amplifier, such as a headphone amplifier, and the capacitor will determine the high pass pole given by Equation 1. Placement location is not critical. C10 and C11 (7–22 pF) are optional crystal loading caps required only when using the internal oscillator feature. Refer to the crystal data sheet for the proper load capaci tance and be certain to account for parasitic capacitance. Place caps C10 and C11 such that they share a common GND connection and the current loop area of the crystal and loading caps is minimized. C12 and C13 (2.2 pF) are noise mitigation caps if digital audio option is in use. The caps need to be placed close to the Si47xx chip. X1 (32.768 kHz) is an optional crystal required only when using the internal oscillator feature. Place the crystal X1 as close to GPO3/DCLK pin 17 and RCLK pin 9 as possible to minimize current loops. Route the RCLK trace as far from SDIO pin 8 and SDIO trace as possible to minimize capacitive coupling. R1 (0 ) is an optional jumper used to route the digital audio clock to GPO3/DCLK pin 17. R1 is only required for a universal design which accommodates BOM population options selecting between crystal and digital audio fc
6 Rev. 0.8 Note: Crystal and digital audio mode cannot be used at the same time. Populate R1 and remove C10, C11, and X1 when using digital audio. Populate C10, C11, and X1 and remove R1 when using the internal oscillator. Place resistor R1 as close to DCLK/ GPO3 pin 17 as possible as shown in Layout Example 4 to minimize trace length from pin 17 to the crystal and load cap. R2-R6 (25 –2 k) are optional series termination resistors and are used to mitigate system noise. The recommended value of the resistors is 2 k for optimal edge rate and noise suppression. Confirm that timing requirements are met with the selected series termination resistor value. Place the series termination resistors R2- R6 as close to the host controller as possible. R7 and R8 (4.7 k ) are optional pull-up resistors for the SCLK and SDIO lines required only when using an I bus. The size of pull-up resistor value will vary based on the number of devices, capacitance and speed of the bus. Placement location is not critical. Refer to the I2C specification for additional design information. R9 (0 ) is used to route power to VA/LIN/DFS supply pin 16. R9 is only required to support a layout for all 3x3 mm QFN devices. If designing for the Si4702/03 only R9 ma y be replaced with trace connections. If designing for Si4704/05/06/07/1x/2x/3x/8x only, R9 is not required. Place resistor R9 as close to VA/LIN/DFS pin 16 as possible. R10 (0 ) is an optional jumper used to route the VA pin 16 for Si4702/03. R10 is only required for a universal design which supports BOM options for the Si4702/03 an d other Si47xx devices. R10 should be populated when using an Si4702/03 and not populated when using an alternate device. R11 (0 ) is an optional jumper used to route the DFS to VA/LIN/DFS pin 16. R11 is only required for a design in which the Si4702/03 and digital audio output (Si4705/0 6/21/31/35/37/39/8x) BOM op tions are desired. Place resistor R11 as close to pin VA/LIN/DFS 16 as possible. R12 (25 –2 k) is a required series termination resistor when using digital audio output (Si4705/06/21/31/35/37/ 39/8x) and is used to mitigate noise from the digital data routed from GND/RIN/DOUT pin 15. The recommended value of the resistor is 604 for optimal edge rate and noise suppression. Confirm that timing requirements are met with the selected series termination resistor value. Place R12 as close to pin 15 as possible. R13 (25 –2 k) is a required series termination resistor when using digital audio (Si4705/06/1x/2x/31/35/37/39/8x only) and is used to mitigate noise from the digital clock routed to GPO3/DCLK pin 17. The recommended value of the resistor is 2 k for optimal edge rate and noise suppression. Confirm that timing requirements are met with the selected series termination resistor value. Place R13 as close to the host controller as possible. R14 (25 –2 k) is a required series termination resistor when using digital audio output (Si4705/06/21/31/35/37/ 39/8x) and is used to mitigate noise from the digital frame clock routed to VA/LIN/DFS pin 16. The recommended value of the resistor is 2 k for optimal edge rate and noise suppression. Confirm that timing requirements are met with the selected series termination resistor value. Place R14 as close to the host controller as possible. R15 (25 –2 k) is a required series termination resistor when using digital audio input (Si471x/2x only) and is used to mitigate noise from the digital frame clock ro uted to LOUT/DFS pin 14. The recommended value of the resistor is 2 k for optimal edge rate and noise suppression. Co nfirm that timing requirements are met with the selected series termination resistor value. Place R15 as close to the host controller as possible. R16 (25 –2 k) is a required series termination resistor when using digital audio input (Si471x/2x only) and is used to mitigate noise from the digital data routed to ROUT/DIN pin 13. The recommended value of the resistors is 2k for optimal edge rate and noise suppression. Confirm that timing requirements are met with the selected series termination resistor value. Place R16 as close to the host controller as possible. R17 (0 ) is an optional jumper used to route the GND pin 15 for Si4702/03. R17 is only required for a universal design which supports BOM options for the Si4702/03 an d other Si47xx devices. R17 should be populated when using an Si4702/03 and not populated when using an al ternate device. Place R17 as close to the Si47xx as possible. R18 (0 ) is an optional jumper used to route the GND pin 4 for Si4702/03. R18 is only required for a universal design which supports BOM options for the Si4702/03 an d other Si47xx devices. R18 should be populated when using an Si4702/03 and not populated when using an al ternate device. Place R18 as close to the Si47xx as possible.
Checklist” for detailed layout and grounding recommendations pertaining to the components described below. pin functionality is not used. ground path should be optimized on the top layer. Route pin 2 to GND/RFGND if the pin functionality is not used. the pin functionality is not used. Table 2. FMI Mitigation Components Table 3. AMI Mitigation Components
the pin functionality is not used. down by design and has no other connections. down by design and has no other connections. optimized on the top layer. Route pin 4 to GND/RFGND if the pin functionality is not used. as close as possible to TXO/LPI pin 4. Route pin 4 to GND/RFGND if the pin functionality is not used. Table 4. GPIO Mitigation Components
1 C15 = 33 pF
2 C15 = 33 pF
Table 5. LPI Mitigation Components
Figure 1. Si47xx 3x3 mm QFN Schematic
The required bill of materials for Figure 1 is shown in Table 6. The optional bill of materials for Figure 1 is shown in Table 7. Table 6. Required Bill of Materials For supply noise mitigation. Optional for Si47xx rev C and earlier parts. For Si47xx rev D parts, C3 is required. Table 7. Optional Bill of Materials
Table 8. Optional Bill of Materials: Emissions Mitigation
3x3 mm QFN devices and features. Table 9. Layout Example Selector Guide by Place and Route Requirements Table 10. Layout Example Selector Guide by Option Table 11. Layout Example Selector Guide by Device
Rev. 0.8 17 Do not route VCO pin 1 and 20 (NC). These pins must be left floating to guarantee proper operation. Place the Si47xx close to the antenna(s) to minimize antenna trace length and capacitance and to minimize inductive and capacitive coupling. This recommendation must be followed for optimal device performance. Route the antenna trace over an unobstructed ground plane to minimize antenna loop area and inductive coupling. Design, place, and route other circuits such that radiation in the band of interest is minimized. Tie unused pin(s) to GND, but do not tie No Connect (NC) pins to GND. For example, in Si471x FM transmitter analog audio input mode, DFS pin 14 and DIN pin 13 are not used; therefore, these two pins should be tied to GND. 2.6.1. Emissions Mitigation Checklist The following design checklist summari zes the guidelines for mitigating emissions in the 3–4 GHz range, if applicable. Place F1 as close as possible to FMI pin 2. Place C14 as close as possible to FMI pin 2. Place C5 even though it is designated as NP, it should be as close as possible to FMI pin2. On the Si4704/05/06/1x/2x products: Place C4 as close as possible to LPI/TXO pin 4 and RFGND pin 3. Place L1 as close as possible to LPI/TXO pin 4. On Si473x products: Place C16 as close as possible to AMI pin 4 and RFGND pin 3. Place L2 as close as possible to AMI pin 4. Place C17 as close as possible to AMI pin 4 and RFGND pin 3. Place C15 and C18 as close as possible to GPO1 & GPO2 pins. Place R19 and R20 as close as possible to GPO1 & GPO2 pins. Route FMI pin 2 to GND/RFGND if the pin functionality is not used. Route TXO/AMI/LPI pin 4 to GND/RFGND if the pin functionality is not used. Flood the primary and secondary layers with ground and place stitching vias between the GND fill and GND plane. Shunt capacitors C4, C5, C14, C15, C16, C17, and C18 should be connected directly to the GND plane on top layer. Do not use heat relief for these pad's GND connection. Connecting shunt capacitors only to a via to the GND plane is not sufficient; though it is permissible to have such a via if the top GND plane is also connected. If additional space is available, increase the size of RFGND trace by moving FMI and AMI signal paths further apart. Avoid unnecessary breaks in the top ground fill between the Si47xx and the system GND connection. The goal is to have the path from shunt capacitors as direct, unbroken, and wide as possible. Rotate the Si47xx (as necessary) in order to create the best ground path for the FMI and GPO mitigation as these are the greater contributors to emissions. Orient the shunt capacitor(s) on FMI (C14) to the right of the trace (towards pin 1). Orient the shunt capacitors on AMI (C16 & C17) to the right of the trace (toward RFGND, pin 3).
- Headphone Antenna for FM Receiver on FMI (Si470x/2x/3x/8x Only)
approximately half the FM wavelength (FM wavelength is ~3 m). of a typical application is shown in Figure 8, “Typical Headphone Antenna Application”. Figure 8. Typical Headphone Antenna Application
Figure 9. Headphone Antenna Schematic be required for proper implementation of any tuner. of 15 or greater at 100 MHz and minimal dc resistance. enough to cause negligible loss with an LNA input capacitance of 4–6 pF. The recommended value is 100 pF–1 nF. complete description of RSHUNT, RP, etc. California Micro Devices CM1210. Diode capacitance should be minimized to minimize CSHUNT, and therefore, CP. negative polarity ESD events. output voltage and the audio output is swinging above and below ground.
With the specified BOM components, the corner frequency of the headphone amplifier is approximately 20 Hz. manufacturer is not critical for resistors and capacitors. Table 12. Headphone Antenna Bill of Materials
Rev. 0.8 21 3.4. Headphone Antenna Layout To minimize inductive and capacitive coupling, inductor LMATCH and headphone jack J24 should be placed together and as far from noise sources such as cl ocks and digital circuits as possible. L MATCH should be placed near the headphone connector to keep audio currents away from the Si47xx. To minimize CSHUNT and CP, place ferrite beads F1 and F2 as close as possible to the headphone connector. To maximize ESD protection diode ef fectiveness, place diodes D1, D2 an d D3 as close as possible to the headphone connector. If capacitance larger than 1 pF is required for D1 and D2, both components should be placed between FB1 and FB2 and the headphone amplifier to minimize C SHUNT. Place the chip as close as possible to the headpho ne connector to minimize antenna trace capacitance, CPCBANT. Keep the trace length short and narrow and as far above the reference plane as possible, restrict the trace to a microstrip topology (trace routes on the top or bottom PCB layers only), minimize trace vias, and relieve ground fill on the trace layer. Note that minimizing capacitance has the effect of maximizing characteristic impedance. It is not necessary to design for 50 transmission lines. To reduce the level of digital noise passed to the antenna, RF shunt capacitors C5 and C6 may be placed on the left and right audio traces close to the headphone ampl ifier audio output pins. The recommended value is 100 pF or greater, however, the designer should confirm that the headphone amplifier is capable of driving the selected shunt capacitance. 3.5. Headphone Antenna Design Checklist Select an antenna length of 1.1 to 1.45 m. Select matching inductor LMATCH to maximize signal strength across the FM band. Select matching inductor LMATCH with a Q of 15 or greater at 100 MHz and minimal dc resistance. Place inductor LMATCH and headphone connector together and as far from potential noise sources as possible to reduce capacitive and inductive coupling. Place the Si47xx close to the headphone connector to minimize antenna trace length. Minimizing trace length reduces CP and the possibility for inductive and capacitive coupling into the antenna by noise sources. This recommendation must be followed for optimal device performance. Select ferrite beads F1–F2 with 2.5 k or greater resistance at 100 MHz to maximize RSHUNT and, therefore, RP. Place ferrite beads F1-F2 close to the headphone connector. Select ESD diodes D1-D3 with minimum capacitance. Place ESD diodes D1-D3 as close as possible to the headphone connector for maximum effectiveness. Place optional RF shunt capacitors near the headphone amplifier’s left and right audio output pins to reduce the level of digital noise passed to the antenna.
go through the shunt ferrite rather than going through the tuning inductor and/or Si47xx chip. to isolate the cable return currents from the FMI pin. does not filter the high frequency. Table 13. Bill of Materials F2 Series Ferrite bead, various types. frequency component of the signals.
24 Rev. 0.8 4.4. Cable Antenna Layout Place the chip as close to the cable antenna as possible. This will minimize the trace length going to the cable antenna which will minimize the parasitic capacitance. Place the shunt ferrite for the ground return current as close to the cable as possible. Putting the shun t ferrite for the ground return current close to the cable ensures that the ground return current has minimal loop whic h will reduce noise coupling. The series ferrites also should be put as close as possible to the cable. This will minimize the parasitic capacitance seen by the FMI pin. 4.5. Cable Antenna Design Checklist Place the chip as close as possible to the cable antenna to minimize parasitic capacitance. Place the tuning inductor, L1, as far away from noise sources as possible. Make sure that the shunt ferrite has a dc rating that exceeds the expected max ground return current of the cable. Place the shunt ferrite close to the cable. Choose series ferrite that is appropriate for each type of signal in the conductor. Place the series ferrite(s) close to the cable.
Rev. 0.8 25 5. Embedded Antenna for FM Transmit on TXO and Receive on LPI (Si4704/ 05/06/1x/2x Only) The FM Transmitter component on the Si471x/2x and the FM Receiver component on the Si4704/05/06/2x support an embedded antenna interface through the TXO/LPI pin. In the case of the Si472x FM Transceiver, the same embedded antenna can be used for both FM Transmit and Receive. 5.1. Embedded Antenna Design An embedded antenna can be designed using a loose wire, fl ex circuit, or PCB trace and can be categorized into two types: stub antenna and loop antenna. For the purp ose of this application note, three types of embedded antenna will be covered in detail: Embedded stub (wire) Embedded loop (wire) Embedded stub (PCB trace) The following table summarizes the advantages and disadvantages of these implementations. Figure 12 is an example of a stub antenna in wire implementation buried inside a cellular handset. Explanations of the dimensions A, B, C, and D are included later in this document. Antenna Description Advantages Disadvantages Embedded Stub (Wire) Wire attached to or molded inside product case Connect to pin 4 for TX/ RX Placement flexibility Minimum PCB space Easy to adjust length during design testing Mechanical attachment to case required Performance can be impacted by case shielding Embedded Loop (Wire) Wire loop attached to or molded inside product case Connect to pin 4 for TX/ RX Can achieve high efficiency per length Placement flexibility Minimum PCB space Easy to adjust length during design testing Mechanical attachment to case required Performance can be impacted by case shielding Embedded Stub (PCB Trace) Wire trace fabricated on outer PCB copper layer Connect to pin 4 for TX/ RX No mechanical attachment to case Ease of product assembly PCB keep out regions required around antenna Additional PCB space Performance can be impacted by case shielding
Figure 12. Stub Antenna in Wire Implementation
Use an ideal vertical wire antenna as a reference point to measure the performance of the wire antenna. wire antenna is bent parallel to the GND plane. trace is not obstructed by the ground plane, shield, or other metal structures (e.g., batteries). other end of the antenna is grounded. Because the other end is grounded, a loop antenna by itself is an inductor. inductor or capacitor and the on-chip shunt variable capacitor. Figure 15. Loop (Wire) Antenna—Side View
Figure 16. Rectangular Loop (Wire) Antenna—Orthogonal View Route the antenna as shown in Figure 16. incident voltage for receive. maximize incident voltage for receive. Antenna inductance for an ideal loop antenna is given by Lant = n²µ0r[ln(8r/b)]. Number of turns greater than one usually results in a high inductance loop with which the varactor cannot resonate. It is acceptable to place two loops in a parallel structure to reduce the effective inductance. approximately applied to a rectangular loop of the same circumference. Use an ideal vertical loop (wire) antenna as a reference point to measure the performance of the loop antenna.
trying different values of L1. It is even better if user sweeps the entire FM band and gets the READANTCAP values. to happen). L1 needs to be adjusted to a bigger value. The rest of the components in the embedded antenna schematic are optional. D1 is the ESD diode and it is only necessary when there is an exposed pad going to the TXO/LPI pin. exposed pad going to the TXO/LPI pin. Table 14. Embedded Antenna Bill of Materials exposed pad going to the TXO/LPI pin. exposed pad going to the TXO/LPI pin.
Rev. 0.8 33 5.4. Embedded Antenna Layout The placement of the chip going into the embedded antenna is critical. Place the chip as close as possible to the embedded antenna feedline. This will minimize the trace going to the embedded antenna wh ich in turn will minimize parasitic capacitance. If long trace is need ed between the TXO/LPI pin to the embedded antenna, keep the trace as a microstrip topology where the trace is on the top or bottom layer. Do not bury the trace on the inner layer. Relieve the ground fill along the trace which includes the ground fill on the inner layer. Note that the goal is to minimize the parasitic capacitance as much as possible, it is not necessary to design a 50 transmission lines in this applications because the embedded antenna is a high impedance ante nna, and the parallel resonant circuit is also high impedance at the resonant frequency. Put the optional ESD diode D1 and ESD current limiting resistor R1 as close to the embedded antenna as possible to ensure optimal ESD performance. 5.5. Embedded Antenna Design Checklist Place the chip as close as possible to the embedded antenna feedline to minimize parasitic capacitance. Select tuning inductor L1 with a Q>30 to maximize radiated power and received voltage. Select tuning inductor L1 as large as possible to maximize radiated power and incident voltage. Place the antenna, and in particular the end of the antenna opposite the Si47xx as far from the ground plane as possible to maximize radiated and received power. Place inductor L1 and the Si47xx chip as far from potential noise sources as possible to reduce capacitive and inductive coupling. Place optional components L2 to filter VCO spurs if needed. Place optional components D1 and R1 to achieve 8 kV contact discharge ESD protection if the antenna is exposed. Select ESD diode D1 with minimum capacitance.
used to isolate the cable return currents from the TXO/LPI pin. does not filter the high frequency. The required bill of materials for the Figure 21 is shown in Table 15. Table 15. Cable Antenna Bill of Materials F2 Series Ferrite bead, various types.
36 Rev. 0.8 6.4. Cable Antenna Layout Place the chip as close to the cable antenna as possible. This will minimize the trace length going to the cable antenna which will minimize the parasitic capacitance. Place the shunt ferrite for the ground return current as cl ose to the cable as possible . Putting the shunt ferrite for the ground return current cl ose to the cable ensures t hat the ground return curren t has minimal loop which will reduce noise coupling. The series ferrites also should be put as cl ose as possible to the cable. This will minimize the parasitic capacitance seen by the TXO/LPI pin. 6.5. Cable Antenna Design Checklist Place the chip as close as possible to the cable antenna to minimize parasitic capacitance. Place the tuning inductor, L1, as far away from the noise source as possible. Make sure that the shunt ferrite has a dc rating that exceeds the expected max ground return current of the cable. Place the shunt ferrite close to the cable. Choose series ferrite that is appropriate for each type of signal in the conductor. Place the series ferrite(s) close to the cable.
diode U3 as close as possible to the whip antenna input connector for maximum effectiveness. Maximize whip antenna length for optimal performance. Select matching inductor L1 with a Q of 15 or greater at 100MHz and minimal DC resistance. capacitive and inductive coupling. must be followed for optimal device performance. Place ESD U3 as close as possible to the whip antenna for maximum effectiveness. Select ESD diode U3 with minimum capacitance. Place the ac coupling capacitor, C5, as close to the FMI pin as possible. Table 16. FM/WB Whip Antenna Bill of Materials
Figure 25. AM Ferrite Loop Antenna Schematic C1 is the ac coupling cap going to the AMI pin and its value should be 0.47 µF. D1 is an optional ESD diode if there is an exposed pad going to the AMI pin. Table 18. Ferrite Loop Antenna Bill of Materials exposed pad going to the AMI pin.
Rev. 0.8 41 8.4. Ferrite Loop Antenna Layout Place the chip as close as possible to the ferrite loop ant enna feedline. This will minimize the trace going to the ferrite antenna which in turn will mini mize parasitic capacitance, and also will minimize the possibility of noise sources coupling to the trace. The placement of the AM antenna is critical, since AM is susceptible to noise sources causing interference in the AM band. Noise sources can come from clock signals, sw itching power supply, and digital activities (e.g., MCU). When the AM input is interfaced to a ferrite loop stick antenna, the placement of the ferrite loop stick antenna is critical to minimize inductive coupling. Place the ferrite loop stick antenna as far away from interference sources as possible. In particular, make sure th e ferrite loop stick antenn a is away from signals on the PCB and away from even the I/O signals of the Si473x. Do not route any signal under or near the ferrite loop stick. Route digital traces in between ground plane for best performance. If that is not possible, route digital traces on the opposite side of the chip. This will minimize capacitive coupling between the plane(s) and the antenna. To tune correctly, the total capacitance seen at the AMI input needs to be minimized and kept under a certain value. The total acceptable capacitance depends on the induct ance seen by the Si4730/31 at its AM input. The acceptable capacitance at the AM input can be calculated using the formula shown in Equation 2. Equation 2. Expected Total Capacitance at AMI Where: CTotal = Total capacitance at the AMI input Leffective = Effective inductance at the AMI input fmax = Highest frequency in AM band The total allowable capacitance, when interfacing a ferrite loop stick antenna, is the effective capacitance resulting from the AMI input pin, the capacitance from the PCB, and the capacitance from the ferrite loop stick antenna. The inductance seen at the AMI in this ca se is primarily the inductance of the ferrite loop stick antenna. The total allowable capacitance in the case of an air loop antenna is the effective capacitance resulting from the AMI input pin, the capacitance of the PCB, the capacitance of the transformer, and the capacitance of the air loop antenna. The inductance in this case should also take all the elem ents of the circuit into account. The input capacitance of the AMI input is 8 pF. The formula shown in Equation 2 gives a total capacitance of 29 pF when a 300 µH ferrite loop stick antenna is used for an AM band with 10 kHz spacing, where the highest frequency in the band is 1710 kHz. 8.5. Ferrite Loop Antenna Design Checklist Place the chip as close as possible to the ferrite loop antenna feedline to minimize parasitic capacitance and the possibility of noise coupling. Place the ferrite loop stick antenna away from any sources of interference and even away from the I/O signals of the Si473x. Please make sure that the AM antenna is as far away as possible from circuits that switch at a rate which falls in the AM band (520–1720 kHz). Place optional component D1 if the antenna is exposed. Select ESD diode D1 with minimum capacitance. Do Not Place any ground plane under the ferrite loop stick antenna if the ferrite loop stick antenna is mounted on the PCB. The recommended ground separation is 1/4 inch or the width of the ferrite. Route traces from the ferrite loop stick connectors to the AMI input via the ac coupling cap C1 such that the capacitance from the traces and the pads is minimized. CTotal 2fmax 2Leffective
Figure 27. AM Air Loop Antenna Schematic C1 is the ac coupling cap going to the AMI pin and its value should be 0.47 µF. D1 is a required ESD diode since the antenna is exposed.
PCB and away from even the I/O signals of the Si473x. Do not route any si gnals under or near the transformer. Use a shielded transformer if possible. Place the transformer away from any sources of interference and even away from the I/O signals of the Si473x. the traces and the pads is minimized. Select ESD diode D1 with minimum capacitance. Table 20. Air Loop Antenna Bill of Materials
- Whip Antenna for SW Receive on AMI (Si4734/35 Only)
analysis for the AM ferrite loop antenna is covered in Section 7. and approximately 22 pF at the center of the FM band. whip antenna, and rubber whip antenna. The following figure shows the rubber and the telescopic whip antenna. Figure 28. Telescopic Whip Antenna
ferrite loop antenna interface. Figure 29. Whip Antenna Schematic plus FM Circuit and AM Ferrite Antenna
48 Rev. 0.8 10.3. SW Whip Antenna Bill of Materials Designator Description Notes WIP_ANTENNA Whip Antenna L1 Low Pass Filter Inductor, 1008, SM, 4.7 µH, COILCRAFT, 1008CS-472GLB Q of 20 or greater at 25 MHz and minimal DC resistance. SW1 SPDT Switch Optional, only needed if the design requires switching between AM and SW. Not required for SW only applications. C3 Capacitor, 33 pF, 5%, COG C8 AC coupling capacitor, 0.47 µF, 10%, Z5U/X7R FERRITE_ANTENNA AM Antenna Optional, can be replaced with a 220 µH shunt inductor for SW only applications U2, U3 IC, SM, ESD DIODE, SOT23-3, California Micro Devices, CM1213-01ST C1 Capacitor, 18 pF, 5%, COG Optional, only for FM L2 Ind, 0603, SM, 180 nH, MURATA, LQW18ANR18J00D Optional, only for FM
Rev. 0.8 49 10.4. SW Whip Antenna Layout Place the chip as close as possible to the whip antenna. This will minimize the trace length between the device and whip antenna which in turn will minimize parasitic capacitance and the possibility of noise coupling. Place the whip antenna away from any sources of interference and away from the I/O signals of the Si4734/35. Place the ac coupling capacitor, C8, as close to the AMI pin as possible. Place the ac coupling capacitor, C1, as close as possible to the FMI pin. Place ESD diodes U2 and U3 as close as possible to the whip antenna input connector for maximum effectiveness. 10.5. SW Whip Antenna Design Checklist Maximize whip antenna length for optimal performance. Select matching inductor L1 with a Q of 20 or greater at 25 MHz and minimal dc resistance. Select L1 inductor value to maximize signal strength across the FM band. Place L1 and whip antenna close together and as far from potential noise sources as possible to reduce capacitive and inductive coupling. Place the chip as close as possible to the whip antenna to minimize the antenna trace length. This reduces parasitic capacitance and hence reduces coupling into the antenna by noise sources. This recommendation must be followed for optimal device performance. Place ESD diodes U2 and U3 as close as possible to the whip antenna for maximum effectiveness. Select ESD diodes U2 and U3 with minimum capacitance. Place the ac coupling capacitor, C8, as close to the AMI pin as possible. Follow the design checklist in "8. Ferrite Loop Antenna for AM/LW Receive on AMI (Si4730/31/34/35/36/37 Only)" on page 39 for the ferrite antenna to optimize AM performance (if AM is used in addition to SW).
is optimized by maximizing input voltage, not power. Figure 32. Headphone Antenna and Matching Network Model CSHUNT, and LNA capacitance, CLNA.
Figure 33. Parallel Resonant RLC Circuit Model will maximize voltage gain across the FM band for optimal RF performance. P should be maximized to maximize the voltage at the LNA input.
- The Q of the circuit should be minimized to maintain a flat response across the FM band.
- The value of L MATCH should be chosen such that the circuit resonates in the center of the FM band.
The antenna length should be 1.1 to 1.45 m, with optimal performance at 1.45 m to maximize RANT*.
52 Rev. 0.8 The Q of the circuit should be minimized to maintain a fl at response across the FM band. To minimize the Q of the circuit with a parallel resistance, R P, that is maximized, the parallel capacitance, C P, should be minimized and LMATCH should be maximized. The parallel capacitance, CP, shown in Figure 33, “Parallel Resonant RLC Circuit Model” is defined as follows: The PCB antenna trace capacitance, CPCBANT, is determined by the structure of the trace and is typically 3 to 4 pF per inch as a rule of thumb. The audio conductor shunt capacitance, C SHUNT, is the parallel addition of PCB trace and component capacitance with respect to ground on th e left and right audio conductors, and other conductors such as the microphone and switch if applicable. Both C PCBANT and C SHUNT should be as small as possible to minimize CP. Specific schematic and layout recommendations minimizing C SHUNT can be found in Section "3.2. Headphone Antenna Schematic" on page 19 and Section "3.4. Headphone Antenna Layout" on page 21. Specific layout recommendation for minimizing C PCBANT can be found in Section “3.4. Headphone Antenna Layout”. The LNA capacitance, C LNA, will range from 4 to 6 pF during normal operation. The ant enna capacitance, C ANT, will range from zero to several picofarads, depending on antenna length. C ANT* is the parallel circuit model of C ANT near the resonant frequency, f, of the RLC circuit, and is approximated as follows: For a given value of parallel capacitance C P, the inductor value L MATCH should be chosen such that the circuit resonates at the center of the FM band. The resonant frequency, f, of the parallel RLC circuit shown in Figure 33, “Parallel Resonant RLC Circuit Model” is defined as follows: Normally it is difficult to reliably measure all of the impedances required to calculate an optimal value for L MATCH. An easier approach is to measure the syste m performance with different values of L MATCH and choose the best values based on these measurements. Typical LMATCH values range from 100 to 400 nH. There are two test methods available for selecting the correct value of L MATCH to properly tune the headphone antenna interface circuit. Both methods require injecting a test signal from a signal generator into the network through a source resistance, R TEST, and adjusting the matching inductor, L MATCH, to maximize the voltage at the LNA input at several points across the FM band. R TEST should be 20 k or larger to prevent loading of the resonant antenna circuit. Figure 34, “Parallel Resonant RLC Circuit Model Test Circuit” shows the parallel resonant RLC model test circuit required for both test methods. CP CPCBANT CSHUNT CLNA CANT * = CANT *C ANT QANT QANT 2 1+ f 1 2 LMATCH CP
Figure 34. Parallel Resonant RLC Circuit Model Test Circuit using the RSSI tuning method.
Figure 35. Headphone Antenna Example Test Signal Injection Frequency Response can be difficult by inspection.
- The mean value of RSSI should be maximized.
- The standard deviation of RSSI should be minimized.
Table 21. Headphone Antenna Example Test Signal Injection Mean and Standard Deviation
of a typical application is shown in Figure 36. Figure 36. Typical Application the ground and power planes be maximized.
- Maximize antenna current.
- Maximize distance between the end of the antenna and the ground and power planes.
point that will be discussed later in this section. tuning inductor. In practice this is easily achieved and is only mentioned for completeness. inductance that should be expected. wavelength, the antenna reactance XANT is capacitive and is replaced with capacitance CANT. Figure 38. Simplified Model of the Electrically Short Monopole
58 Rev. 0.8 CBUFFER = Variable Tuning Capacitance (C TUNE) + Con chip parasitic RBUFFER = Variable Tuning Capacitor Series Resistance LTUNE = Tuning Inductance RTUNE = Tuning Inductor Series Resistance CPCB = PCB Parasitic Capacitance CANT = Antenna Capacitance RANT = Antenna Series Resistance XANT is 1.6 k for a 6 cm antenna at 100 MHz and is approximated as follows: where L =0 . 0 6 , f =1 0 0M H z , c=3x1 08 CANT is 1 pF at 100 MHz for XANT of 1.6 k and is given as follows: RANT is 0.31 for a 6 cm antenna at 100 MHz and is approximated as follows: , where L =0 . 0 6 , f =1 0 0M H z , c=3x1 08 QANT is approximately 5000 for a 6 cm antenna at 100 MHz and is approximated as follows: The series resistances RBUFFER, RTUNE and RANT can be transformed to a parallel resistance over a narrow range of frequencies with the following equation if the Q of each of the reactive elements C BUFFER, LTUNE, and CANT are known: The series inductance, L TUNE, can be transformed to a parallel inductance over a narrow range of frequencies if the Q of LTUNE is known with the following approximation: XANT 198c CANT 2fXANT RANT 20 2fL 2 Q XANT RANT RP RS Q2 1+=
Rev. 0.8 59 for Q >> 1 For sufficiently large Q, the inductive element is approximately the same for a series and parallel model. The series capacitances C BUFFER and CANT can be transformed to a parallel capacitance over a narrow range of frequencies if the Q of CBUFFER and CANT are known with the following approximation: for Q >> 1 LP LS Q2 1+ CP CS Q2 1+
For sufficiently large Q, the capacitive element is approximately the same for a series and parallel model. appreciably. The parallel model for each circuit element is indicated with an asterisk. Figure 39. Equivalent RLC Model of the Electrically Short Vertical Monopole CTUNE will range from 0.25 to 47.75 pF. Conchip parasitic is approximately 5 pF. CBUFFER will range from 5 to 53 pF. CPCB should be 4 pF or less to allow sufficient range for CBUFFER to tune across the FM band. CANT will be approximately 1 pF.
62 Rev. 0.8 The actual CTUNE needed then has to be well within the available range of CTUNE, which is: CTUNE min = 0.25 pF CTUNE max = 47.75 pF CTUNE can be read from the chip and the range will be 1–191. Each number represents 0.25 pF, so the range is 0.25 to 47.75 pF. Example 1 Conchip parasitic = 5 pF CPCB = 4 pF CANT = 1 pF Ctotal parasitic capacitance = 5 + 4 + 1 = 10 pF LTUNE = 120 nH Desired FM frequency = 76–108 MHz At 76 MHz > Ctotal = 37 pF, CTUNE = 37 – 10 = 27 pF At 108 MHz > Ctotal = 18 pF, CTUNE = 18 – 10 = 8 pF In this case at the FM frequency of interest (76 MHz to 108 MHz), the needed CTUNE range (8–27 pF) is within the available CTUNE range on the chip (0.25–47.75 pF) which means that the 120 nH inductor value is a good choice. Example 2 Conchip parasitic = 5 pF CPCB = 10 pF CANT = 1 pF Ctotal parasitic capacitance = 5 + 10 + 1 = 16 pF At 76 MHz > Ctotal = 37 pF, CTUNE = 37 – 16 = 21 pF At 108 MHz > Ctotal = 18 pF, CTUNE = 18 – 16 = 2 pF In this case at 108 MHz even though CTUNE needed (2 pF ) is still higher than the min CTUNE (0.25 pF), it is not advisable to keep LTUNE at 120 nH. Variation in the parasitic capacitance from the PCB and different components may result in the CTUNE needed to be equal or less than 0.25 pF. It is advisable then to lower the LTUNE value to 100 nH. Solution Make LTUNE = 100 nH At 76 MHz > Ctotal = 44 pF, CTUNE = 28 pF At 108 MHz > Ctotal = 22 pF, CTUNE = 6 pF In this case the needed CTUNE range (6–28 pF) is well within the available CTUNE (0.25 to 47.75 pF).
Rev. 0.8 63 APPENDIX C—AM F ERRITE LOOP STICK ANTENNA INTERFACE MODEL This appendix describes how to interface a ferrite loop stick antenna to the AM receiver input. The application note begins with an overview of AM ferrite loop antennas follo wed by the interface to a ferrite loop stick antenna. The last section of the application note presents designers with guidelines for designing ferrite loop stick antennas. AM Ferrite Loop Stick Antenna Overview An AM antenna works on the basis of Faraday's Law. Faraday 's law dictates that a varying magnetic field through a wire loop induces an EMF (Electro-Motive Force) in the loop and is expressed as: Where = magnetic flux. The negative sign in Equation indicates that the current generated in the loop is in a direction which generates a magnetic field that opposes the magnetic field causing t he induced EMF. An AM loop antenna is made of a single loop or many loops of a conducting material wrapped around an air core or a ferrite core. In the case of radio transmissions, the induced voltage represents the AM signal being transmitted by a radio station as electromagnetic waves. A ferrite loop stick antenna is a coil wrapped around a fe rrite core. Ferrite is a ferromagnetic material which does not display any magnetic properties till it is excited by a magnetic field. A ferrite multiplies the applied magnetic field by a factor that is known as the ef fective permeability of the ferrite materi al. Since the permeability of a ferrite material is orders of magnitude higher than air, the vo ltage induced in a loop antenna wound around a ferrite core is also orders of magnitude greater than the voltage that would be induced in an air loop antenna of the same size. All ferrite loop stick antennas have an inductance associated with them and this can be expressed as: Equation 3. Trap Frequency Calculation Where: Lant = Antenna inductance k = Permeability modifier constant µ r = Relative permeability of ferrite rod µo = Permeability of air/free space N = Number of turns in coil A = Cross-sectional area of ferrite rod l r = Length of ferrite rod In Equation 3, µ r is the relative permeability of the ferrite rod. The rod dimensions play an important role in determining the relative perme ability of the rod. The permeability modifier constant is based on the ratio of ferrite rod length to the coil length. The re lative permeability of t he rod and the permeability modifier constant are combined together to yiel d the effective permeability of the antenna and ar e used to reduce Equation 3 to the following: EMF d Lant kroN2A lr
64 Rev. 0.8 Equation 4. Ferrite Loop Inductance Calculation Where µe = Effective relative permeability of antenna Signal receiving capability of an antenna is defined by its antenna height. Antenna he ight of a lo op antenna is derived from Equation by replacing the flux with the inner product of the magnetic field and the surface area of the coil and is expressed as follows: Equation 5. Simplified Ferrite Loop Inductance Calculation Where: he = Effective antenna height N = Number of turns in coil A = Cross-sectional area of ferrite rod µ e = Relative effective permeability of antenna = Wavelength of signal Equation 6 is used to rewrite the antenna height in terms of antenna inductance as follows: Equation 6. Effective Antenna Height Calculation Where: f = Signal frequency L ant = Antenna inductance lr = Length of ferrite rod c = speed of light µ o = Permeability of air/free space N = Number of turns in coil Equation 6 tells us the relationship between antenna height and the factors that affect antenna height. The induced voltage can be calculated simply by multiplying the antenn a height with the electric fi eld strength for an AM signal (denoted by E) with dimensions of Volts/unit length. Equation 7 expresses this relationship: Equation 7. Induced Voltage Calculation L oeN2A Ir he 2NAe he 2fLant lr Vinduced E 2fLant lr
for the front-end of a loop antenna attached to the AM RX. Figure 41. AM Front-End with Ferrite Loop Antenna implemented as a bank of capacitors and as capacitors are switched in or out, the stray resistance also changes. to reduce gain is helpful if the received signal is too strong and does not need to be gained by the front-end circuit. front-end can be controlled by the De-Q resistor.
Rev. 0.8 67 DOCUMENT CHANGE LIST Revision 0.3 to Revision 0.4 Updated "2. Si47xx 3x3 mm QFN Schematic and Layout" on page 5 with latest recommendation on schematic, layout and design guidelines. Added "6. Cable Antenna for FM Transmit on TXO and Receive on LPI (Si4704/05/06/1x/2x Only)" on page 34. Added "7. Whip Antenna for FM/WB Receiver on FMI (Si4707/3x Only)" on page 37. Updated "8. Ferrite Loop Antenna for AM/LW Receive on AMI (Si4730/31/34/35/36/37 Only)" on page 39 with ferrite loop antenna pictures, recommendation and vendor information. Updated "9. Air Loop Antenna for AM/LW Receive on AMI (Si4730/31/34/35/36/37 Only)" on page 42 with air loop antenna pictures, transformer recommendation and vendor information. Added "10. Whip Antenna for SW Receive on AMI (Si4734/35 Only)" on page 45. Revision 0.4 to Revision 0.5 Updated "2. Si47xx 3x3 mm QFN Schematic and Layout" on page 5 with latest recommendation on schematic, layout and design guidelines. Added "4. Cable Antenna for FM Receive on FMI (Si470x/2x/3x/8x Only)" on page 22. Updated "5. Embedded Antenna for FM Transmit on TXO and Receive on LPI (Si4704/05/06/1x/2x Only)" on page 25. Added "6. Cable Antenna for FM Transmit on TXO and Receive on LPI (Si4704/05/06/1x/2x Only)" on page 34. Added "7. Whip Antenna for FM/WB Receiver on FMI (Si4707/3x Only)" on page 37. Updated "8. Ferrite Loop Antenna for AM/LW Receive on AMI (Si4730/31/34/35/36/37 Only)" on page 39 with vendor information. Updated "9. Air Loop Antenna for AM/LW Receive on AMI (Si4730/31/34/35/36/37 Only)" on page 42 with vendor information. Revision 0.5 to Revision 0.6 Added Note to “2.1. Si47xx 3x3 mm Design” and updated pin names and pin numbers on page 5. Revision 0.6 to Revision 0.8 Removed Note from Section “2.1. Si47xx 3x3 mm Design”.
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68 Rev. 0.8 NOTES: