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Rev. 1.0 9/14 Copyright © 2014 by Silicon Laboratories AN332 AN332 Si47 XX P ROGRAMMING G UIDE 1. Introduction This document provides an overview of the programming requirements for the Si47 04/05/06/07/1x/2x/3x/4x/84/85 FM transmitter/AM/FM/SW/LW/WB receiver. The hardware control interface and software commands are detailed along with several examples of the required steps to configure the device for various modes of operation. 2. Overview This family of products is progr ammed using commands and responses. To perform an action, the system controller writes a command byte and associated arguments, causing the devi ce to execute the given command. The device will, in tu rn, provide a response depending on the type of command that was sent. Section "4. Commands and Responses" on page 6 and section "5. Commands and Properties" on page 7 describe the procedures for using commands and responses and prov ide complete lists of commands, properties, and responses. The device has a slave control interface that allows the system controller to send commands to and receive responses from the device using one of three serial protocols (or bus modes): 2-wire mode (I 2C and SMBUS compatible), 3-wire mode, or SPI mode. Section "6. Control Interface" on page 206 describes the control interface in detail. Section "7. Powerup" on page 214 describes options for the sequencing of VDD and VIO power supplies, selection of the desired bus mode, provision of the reference clock, RCLK, and sending of the POWER_UP command. Section "8. Powerdown" on page 221 describes sendi ng the POWER_DOWN command and removing VDD and VIO power supplies as necessary. Section "9. Digital Audio Interface" on page 222 describ es the digital audio format supported and how to operate the device in digital mode. Section "10. Timing" on page 225 describes the CTS (Clear to Send) timing indicating when the command has been accepted and in most cases completed executi on, and the STC (Seek/Tune Complete) timing indicating when the Seek/Tune commands have completed execution. Section "11. FM Transmitter" on page 231 describes the audio dynamic range control, limiter, pre-emphasis, recommendations for maximizing audio volume for the FM transmitter. Section "12. Programming Examples" on page 235 pr ovides flowcharts and st ep-by-step procedures for programming the device.
Table 1. Product Family Function
- Si4706, Si4707, and Si474x are covered under NDA.
- High Performance RDS is available in Si4705/31/35/85-D50 and later.
Table 1. Product Family Function (Continued)
- Si4706, Si4707, and Si474x are covered under NDA.
- High Performance RDS is available in Si4705/31/35/85-D50 and later.
4 Rev. 1.0 TABLE OF C ONTENTS Section Page 5.2. Commands and Properties for the FM/RDS Receiver 5.3. Commands and Properties for the AM/SW/LW Receiver Appendix A—Comparison of the Si4704/05/3x-B20,
Rev. 1.0 5 3. Terminology SEN—Serial enable pin, active low; used as device sele ct in 3-wire and SPI operation and address selection in 2-wire operation. SDIO—Serial data in/data out pin. SCLK—Serial clock pin. RST or RSTb—Reset pin, active low RCLK—External reference clock GPO—General purpose output CTS—Clear to send STC—Seek/Tune Complete NVM—Non-volatile internal device memory Device—Refers to the FM Trans mitter/AM/FM/SW/LW/WB Receiver System Controller—Refers to the system microcontroller CMD—Command byte COMMANDn—Command register (16-bit) in 3-Wire mode (n = 1 to 4) ARGn—Argument byte (n = 1 to 7) STATUS—Status byte RESPn—Response byte (n = 1 to 15) RESPONSEn—Response regist er (16-bit) in 3-Wire mode (n = 1 to 8)
Commands control actions, such as power up, power down , or tune to a frequency, and are one byte in size. additional response bytes. A complete list of commands is available in “5. Commands and Properties”. that a command and three arguments be sent and returns one status byte. The table is broken into three columns. complete list of properties is available in Section “5. Commands and Properties”. SET_PROPERTY command and five argument bytes. AR G1 of the SET_PROPERTY command is always 0x00. are used to set the property value, PROPD (0x8000 or 32768 Hz in the example). Table 2. Using the TX_TUNE_FREQ Command STATUS 0x80 Reply Status. Clear-to-send high. Table 3. Using the SET_PROPERTY Command 0x80 Reply Status. Clear-to-send high.
The following four subsections list all the commands and properties used by each of the component. Table 4. FM/RDS Transmitter Command Summary file, see "7.2. Powerup from a Component Patch" on page 216.
Table 5. FM Transmitter Property Summary 34406 Hz, or 0 to disable the AFC. Default has pilot and L-R enabled. level. Units are in 10 Hz increments. 10 Hz increments. Default is 2 kHz.
- Digital Audio Input feature (property DIGITAL_INPUT_FORMAT and DIGITAL_INPUT_SAMPLE_RATE) is supported
in FMTX component 2.0 or later.
- RDS feature (command TX_RDS_BUFF, TX_RDS_PS and RDS properties 0x2103, 0x2C00 through 2C07) is
supported in FMTX component 2.0 or later.
- Limiter feature (LIMITEN bit in TX_ACOMP_ENABLE and property TX_LIMITER_RELEASE_TIME) is supported in
FMTX component 2.0 or later.
dynamic range control is disabled). 2 Configure RDS interrupt sources. Table 5. FM Transmitter Property Summary (Continued)
- Digital Audio Input feature (property DIGITAL_INPUT_FORMAT and DIGITAL_INPUT_SAMPLE_RATE) is supported
in FMTX component 2.0 or later.
- RDS feature (command TX_RDS_BUFF, TX_RDS_PS and RDS properties 0x2103, 0x2C00 through 2C07) is
supported in FMTX component 2.0 or later.
- Limiter feature (LIMITEN bit in TX_ACOMP_ENABLE and property TX_LIMITER_RELEASE_TIME) is supported in
FMTX component 2.0 or later.
mitting the next PS message.
- Digital Audio Input feature (property DIGITAL_INPUT_FORMAT and DIGITAL_INPUT_SAMPLE_RATE) is supported
in FMTX component 2.0 or later.
- RDS feature (command TX_RDS_BUFF, TX_RDS_PS and RDS properties 0x2103, 0x2C00 through 2C07) is
supported in FMTX component 2.0 or later.
- Limiter feature (LIMITEN bit in TX_ACOMP_ENABLE and property TX_LIMITER_RELEASE_TIME) is supported in
FMTX component 2.0 or later.
Table 6. Status Response 0 = Wait before sending next command. 1 = Clear to send next command. 5:3 Reserved Values may vary.
2 RDSINT
0 = RDS interrupt has not been triggered. 1 = RDS interrupt has been triggered. 0 = Signal quality measurement has not been triggered. 1 = Signal quality measurement has been triggered. Seek/Tune Complete Interrupt. 0 = Tune complete has not been triggered. 1 = Tune complete has been triggered.
12 Rev. 1.0 5.1.1. Commands and Properties for the FM/RDS Transmitter Command 0x01. POWER_UP Initiates the boot process to move the device from powerdown to powerup mode. The boot can occur from internal device memory or a system controller downloaded patch. To confirm that the patch is compatible with the internal device library revision, the library revision should be confirmed by issuing the POWER_UP command with Function = 15 (query library ID). The device will return the response, including the library revision, and then moves into powerdown mode. The device can then be placed in powerup mode by issuing the POWER_UP command with Function = 2 (transmit) and the patch may be applied. Only the STATUS byte will be returned in the response stream in transmit mode. The POWER_UP command configur es the state of DIN (pin 13 ), DFS (pin 14), and RIN (pin 15) and LIN (pin 16) for analog or digital audio modes and GPO2/INT (pin 18) for interrupt operation. The command configures GPO2/INT interrupts (GPO2OEN) an d CTS interrupts (CTSIEN). If both are enabled, GPO2/INT is driven high during normal operation and low for a minimum of 1 µs during the interrupt. The CTSIEN bit is duplicated in the GPO_IEN property. The command is complete when the CTS bit (and optional interrupt) is set. Note: To change function (e.g., FM TX to FM RX), issue th e POWER_DOWN command to st op the current function; then, issue POWER_UP to start the new function. Note: Delay at least 500 ms between powerup command and first tu ne command to wait for the oscillator to stabilize if XOSCEN is set and crystal is used as the RCLK. Available in: All Command Arguments: Two Response Bytes: None (FUNC = 2), Seven (FUNC = 15) Command B i t D 7D 6D 5 D 4 D 3 D 2D 1D 0 CMD 000 0 0 001 ARG1 CTSIEN GPO2OEN PATCH XOSCEN FUNC[3:0] ARG2 OPMODE[7:0] ARG Bit Name Function 1 7 CTSIEN CTS Interrupt Enable. 0 = CTS interrupt disabled. 1 = CTS interrupt enabled. 1 6 GPO2OEN GPO2 Output Enable. 0 = GPO2 output disabled, (Hi-Z). 1 = GPO2 output enabled.
15 P A T C H
Patch Enable. 0 = Boot normally 1 = Copy non-volatile memory to RAM, but do not boot. After CTS has been set, RAM may be patched
Rev. 1.0 13 Response (to FUNC = 2, TX) Response (to FUNC = 15, Query Library ID) 1 4 XOSCEN Crystal Oscillator Enable. 0 = Use external RCLK (crystal oscillator disabled). 1 = Use crystal oscillator (RCLK and GPO3/DCLK with external 32.768 kHz crys- tal and OPMODE=01010000). See Si47xx Data Sheet Application Schematic for external BOM details. 1 3:0 FUNC[3:0] Function. 0–1, 3–14 = Reserved. 2 = Transmit. 15 = Query Library ID. 2 7:0 OPMODE[7:0] Application Setting 01010000 = Analog audio inputs (LIN/RIN) 00001111 = Digital audio inputs (DIN/DFS/DCLK) B i t D 7D 6D 5 D 4 D 3 D 2 D 1 D 0 STATUS CTS ERR X X X RDSINT ASQINT STCINT B i t D 7 D 6 D 5D 4D 3 D 2 D 1 D 0 STATUS CTS ERR X X X RDSINT ASQINT STCINT RESP1 PN[7:0] RESP2 FWMAJOR[7:0] RESP3 FWMINOR[7:0] RESP4 RESERVED[7:0] RESP5 RESERVED[7:0] RESP6 CHIPREV[7:0] RESP7 LIBRARYID[7:0] RESP Bit Name Function 1 7:0 PN[7:0] Final 2 digits of part number. 2 7:0 FWMAJOR[7:0] Firmware Major Revision. 3 7:0 FWMINOR[7:0] Firmware Minor Revision. 4 7:0 RESERVED[7:0] Reserved, various values. 5 7:0 RESERVED[7:0] Reserved, various values. 6 7:0 CHIPREV[7:0] Chip Revision. 7 7:0 LIBRARYID[7:0] Library Revision. ARG Bit Name Function
14 Rev. 1.0 Command 0x10. GET_REV Returns the part number, chip revision, firmware revision , patch revision and component revision numbers. The command is complete when the CTS bit (and optional interrupt) is set. This command may only be sent when in powerup mode. Available in: All Command arguments: None Response bytes: Eight Command Response B i t D 7D 6D 5 D 4 D 3 D 2 D 1 D 0 CMD 000 1 0 0 0 0 B i t D 7D 6D 5D 4D 3D 2D 1D 0 STATUS CTS ERR X X X RDSINT ASQINT STCINT RESP1 PN[7:0] RESP2 FWMAJOR[7:0] RESP3 FWMINOR[7:0] RESP4 PATCH H[7:0] RESP5 PATCHL[7:0] RESP6 CMPMAJOR[7:0] RESP7 CMPMINOR[7:0] RESP8 CHIPREV[7:0] RESP Bit Name Function 1 7:0 PN[7:0] Final 2 digits of Part Number 2 7:0 FWMAJOR[7:0] Firmware Major Revision 3 7:0 FWMINOR[7:0] Firmware Minor Revision 4 7:0 PATCH H[7:0] Patch ID High Byte 5 7:0 PATCH L[7:0] Patch ID Low Byte 6 7:0 CMPMAJOR[7:0] Component Major Revision 7 7:0 CMPMINOR[7:0] Component Minor Revision 8 7:0 CHIPREV[7:0] Chip Revision
Rev. 1.0 15 Command 0x11. POWER_DOWN Moves the device from powerup to powerdo wn mode. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Note that only the POWER_UP command is accepted in powerdown mode. If the system controller writes a command other than POWER_UP when in powerdown mode, the device does not respond. The device will only respond when a POWER_UP command is written. GPO pins are powered down and not active during this state. For optimal power down current, GPO2 must be either internally driven low through GPIO_CTL command or externally driven low. Note: In FMTX component 1.0 and 2.0, a re set is required when the system contro ller writes a command other than POW- ER_UP when in powerdown mode. Note: The following describes the state of all the pins when in powerdown mode: GPIO1, GPIO2, and GPIO3 = 0 DIN, DFS, RIN, LIN = HiZ Available in: All Command arguments: None Response bytes: None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 000 1 0 0 0 1 B i t D 7D 6D 5 D 4 D 3 D 2 D 1 D 0 STATUS CTS ERR X X X RDSINT ASQINT STCINT
16 Rev. 1.0 Command 0x12. SET_PROPERTY Sets a property shown in Table 5, “FM Transmitter Property Summary,” on page 8. The CTS bit (and optional interrupt) is set when it is safe to send the next co mmand. This command may only be sent when in powerup mode. See Figure 29, “CTS and SET_PROPERTY Command Complete tCOMP Timing Model,” on page 226 and Table 45, “Command Timing Parameters for the FM Transmitter,” on page 227. Available in: All Command Arguments: Five Response bytes: None Command Response B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 00010010 ARG1 00000000 ARG2 PROP H[7:0] ARG3 PROPL[7:0] ARG4 PROPDH[7:0] ARG5 PROPDL[7:0] ARG Bit Name Function 1 7:0 Reserved Always write to 0. 2 7:0 PROP H[7:0] Property High Byte. This byte in combination with PROPL is used to specify the property to 3 7:0 PROP L[7:0] Property Low Byte. This byte in combination with PROPH is used to specify the property to 4 7:0 PROPD H[7:0] Property Value High Byte. This byte in combination with PROPVL is used to set the property value. See Section "5.1.2. FM/RDS Transmitter Properties" on page 31. 5 7:0 PROPD L[7:0] Property Value Low Byte. This byte in combination with PROPVH is used to set the property value. See Section "5.1.2. FM/RDS Transmitter Properties" on page 31. B i t D 7D 6D 5 D 4 D 3 D 2 D 1 D 0 STATUS CTS ERR X X X RDSINT ASQINT STCINT
Rev. 1.0 17 Command 0x13. GET_PROPERTY Gets a property shown in Table 5, “FM Transmitter Property Summary,” on page 8. The CTS bit (and optional interrupt) is set when it is safe to send the next co mmand. This command may only be sent when in powerup mode. Available in: All Command arguments: Three Response bytes: Three Command Response B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 00010011 ARG1 00000000 ARG2 PROP H[7:0] ARG3 PROPL[7:0] ARG Bit Name Function 1 7:0 Reserved Always write to 0. 27 : 0 P R O P H[7:0] Property Get High Byte. This byte in combination with PROPL is used to specify the property to get. 37 : 0 P R O P L[7:0] Property Get Low Byte. This byte in combination with PROPH is used to specify the property to get. B i tD 7D 6D 5D 4D 3D 2D 1D 0 STATUS CTS ERR X X X RDSINT ASQINT STCINT RESP1 XXXXXXXX RESP2 PROPDH[7:0] RESP3 PROPDL[7:0] RESP Bit Name Function 1 7:0 Reserved Reserved, various values. 27 : 0 P R O P D H[7:0] Property Value High Byte. This byte in combination with PROPVL will represent the requested prop- erty value. 37 : 0 P R O P D L[7:0] Property Value High Byte. This byte in combination with PROPVH will represent the requested prop- erty value.
18 Rev. 1.0 Command 0x14. GET_INT_STATUS Updates bits 6:0 of the status byte. This command shou ld be called after any command that sets the STCINT, ASQINT, or RDSINT bits. When polling this command should be periodically called to monitor the STATUS byte, and when using interrupts, this command should be called after the interrupt is set to update the STATUS byte. The command is complete when the CTS bit (and optional interrupt) is set. This command may only be sent when in powerup mode. Available in: All Command arguments: None Response bytes: None Command Response B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 00010100 B i tD 7D 6D 5D 4D 3D 2D 1D 0 STATUS CTS ERR X X X RDSINT ASQINT STCINT
Rev. 1.0 19 Command 0x30. TX_TUNE_FREQ Sets the state of the RF carrier and sets the tuning fr equency between 76 and 108 MHz in 10 kHz units and steps of 50 kHz. For example 76.05 MHz = 7605 is valid be cause it follows the 50 kHz step requirement but 76.01 MHz = 7601 is not valid. The CTS bit (and optional in terrupt) is set when it is safe to send the next command. The ERR bit (and optional interrupt) is set if an invalid argument is sent. Note that only a single interrupt occurs if both the CTS and ERR bits are set. The optional STC interrupt is set when the command completes. The STCINT bit is set only after the GET_INT_STATUS comman d is called. This command may only be sent when in powerup mode. The command clears the STC bit if it is al ready set. See Figure 28, “CTS and STC Timing Model,” on page 226 and Table 45, “Command Timing Parameters for the FM Transmitter,” on page 227. Available in: All Command arguments: Three Response bytes: None Command Response B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 00110000 ARG1 00000000 ARG2 FREQ H[7:0] ARG3 FREQL[7:0] ARG Bit Name Function 1 7:0 Reserved Always write to 0. 27 : 0 F R E Q H[7:0] Tune Frequency High Byte. This byte in combination with FREQL selects the tune frequency in units of 10 kHz. The valid range is from 7600 to 10800 (76–108 MHz). The frequency must be a multiple of 50 kHz. 37 : 0 F R E Q L[7:0] Tune Frequency Low Byte. This byte in combination with FREQH selects the tune frequency in units of 10 kHz. The valid range is from 7600 to 10800 (76–108 MHz). The frequency must be a multiple of 50 kHz. B i t D 7D 6D 5 D 4 D 3 D 2 D 1 D 0 STATUS CTS ERR X X X RDSINT ASQINT STCINT
20 Rev. 1.0 Command 0x31. TX_TUNE_POWER Sets the RF voltage level between 88 dBµV and 115 dBµV in 1 dB units. Power may be set as high as 120 dBµV; however, voltage accuracy is not guaranteed. A value of 0x00 indicates off. The command also sets the antenna tuning capacitance. A value of 0 indicates autotuning, and a value of 1–191 indicates a manual override. The CTS bit (and optional interrupt) is set when it is safe to se nd the next command. The ERR bit (and optional interrupt) is set if an invalid argument is sent. Note that only a single interrupt occurs if both the CTS and ERR bits are set. The optional STC interrupt is set when the command comp letes. The STCINT bit is set only after the GET_INT_STATUS command is called. This command may only be sent when in powerup mode. The command clears the STC bit if it is already set. See Figure 2 8, “CTS and STC Timing Model,” on page 226 and Table 45, “Command Timing Parameters for the FM Transmitter,” on page 227. Available in: All Command arguments: Four Response bytes: None Command Response B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 00110001 ARG1 00000000 ARG2 00000000 ARG3 RFdBµV[7:0] ARG4 ANTCAP[7:0] ARG Bit Name Function 1 7:0 Reserved Always write to 0. 2 7:0 Reserved Always write to 0. 3 7:0 RFdBµV[7:0] Tune Power Byte. Sets the tune power in dBµV in 1 dB steps. The valid range is from 88– 115 dBµV. Power may be set as high as 120 dBµV; however, voltage accu- racy is not guaranteed. 4 7:0 ANTCAP[7:0] Antenna Tuning Capacitor. This selects the value of the antenna tuning capacitor manually, or automati- cally if set to zero. The valid range is 0 to 191, which results in a tuning capacitance of 0.25 pF x ANTCAP . B i t D 7D 6D 5 D 4 D 3 D 2 D 1 D 0 STATUS CTS ERR X X X RDSINT ASQINT STCINT
Rev. 1.0 21 Command 0x32. TX_TUNE_MEASURE Enters receive mode (disables transmitter output power) and measures the received noise level (RNL) in units of dBµV on the selected frequency. The command sets the tuning frequency between 76 and 108 MHz in 10 kHz units and steps of 50 kHz. For example 76.05 MHz = 7605 is valid because it follows the 50 kHz step requirement but 76.01 MHz = 7601 is not valid. The command also sets th e antenna tuning capacitance. A value of 0 indicates autotuning, and a value of 1–191 indicates a manual override. The CTS bit (and optional interrupt) is set when it is safe to send the next command. The ERR bit (and optional interrupt) is set if an invalid argument is sent. Note that only a single interrupt occurs if both the CTS and ERR bi ts are set. The optional STC interrupt is set when the command completes. The STCINT bit is set only after the GET_INT_STATUS command is called. This command may only be sent when in powerup mode. The command clears the STC bit if it is already set. See Figure 28, “CTS and STC Timing Model,” on page 226 and Table 45, “Com mand Timing Parameters for the FM Transmitter,” on page 227. Available in: Si4712/13/20/21 Command arguments: Four Response bytes: None Command Response B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 00110010 ARG1 00000000 ARG2 FREQ H[7:0] ARG3 FREQL[7:0] ARG4 ANTCAP[7:0] ARG Bit Name Function 1 7:0 Reserved Always write to 0. 27 : 0 F R E Q H[7:0] Tune Frequency High Byte. This byte in combination with FREQL selects the tune frequency in units of 10 kHz. In FM mode the valid range is from 7600 to 10800 (76–108 MHz). The frequency must be a multiple of 50 kHz. 37 : 0 F R E Q L[7:0] Tune Frequency Low Byte. This byte in combination with FREQH selects the tune frequency in units of 10 kHz. In FM mode the valid range is from 7600 to 10800 (76–108 MHz). The frequency must be a multiple of 50 kHz. 4 7:0 ANTCAP[7:0] Antenna Tuning Capacitor. This selects the value of the antenna tuning capacitor manually, or auto- matic if set to zero. The valid range is 0–191. B i t D 7D 6D 5 D 4 D 3 D 2 D 1 D 0 STATUS CTS ERR X X X RDSINT ASQINT STCINT
22 Rev. 1.0 Command 0x33. TX_TUNE_STATUS Returns the status of the TX_TUNE_FREQ, TX_T UNE_MEASURE, or TX_TUNE_POWER commands. The command returns the current frequency, output voltage in dBµV (if applicable), the antenna tuning capacitance value (0–191) and the received noise level (if applicable). The command clears the STCINT interrupt bit when INTACK bit of ARG1 is set. The CTS bit (and optional interrup t) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Available in: All Command arguments: One Response bytes: Seven Command Response B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 00110011 ARG1 0000000 I N T A C K ARG Bit Name Function 1 7:1 Reserved Always write to 0. 10 I N T A C K Seek/Tune Interrupt Clear. If set this bit clears the seek/tune complete interrupt status indicator. B i tD 7D 6D 5D 4D 3D 2D 1D 0 STATUS CTS ERR X X X RDSINT ASQINT STCINT RESP1 XXXXXXXX RESP2 READFREQ H[7:0] RESP3 READFREQL[7:0] RESP4 XXXXXXXX RESP5 READRFdBµV[7:0] RESP6 READANTCAP[7:0] RESP7 RNL[7:0]
Rev. 1.0 23 RESP Bit Name Function 1 7:0 Reserved Returns various data. 2 7:0 READFREQ H[7:0] Read Frequency High Byte. This byte in combination with READFREQL returns frequency being tuned. 37 : 0 R E A D F R E Q L[7:0] Read Frequency Low Byte. This byte in combination with READFREQH returns frequency being tuned. 4 7:0 Reserved Returns various data. 5 7:0 READRFdBµV[7:0] Read Power. Returns the transmit output voltage setting. 6 7:0 READANTCAP [7:0] Read Antenna Tuning Capacitor. This byte will contain the current antenna tuning capacitor value. 7 7:0 RNL[7:0] Read Received Noise Level (Si4712/13 Only). This byte will contain the receive level as the response to a TX Tune Mea- sure command. The returned value will be the last RNL measurement (or 0 if no measurement has been performed) for the TX Tune Freq and TX Tune Power commands.
24 Rev. 1.0 Command 0x34. TX_ASQ_STATUS Returns status information about the audio signal quality and current FM transmit frequency. This command can be used to check if the input audio stream is below a low threshold as reported by the IALL bit, or above a high threshold as reported by the IALH bit. The thresholds can be configured to detect a silence condition or an activity condition which can then be used by the host to take an appropriate action such as turning off the carrier in the case of prolonged silence. The thresholds are set using the TX_ ASQ_LEVEL_LOW and TX_ASQ_LEVEL_HIGH properties. The audio must be above or below the threshol d for greater than the amount of time specified in the TX_ASQ_DURATION_LOW and TX_ASQ_DURATION_HIGH properties for the status to be detected. Additionally the command can be used to determine if an overmodulation condition has occurred or the limiter has engaged, as reported by the OVERMOD bit, in whic h case the host could reduce the audio level to the part. If any of the OVERMOD, IALH, or IALL bits are set, the ASQINT bit will also be set. The ASQINT bit can be routed to a hardware interrupt via the GPO_IEN property. Clearing the IALH or IALL interrupts will result in the TX_ASQ _DURATION_LOW or TX_ASQ_DURATION_HIGH counters being rearmed, respectively, to start another detection interval measurement. The command clears the ASQINT interrupt bit and OVERMOD, IALH, and IALL bits when the INTACK bit of ARG1 is set. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Note that the TX_ASQ_DURATI ON_LOW and TX_ASQ_DURATION_HIGH counters start and the TX_ASQ_STATUS command will only retu rn valid data after a call to TX_TUNE_FREQ, TX_TUNE_POWER, or TX_TUNE_MEASURE. Available in: All Command arguments: One Response bytes: Four Command B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 00110100 ARG1 0000000 I N T A C K ARG Bit Name Function
10 I N T A C K
Interrupt Acknowledge. 0 = Interrupt status preserved. 1 = Clears ASQINT, OVERMOD, IALDH, and IALDL.
Rev. 1.0 25 Response B i t D 7D 6D 5D 4D 3 D 2 D 1D 0 STATUS CTS ERR X X X RDSINT ASQINT STCINT RESP1 X X X X X OVERMOD IALH IALL RESP2 XXXXX X XX RESP3 XXXXX X XX RESP4 INLEVEL[7:0] RESP Bit Name Function 1 2 OVERMOD Overmodulation Detection. 0 = Output signal is below requested modulation level. 1 = Output signal is above requested modulation level.
11 I A L H
Input Audio Level Threshold Detect High. 0 = Input audio level high threshold not exceeded. 1 = Input audio level high threshold exceeded.
10 I A L L
Input Audio Level Threshold Detect Low. 0 = Input audio level low threshold not exceeded. 1 = Input audio level low threshold exceeded. 27 : 0 R e s e r v e d Returns various values. 37 : 0 R e s e r v e d Returns various values. 4 7:0 INLEVEL[7:0] Input Audio Level. The current audio input level measured in dBfs (2s complement nota- tion).
26 Rev. 1.0 Command 0x35. TX_RDS_BUFF Loads or clears the RDS group buffer FIFO or circular buffer and returns the FIFO status. The buffer can be allocated between the circular buffer and FIFO with the TX_RDS_FIFO_SIZE property. A common use case for the circular buffer is to broadcast group 2A radio text, a nd a common use case for the FIFO is to broadcast group 4A real time clock. The command clears the INTACK interrupt bit when the INTACK bit of ARG1 is set. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Note: TX_RDS_BUFF is supported in FMTX component 2.0 or later. Available in: Si4711/13/21 Command arguments: Seven Response bytes: Five Command B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 00110101 ARG1 FIFO 0 0 0 0 LDBUFF MTBUFF INTACK ARG2 RDSB H[7:0] ARG3 RDSBL[7:0] ARG4 RDSCH[7:0] ARG5 RDSCL[7:0] ARG6 RDSDH[7:0] ARG7 RDSDL[7:0] ARG Bit Name Function 1 7 FIFO Operate on FIFO. If set, the command operates on the FIFO buffer. If cleared, the command operates on the circular buffer. 1 6:3 Reserved Always write to 0.
12 L D B U F F
Load RDS Group Buffer. If set, loads the RDS group buffer with RDSB, RDSC, and RDSD. Block A data is generated from the RDS_TX_PI property when the buffer is transmit- ted. 11 M T B U F F Empty RDS Group Buffer. If set, empties the RDS group buffer. 10 I N T A C K Clear RDS Group buffer interrupt. If set this bit clears the RDS group buffer interrupt indicator. 27 : 0 R D S B H[7:0] RDS Block B High Byte. This byte in combination with RDSBL sets the RDS block B data.
Rev. 1.0 27 Response 37 : 0 R D S B L[7:0] RDS Block B Low Byte. This byte in combination with RDSBH sets the RDS block B data. 4 7:0 RDSC H[7:0] RDS Block C High Byte. This byte in combination with RDSCL sets the RDS block C data. 5 7:0 RDSC L[7:0] RDS Block C Low Byte. This byte in combination with RDSCH sets the RDS block C data. 6 7:0 RDSD H[7:0] RDS Block D High Byte. This byte in combination with RDSDL sets the RDS block D data. 7 7:0 RDSD L[7:0] RDS Block D Low Byte. This byte in combination with RDSDH sets the RDS block D data. Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X X RDSINT ASQINT STCINT RESP1 X X X RDSPSXMIT CBUFXMIT FIFOXMIT CBUFWRAP FIFOMT RESP2 CBAVAIL[7:0] RESP3 CBUSED[7:0] RESP4 FIFOAVAIL[7:0] RESP5 FIFOUSED[7:0] RESP Bit Name Function 1 7:5 Reserved Values may vary. 1 4 RDSPSXMIT Interrupt source: RDS PS Group has been transmitted. 1 3 CBUFXMIT Interrupt source: RDS Group has been transmitted from the FIFO buffer. 1 2 FIFOXMIT Interrupt source: RDS Group has been transmitted from the circular buffer. 1 1 CBUFWRAP Interrupt source: RDS Group Circular Buffer has wrapped. 1 0 FIFOMT Interrupt source: RDS Group FIFO Buffer is empty. 2 7:0 CBAVAIL[7:0] Returns the number of available Circular Buffer blocks. 3 7:0 CBUSED[7:0] Returns the number of used Circular Buffer blocks. 4 7:0 FIFOAVAIL[7:0] Returns the numb er of available FIFO blocks. 5 7:0 FIFOUSED[7:0] Returns the number of used FIFO blocks. ARG Bit Name Function
28 Rev. 1.0 Command 0x36. TX_RDS_PS Loads or clears the program service buffer. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Note: TX_RDS_PS is supported in FMTX component 2.0 or later. Available in: Si4711/13/21 Command arguments: Five Response bytes: None Command Response B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 00110110 ARG1 0 0 0 PSID[4:0] ARG2 PSCHAR0 [7:0] ARG3 PSCHAR1 [7:0] ARG4 PSCHAR2 [7:0] ARG5 PSCHAR3 [7:0] ARG Bit Name Function 1 7:5 Reserved Always write to 0. 1 4:0 PSID[4:0] Selects which PS data to load (0–23) 0 = First 4 characters of PS0. 1 = Last 4 characters of PS0. 2 = First 4 characters of PS1. 3 = Last 4 characters of PS1. 22 = First 4 characters of PS11. 23 = Last 4 characters of PS11. 2 7:0 PSCHAR0[7:0] RDS PSID CHAR0. First character of selected PSID. 3 7:0 PSCHAR1[7:0] RDS PSID CHAR1. Second character of selected PSID. 4 7:0 PSCHAR2[7:0] RDS PSID CHAR2. Third character of selected PSID. 5 7:0 PSCHAR3[7:0] RDS PSID CHAR3. Fourth character of selected PSID. B i t D 7D 6D 5 D 4 D 3 D 2 D 1 D 0 STATUS CTS ERR X X X RDSINT ASQINT STCINT
Rev. 1.0 29 Command 0x80. GPIO_CTL Enables output for GPO1, 2, and 3. GPO1, 2, and 3 can be configured for output (Hi-Z or active drive) by setting the GPO1OEN, GPO2OEN, and GPO3OEN bit. The state (high or low) of GPO1, 2, and 3 is set with the GPIO_SET command. To avoid excessive current consumption due to oscillation, GPO pins should not be left in a high impedance state. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. The default is all GPO pins set for high impedance. Notes: 2. The use of GPO2 as an interrupt pin and/or the use of GPO3 as DCLK digital clock input will override this GPIO_CTL function for GPO2 and/or GPO3 respectively. Available in: All except Si4710-A10 Command arguments: One Response bytes: None Command Response B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 10000000 ARG1 0 0 0 0 GPO3OEN GPO2OEN GPO1OEN 0 ARG Bit Name Function 1 7:4 Reserved Always write 0. 1 3 GPO3OEN GPO3 Output Enable. 0 = Output Disabled (Hi-Z) (default). 1 = Output Enabled. 1 2 GPO2OEN GPO2 Output Enable. 0 = Output Disabled (Hi-Z) (default). 1 = Output Enabled. 1 1 GPO1OEN GPO1 Output Enable. 0 = Output Disabled (Hi-Z) (default). 1 = Output Enabled. 1 0 Reserved Always write 0. B i t D 7D 6D 5 D 4 D 3 D 2 D 1 D 0 STATUS CTS ERR X X X RDSINT ASQINT STCINT
30 Rev. 1.0 Command 0x81. GPIO_SET Sets the output level (high or low) for GPO1, 2, and 3. GPO1, 2, and 3 can be configured for output by setting the GPO1OEN, GPO2OEN, and GPO3OEN bit in the GPIO_CT L command. To avoid excessive current consumption due to oscillation, GPO pins should not be left in a high impedance state. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is all GPO pins set for high impedance. Note: GPIO_SET is fully-supported in FMTX comp 3.0 or later. Only bit GPO3LEVEL is supported in FMTX comp 2.0. Available in: All except Si4710-A10 Command arguments: One Response bytes: None Command Response B i t D 7 D 6D 5D 4 D 3 D 2 D 1 D 0 CMD 1 0 0 0 000 1 ARG1 0 0 0 0 GPO3LEVEL GPO2LEVEL GPO1LEVEL 0 ARG Bit Name Function 1 7:4 Reserved Always write 0. 1 3 GPO3LEVEL GPO3 Output Level. 0 = Output low (default). 1 = Output high. 1 2 GPO2LEVEL GPO3 Output Level. 0 = Output low (default). 1 = Output high. 1 1 GPO1LEVEL GPO3 Output Level. 0 = Output low (default). 1 = Output high. 1 0 Reserved Always write 0. B i t D 7D 6D 5 D 4 D 3 D 2 D 1 D 0 STATUS CTS ERR X X X RDSINT ASQINT STCINT
Rev. 1.0 31 5.1.2. FM/RDS Transmitter Properties Property 0x0001. GPO_IEN Configures the sources for the GPO2/INT interrupt pin. Valid sources are the lower 8 bits of the STATUS byte, including CTS, ERR, RDSINT, ASQINT, and STCINT bits. The corresponding bit is set before the interrupt occurs. The CTS bit (and optional interrupt) is set when it is safe to send the next command. The CTS interrupt enable (CTSIEN) can be set with this property and the POWER_UP command. The state of the CTSIEN bit set during the POWER_UP command can be read by reading the this pr operty and modified by writing this property. This property may only be set or read when in powerup mode. The default is no interrupts enabled. Available in: All Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 00000 RDSREP ASQREP STCREP CTSIEN ERRIEN 000 RDSIEN ASQIEN STCIEN Bit Name Function 15:11 Reserved Always write to 0.
10 RDSREP
RDS Interrupt Repeat. (Si4711/13/21 Only) 0 = No interrupt generated when RDSINT is already set (default). 1 = Interrupt generated even if RDSINT is already set. 9A S Q R E P ASQ Interrupt Repeat. 0 = No interrupt generated when ASQREP is already set (default). 1 = Interrupt generated even if ASQREP is already set.
8 STCREP
STC Interrupt Repeat. 0 = No interrupt generated when STCREP is already set (default). 1 = Interrupt generated even if STCREP is already set. 7C T S I E N CTS Interrupt Enable. 0 = No interrupt generated when CTS is set (default). 1 = Interrupt generated when CTS is set. After PowerUp, this bit will reflect the CTSIEN bit in ARG1 of PowerUp Command.
6 ERRIEN
ERR Interrupt Enable. 0 = No interrupt generated when ERR is set (default). 1 = Interrupt generated when ERR is set. 5:3 Reserved Always write to 0.
2 RDSIEN
RDS Interrupt Enable (Si4711/13/21 Only). 0 = No interrupt generated when RDSINT is set (default). 1 = Interrupt generated when RDSINT is set.
1 ASQIEN
Audio Signal Quality Interrupt Enable. 0 = No interrupt generated when ASQINT is set (default). 1 = Interrupt generated when ASQINT is set. 0S T C I E N Seek/Tune Complete Interrupt Enable. 0 = No interrupt generated when STCINT is set (default). 1 = Interrupt generated when STCINT is set.
32 Rev. 1.0 Property 0x0101. DIGITAL_INPUT_FORMAT Configures the digital input format. The CTS bit (and optio nal interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. Note: DIGITAL_INPUT_FORMAT is supported in FMTX component 2.0 or later. Available in: All except Si4710-A10 Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 000000 0 0 I F A L L I M O D E [ 3 : 0 ] I M O N O I S I Z E [ 1 : 0 ] Bit Name Function 15:8 Reserved Always write to 0. 7I F A L L DCLK Falling Edge. 0 = Sample on DCLK rising edge (default). 1 = Sample on DCLK falling edge. 6:3 IMODE[3:0] Digital Mode. 0000 = default 0001 = I2S Mode. 0111 = Left-justified mode. 1101 = MSB at 1st DCLK rising edge after DFS Pulse. 1001 = MSB at 2nd DCLK rising edge after DFS Pulse. 2I M O N O Mono Audio Mode. 0 = Stereo audio mode (default). 1 = Mono audio mode. 1:0 ISIZE[1:0] Digital Audio Sample Precision. 00 = 16 bits (default) 01 = 20 bits 10 = 24 bits 11 = 8 bits
Rev. 1.0 33 Property 0x0103. DIGITAL_INPUT_SAMPLE_RATE Configures the digital input sample rate in 1 Hz units. The input sample rate must be set to 0 before removing the DCLK input or reducing the DCL K frequency below 2 MHz. If this guidelin e is not followed, a device reset will be required. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. TX_TUN E_FREQ command must be sent after the POWER_UP command to start the internal clocking before setting this property. Note: DIGITAL_INPUT_SAMPLE_RATE is supported in FMTX component 2.0 or later. Available in: All except Si4710-A10 Default: 0x0000 Units: 1 Hz Step: 1 Hz Range: 0, 32000-48000 B i tD 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name DISR[15:0] Bit Name Function 15:0 DISR Digital Input Sample Rate. 0 = Disabled. Required before removing DCLK or reducing DCLK frequency below 2 MHz. The range is 32000–48000 Hz.
10, or frequencies up to 311300 Hz. Table 7 summarizes these RCLK gaps. Figure 1. REFCLK Prescaler mode. The default is 32768 Hz. Table 7. RCLK Gaps
40 MHz
Rev. 1.0 35 Property 0x0202. REFCLK_PRESCALE Sets the number used by the prescaler to divide the external RCLK down to the internal REFCLK. The range may be between 1 and 4095 in 1 unit steps. For example, an RCLK of 13 MHz would require a prescaler value of 400 to divide it to 32500 Hz. The reference clock frequency property would then need to be set to 32500 Hz. The RCLK must be valid 10 ns before and 10 ns after sending the TX_TUNE_MEASURE, TX_TUNE_FREQ, or TX_TUNE_POWER commands. In addition, the RCLK must be valid at all times when the carrier is enabled for proper AFC operation. The RCLK may be removed or reco nfigured at other times. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 1. Available in: All Default: 0x0001 Step: 1 Range: 1–4095 B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name REFCLKF[15:0] Bit Name Function 15:0 REFCLKF[15:0] Frequency of Reference Clock in Hz. The allowed REFCLK frequency range is between 31130 and 34406 Hz (32768 ±5%), or 0 (to disable AFC). B i tD 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 000 RCLK SEL RCLKP[11:0] Bit Name Function 15:13 Reserved Always write to 0.
12 RCLKSEL
RCLKSEL. 0 = RCLK pin is clock source. 1 = DCLK pin is clock source. 11:0 REFCLKP[11:0] Prescaler for Reference Clock. Integer number used to divide the RCLK frequency down to REFCLK frequency. The allowed REFCLK frequency range is between 31130 and 34406 Hz (32768 ±5%), or 0 (to disable AFC).
36 Rev. 1.0 Property 0x2100. TX_COMPONENT_ENABLE Individually enables the stereo pilot, left minus right stereo and RDS components. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is stereo pilot and left minus right stereo components enabled. Available in: All Default: 0x0003 Property 0x2101. TX_AUDIO_DEVIATION Sets the transmit audio deviation from 0 to 90 kHz in 10 Hz units. The sum of the audio deviation, pilot deviation and RDS deviation should not exceed regulatory requ irements, typically 75 kHz. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 6825, or 68.25 kHz. Available in: All Default: 0x1AA9 (6825) Units: 10 Hz Step: 10 Hz Range: 0–9000 B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1 D 0 Name 0000000000000 R D S L M R P I L O T Bit Name Function 15:3 Reserved Always write 0. 2R D S RDS Enable (Si4711/13/21 Only). 0 = Disables RDS (default). 1 = Enables RDS to be transmitted. 1L M R Left Minus Right. 0 = Disables Left Minus Right. 1 = Enables Left minus Right (Stereo) to be transmitted (default). 0P I L O T Pilot Tone. 0 = Disables Pilot. 1 = Enables the Pilot tone to be transmitted (default). B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name TXADEV[15:0] Bit Name Function 15:0 TXADEV[15:0] Transmit Audio Frequency Deviation. Audio frequency deviation is programmable from 0 Hz to 90 kHz in 10 Hz units. Default is 6825 (68.25 kHz). Note that the total deviation of the audio, pilot, and RDS must be less than 75 kHz to meet regulatory requirements.
Rev. 1.0 37 Property 0x2102. TX_PILOT_DEVIATION Sets the transmit pilot deviation from 0 to 90 kHz in 10 Hz units. The sum of the audio deviation, pilot deviation and RDS deviation should not exceed regulatory requirements, typically 75 kHz. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This prope rty may only be set or read when in powerup mode. The default is 675, or 6.75 kHz. Available in: All Default: 0x02A3 (675) Units: 10 Hz Step: 10 Hz Range: 0–9000 Property 0x2103. TX_RDS_DEVIATION Sets the RDS deviation from 0 to 7.5 kHz in 10 Hz units . The sum of the audio deviation, pilot deviation and RDS deviation should not exceed regulatory requirements, typically 75 kHz. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This prop erty may only be set or read when in powerup mode. The default is 200, or 2 kHz. Available in: Si4711/13/21 Default: 0x00C8 (200) Units: 10 Hz Step: 10 Hz Range: 0–9000 B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name TXPDEV[15:0] Bit Name Function 15:0 TXPDEV[15:0] Transmit Pilot Frequency Deviation. Pilot tone frequency deviation is programmable from 0 Hz to 90 kHz in 10 Hz units. Default is 675 (6.75 kHz). Note that the total deviation of the audio, pilot, and RDS must be less than 75 kHz to meet regulatory requirements. B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name TXRDEV[15:0] Bit Name Function 15:0 TXRDEV[15:0] Transmit RDS Frequency Deviation. RDS frequency deviation is programmable from 0 Hz to 90 kHz in 10 Hz units. Default is 200 (2 kHz). Note that the total deviation of the audio, pilot, and RDS must be less than 75 kHz to meet regulatory requirements.
38 Rev. 1.0 Property 0x2104. TX_LINE_INPUT_LEVEL Sets the input resistance and maximum audio input level for the LIN/RIN pins. An application providing a 150 mVPK input to the device on RIN/LIN would set Line Attenuati on = 00, resulting in a maximu m permissible input level of 190 mVPK on LIN/RIN and an input resistance of 396 k. The Line Level would be set to 150 mV to correspond to the TX audio deviation level set by the TX_AUDIO_DEVIATION property. An application providing a 1 VPK input to the device on RIN/LIN would set Line Attenuation = 11, resulting in a maximum permissible input level of 636 mVPK on LIN/RIN and an input resistance of 60 k . An external series resistor on LIN and RIN inputs of 40 k would create a resistive voltage divider that would keep the maximum line level on RIN/LIN below 636 mV PK. The Line Level would be set to 636 mVPK to correspond to the TX audio deviati on level set by the TX_AUDIO_DEVIATION property. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default input level and peak line level is 636 mV PK with an input impedance of 60 k. Available in: All Default: 0x327C B i t D 1 5 D 1 4 D 1 3D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 0 0 LIATTEN[1:0] 0 0 LILEVEL[9:0] Bit Name Function 15:14 Reserved Always write to 0. 13:12 LIATTEN[1:0] Line Attenuation. 00 = Max input level = 190 mVPK; input resistance = 396 k 01 = Max input level = 301 mVPK; input resistance = 100 k 10 = Max input level = 416 mVPK; input resistance = 74 k 11 = Max input level = 636 mVPK; input resistance = 60 k(default) 11:10 Reserved Always write to 0. 9:0 LILEVEL[9:0] Line Level. Maximum line amplitude level on the LIN/RIN pins in mVPK. The default is 0x27C or 636 mVPK.
Rev. 1.0 39 Property 0x2105. TX_LINE_INPUT_MUTE Selectively mutes the left and right audio inputs. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. Available in: All Default: 0x0000 Property 0x2106. TX_PREEMPHASIS Sets the transmit pre-emphasis to 50 µs, 75 µs or off. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 75 µs. Available in: All Default: 0x0000 B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2 D 1 D 0 Name 0 0 0 0 0 0 00000000 L I M U T E R I M U T E Bit Name Function 15:2 Reserved Always write to 0. 1L I M U T E Mutes L Line Input. 0 = No mute (default) 1=M u t e 0R I M U T E Mutes R Line Input. 0 = No mute (default) 1=M u t e B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 00000000000000 F M P E [ 1 : 0 ] Bit Name Function 15:2 Reserved Always write to 0. 1:0 FMPE[1:0] FM Pre-Emphasis. 00 = 75 µs. Used in USA (default) 01 = 50 µs. Used in Europe, Australia, Japan 10 = Disabled 11 = Reserved
40 Rev. 1.0 Property 0x2107. TX_PILOT_FREQUENCY This property is used to se t the frequency of the stereo pilot in 1 Hz st eps. The stereo pilot is nominally set to 19 kHz for stereo operation, however the pilot can be se t to any frequency from 0 Hz to 19 kHz to support the generation of an audible test tone. The pilot tone is enabled by setting the PILOT bit (D0) of the TX_COMPONENT_ENABLE property. When using the stereo pilot as an audible test generator it is recommended that the RDS bit (D2) be disabled. The CTS bit (and optio nal interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. Available in: All Default: 0x4A38 (19000) Units: 1 Hz Step: 1 Hz Range: 0–19000 Property 0x2200. TX_ACOMP_ENABLE Selectively enables the audio dynamic range control and limiter. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may on ly be set or read when in powerup mode. The default is limiter enabled and audio dynamic range control disabled. Note: LIMITEN bit is supported in FMTX component 2.0 or later. Reset this bit to 0 in FMTX component 1.0. Available in: All Default: 0x0002 B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name FREQ[15:0] Bit Name Function 15:0 FREQ Stereo Pilot Frequency Sets the frequency of the stereo pilot in 1 Hz steps. Range 0 Hz–19000 Hz (default is 0x4A38 or 19 kHz). Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0000000 0 0 0 0 0 0 0 L I M I T E N A C E N Bit Name Function 15:2 Reserved Always write to 0.
1 LIMITEN
Audio Limiter. 0=D i s a b l e 1 = Enable (default) 0A C E N Transmit Audio Dynamic Range Control Enable. 0 = Audio dynamic range control disabled (default) 1 = Audio dynamic range control enabled
Rev. 1.0 41 Property 0x2201. TX_ACOMP_THRESHOLD Sets the threshold for audio dynamic range control from 0 dBFS to –40 dBFS in 1 dB units in 2's complement notation. For example, a setting of –40 dB would be 65536 – 40 = 65496 = 0xFFD8. The threshold is the level below which the device applies the gain set by the TX_ACOMP_GAIN property, and above which the device applies the compression defined by (gain + threshold) / threshold. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0xFFD8, or –40 dBFS. Available in: All Default: 0xFFD8 (–40) Units: 1 dB Step: 1 dB Range: –40 to 0 B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name THRESHOLD[15:0] Bit Name Function 15:0 THRESHOLD[15:0] Transmit Audio Dynamic Range Control Threshold. Range is from –40 to 0 dBFS in 1 dB steps (0xFFD8–0x0). Default is 0xFFD8 (–40 dBFS).
42 Rev. 1.0 Property 0x2202. TX_ACOMP_ATTACK_TIME Sets the time required for the device to respond to audio level transitions from below the threshold in the gain region to above the threshold in the compression region. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0.5 ms, or Available in: All Default: 0x0000 Range: 0–9 B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 000000000000 A T T A C K [ 3 : 0 ] Bit Name Function 15:4 Reserved Always write to 0. 3:0 ATTACK[3:0] Transmit Audio Dynamic Range Control Attack Time. 0 = 0.5 ms (default) 1 = 1.0 ms 2 = 1.5 ms 3 = 2.0 ms 4 = 2.5 ms 5 = 3.0 ms 6 = 3.5 ms 7 = 4.0 ms 8 = 4.5 ms 9 = 5.0 ms
Rev. 1.0 43 Property 0x2203. TX_ACOMP_RELEASE_TIME Sets the time required for the device to respond to audio level transitions from above the threshold in the compression region to below the threshold in the gain region . The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 1000 ms, or 4. Available in: All Default: 0x0004 Range: 0–4 Property 0x2204. TX_ACOMP_GAIN Sets the gain for audio dynamic range control from 0 to 20 dB in 1 dB units. For example, a setting of 15 dB would be 15 = 0xF. The gain is applied to the audio below the threshold set by the TX_ACOMP_THRESHOLD property. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 15 dB or 0xF. Available in: All Default: 0x000F (15) Units: 1 dB Step: 1 dB Range: 0–20 B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 0000000000000R E L E A S E [ 2 : 0 ] Bit Name Function 15:3 Reserved Always write to 0. 2:0 RELEASE[2:0] Transmit Audio Dynamic Range Control Release Time. 0 = 100 ms 1 = 200 ms 2 = 350 ms 3 = 525 ms 4 = 1000 ms (default) B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name GAIN[5:0] Bit Name Function 15:6 Reserved Always write to 0. 5:0 GAIN[5:0] Transmit Audio Dynamic Range Control Gain. Range is from 0 to 20 dB in 1 dB steps. Default is 15.
44 Rev. 1.0 Property 0x2205. TX_LIMITER_RELEASE_TIME Sets the time required for the device to respond to audio level transitions from above the limiter threshold to below the limiter threshold. The CTS bit (and optional interrup t) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 5.01 ms, or 102. Note: TX_LIMITER_RELEASE_TIME is supported in FMTX component 2.0 or later. Available in: All except Si4710-A10 Default 0x0066 (102) Step: 1 Range: 5–2000 B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name LIMITERTC[15:0] Bit Name Function 15:0 LMITERTC[15:0] Sets the limiter release time. 5 = 102.39 ms 6 = 85.33 ms 7 = 73.14 ms 8 = 63.99 ms 10 = 51.19 ms 13 = 39.38 ms 17 = 30.11 ms 25 = 20.47 ms 51 = 10.03 ms 57 = 8.97 ms 64 = 7.99 ms 73 = 7.01 ms 85 = 6.02 ms 102 = 5.01 ms (default) 127 = 4.02 ms 170 = 3.00 ms 255 = 2.00 ms 510 = 1.00 ms 1000 = 0.50 ms 2000 = 0.25 ms
Rev. 1.0 45 Property 0x2300. TX_ASQ_INTERRUPT_SELECT This property is used to enable which Audio Signal Quality (ASQ) measurements trigger ASQ_INT bit in the TX_ASQ_STATUS command. OVERMODIEN bit enables ASQ interrupt by the OVERMOD bit, which turns on with overmodulation of the FM output signal due to excessive input signal level. IALHIEN and IALLIEN bits enable ASQ interrupt by the IALH and IALL bits, which report high or low input audio condition. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. Available in: All Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0000000 O V E R M O D I E N I A L H I E N I A L L I E N Bit Name Function 15:3 Reserved Always write to 0.
2 OVERMODIEN
Overmodulation Detection Enable. 0 = OVERMOD detect disabled (default). 1 = OVERMOD detect enabled.
1 IALHIEN
Input Audio Level Detection High Threshold Enable. 0 = IALH detect disabled (default). 1 = IALH detect enabled.
0 IALLIEN
Input Audio Level Detection Low Threshold Enable. 0 = IALL detect disabled (default). 1 = IALL detect enabled.
46 Rev. 1.0 Property 0x2301. TX_ASQ_LEVEL_LOW This property sets the low audio level threshold relative to 0 dBFS in 1 dB increments, which is used to trigger the IALL bit. This threshold can be set to detect a silence condition in the input audio allowing the host to take an appropriate action such as disabling the RF carrier or powering down the chip. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0x0000 and the range is 0 to –70. Available in: All Default: 0x0000 Units: 1 dB Step: 1 dB Range: –70 to 0 Property 0x2302. TX_ASQ_DURATION_LOW This property is used to determine the duration (in 1 m s increments) that the input signal must be below the TX_ASQ_LEVEL_LOW threshold in order for an IALL condition to be generated. The range is 0 ms to 65535 ms, and the default is 0 ms. Note that the TX_ASQ_DURATION_LOW and TX_ASQ_DURATION_HIGH counters start and the TX_ASQ_STATUS command will only retu rn valid data after a call to TX_TUNE_FREQ, TX_TUNE_POWER, or TX_TUNE_MEASURE. The CTS bit (and opti onal interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. Available in: All Default: 0x0000 Units: 1 ms Step: 1 ms Range: 0–65535 B i t D 1 5 D 1 4D 1 3 D 1 2 D 1 1 D 1 0D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 000000 0 0 I A L L T H [ 7 : 0 ] Bit Name Function 15:8 Reserved Always write to 0. 7:0 IALLTH[7:0] Input Audio Level Low Threshold. Threshold which input audio level must be below in order to detect a low audio condition. Specified in units of dBFS in 1 dB steps (–70 .. 0). Default is 0. B i t D 1 5 D 1 4D 1 3 D 1 2 D 1 1 D 1 0D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name IALLDUR[15:0] Bit Name Function 15:0 IALLDUR[15:0] Input Audio Level Duration Low. Required duration the input audio level must fall below IALLTH to trigger an IALL inter- rupt. Specified in 1mS increments (0–65535 ms). Default is 0.
Rev. 1.0 47 Property 0x2303. TX_ASQ_LEVEL_HIGH This property sets the high audio level threshold relative to 0 dBFS in 1 dB increments, which is used to trigger the IALH bit. This threshold can be set to detect an activity condition in the input audio allowing the host to take an appropriate action such as enabling the RF carrier afte r an extended silent period. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0x0000 and the range is 0 to –70. Available in: All Default: 0x0000 Units: 1 dB Step: 1 dB Range: –70 to 0 B i t D 1 5 D 1 4D 1 3 D 1 2 D 1 1 D 1 0D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 000000 0 0 I A L H T H [ 7 : 0 ] Bit Name Function 15:8 Reserved Always write to 0. 7:0 IALHTH[7:0] Input Audio Level High Threshold Threshold which input audio level must be above in order to detect a high audio condition. Specified in units of dBFS in 1 dB steps (–70 .. 0). Default is 0.
48 Rev. 1.0 Property 0x2304. TX_ASQ_DURATION_HIGH This property is used to determine the duration (in 1 m s increments) that the input signal must be above the TX_ASQ_LEVEL_HIGH threshold in order for a IALH condit ion to be generated. The range is 0 to 65535 ms, and the default is 0 ms. Note that the TX_ASQ_DURATION_LOW and TX_ASQ_DURATION_HIGH counters start and the TX_ASQ_STATUS command will only return valid data after a call to TX_TUNE_FREQ, TX_TUNE_POWER, or TX_TUNE_MEASURE. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. Available in: All Default: 0x0000 Units: 1 ms Step: 1 ms Range: 0–65535 B i t D 1 5 D 1 4D 1 3 D 1 2 D 1 1 D 1 0D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name IALHDUR[15:0] Bit Name Function 15:0 IALHDUR[15:0] Input Audio Level Duration High. Required duration the input audio level must exceed IALHTH to trigger an IALH inter- rupt. Specified in 1 ms increments (0 – 65535 ms). Default is 0.
Rev. 1.0 49 Property 0x2C00. TX_RDS_INTERRUPT_SOURCE Configures the RDS interrupt sources. The CTS bit (and opti onal interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. Note: TX_RDS_INTERRUPT_SOURCE is supported in FMTX component 2.0 or later. Available in: Si4711/13/21 Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 000000 0 0 0 0 0 RDS PSXMIT RDS CBUFXMIT RDS- FIFOXMIT RDS CBUFWRAP RDS- FIFOMT Bit Name Function
4 RDSPSXMIT
0 = Do not interrupt (default). 1 = Interrupt when a RDS PS Group has been transmitted. The interrupt occurs when a PS group begins transmission.
3 RDSCBUFXMIT
0 = Do not interrupt (default). 1 = Interrupt when a RDS Group has been transmitted from the Circular Buffer. The interrupt occurs when a group is fetched from the buffer.
2 RDSFIFOXMIT
0 = Do not interrupt (default). 1 = Interrupt when a RDS Group has been transmitted from the FIFO Buffer. The interrupt occurs when a group is fetched from the buffer.
1 RDSCBUFWRAP
0 = Do not interrupt (default). 1 = Interrupt when the RDS Group Circular Buffer has wrapped. The interrupt occurs when the last group is fetched from the buffer.
0 RDSFIFOMT
0 = Do not interrupt (default). 1 = Interrupt when the RDS Group FIFO Buffer is empty. The interrupt occurs when the last group is fetched from the FIFO.
50 Rev. 1.0 Property 0x2C01. TX_RDS_PI Sets the RDS PI code to be transmitted in block A and block C (for type B groups). The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. Note: TX_RDS_PI is supported in FMTX component 2.0 or later. Available in: Si4711/13/21 Default: 0x40A7 Property 0x2C02. TX_RDS_PS_MIX Sets the ratio of RDS PS (group 0A) and circular buffer/FIFO groups. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. Note: TX_RDS_PS_MIX is supported in FMTX component 2.0 or later. Available in: Si4711/13/21 Default: 0x0003 Range: 0–6 B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name RDSPI[15:0] Bit Name Function 15:0 RDSPI[15:0] Transmit RDS Program Identifier. RDS program identifier data. B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2 D 1 D 0 Name 0000000000000 R D S P S M I X [ 2 : 0 ] Bit Name Function 15:3 Reserved Always write to 0. 2:0 RDSPSMIX[2:0] Transmit RDS Mix. 000 = Only send RDS PS if RDS Group Buffer is empty 001 = Send RDS PS 12.5% of the time 010 = Send RDS PS 25% of the time 011 = Send RDS PS 50% of the time (default) 100 = Send RDS PS 75% of the time 101 = Send RDS PS 87.5% of the time 110 = Send RDS PS 100% of the time
Rev. 1.0 51 Property 0x2C03. TX_RDS_PS_MISC Configures miscellaneous RDS flags. The CTS bit (and option al interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. Note: TX_RDS_PS_MISC is supported in FMTX component 2.0 or later. Available in: Si4711/13/21 Default: 0x1008 B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5 D 4 D 3 D 2D 1D 0 Name RDSD3 RDSD2 RDSD1 RDSD0 FORCEB RDSTP RDSPTY[4:0] RDSTA RDSMS 0 0 0 Bit Name Function
15 RDSD3
Dynamic PTY code. 0 = Static PTY (default). 1 = Indicates that the PTY code is dynamically switched.
14 RDSD2
Compressed code. 0 = Not compressed (default). 1 = Compressed.
13 RDSD1
Artificial Head code. 0 = Not artificial head (default). 1 = Artificial head.
12 RDSD0
Mono/Stereo code. 0 = Mono. 1 = Stereo (default).
11 FORCEB
Use the PTY and TP set here in all block B data. 0 = FIFO and BUFFER use PTY and TP as when written (default). 1 = FIFO and BUFFER force PTY and TP to be the settings in this property. 10 RDSTP Traffic Program Code (default = 0). 9:5 RDSPTY[4:0] Program Type Code (default = 0). 4R D S T A Traffic Announcement Code (default = 0). 3R D S M S Music/Speech Switch Code. 0 = Speech. 1 = Music (default). 2:0 Reserved Always write to 0.
52 Rev. 1.0 Property 0x2C04. TX_RDS_PS_REPEAT_COUNT Sets the number of times a program service group 0A is repeated. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. Note: TX_RDS_PS_REPEAT_COUNT is supported in FMTX component 2.0 or later. Available in: Si4711/13/21 Default: 0x0003 Range: 1–255 Property 0x2C05. TX_RDS_PS_MESSAGE_COUNT Sets the number of program service messages through whic h to cycle. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. Note: TX_RDS_PS_MESSAGE_COUNT is supported in FMTX component 2.0 or later. Available in: Si4711/13/21 Default: 0x0001 Range 1–12 B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 00000000 R D SPSRC[7:0] Bit Name Function 15:8 Reserved Always write to 0. 7:0 RDSPSRC[7:0] Transmit RDS PS Repeat Count. Number of times to repeat transmission of a PS message before transmitting the next PS message. B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 000000000000 R D SPSMC[3:0] Bit Name Function 15:4 Reserved Always write to 0. 3:0 RDSPSMC[3:0] Transmit RDS PS Message Count. Number of PS messages to cycle through. Default is 1.
Rev. 1.0 53 Property 0x2C06. TX_RDS_PS_AF Sets the AF RDS Program Service Alternate Frequency. This provides the ability to inform the receiver of a single alternate frequency using AF Method A coding and is tr ansmitted along with the RDS_PS Groups. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. Note: TX_RDS_PS_AF is supported in FMTX component 2.0 or later. Available in: Si4711/13/21 Default: 0xE0E0 Range: 0xE000–0xE0CC B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name RDSAF[15:0] Bit Name Function 15:0 RDSAF[15:0] Transmit RDS Program Service Alternate Frequency. 0xE101 = 1 AF @ 87.6 MHz 0xE102 = 1 AF @ 87.7 MHz ... 0xE1CB = 1 AF @ 107.8 MHz 0xE1CC = 1 AF @ 107.9 MHz 0xE0E0 = No AF exists (default)
54 Rev. 1.0 Property 0x2C07. TX_RDS_FIFO_SIZE Sets the RDS FIFO size in number of blocks. Note that the value written must be one larger than the desired FIFO size. The number of bl ocks allocated will reduce the si ze of the Circular RDS Group Buffer by the same amount. For instance, if RDSFIFOSZ = 20, then the RDS Circular Buffer will be reduced by 20 blocks. The minimum number of blocks which should be allocated is 4. This provides enough room for a single group of any type (xA or xB) to be transmitted. Groups xA require 3 Blocks, Groups xB require 2 Blocks as block C' is always the same as the RDS PI code. Before setting this value, determine the availa ble blocks through the TX_RDS_FIFO command, as the buffer size may vary between versions or part numbers. The guaranteed minimum FIFO size, however, is 53 blocks. The RDS FIFO and the RDS Circular Buffer s hould be emptied with the TX_RDS_FIFO command prior to changing the size of the FIFO. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. Note: TX_RDS_FIFO_SIZE is supported in FMTX component 2.0 or later. Available in: Si4711/13/21 Default: 0x0000 Units: blocks Step: 3 blocks Range: 0, 4, 7, 10–54 Note: Actual maximum FIFO size returned by the TX_RDS_BUFF command is larger, however, this is 53 blocks is the guaranteed FIFO size. B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 00000000 R D S F I F O S Z [ 7 : 0 ] Bit Name Function 15:8 Reserved Always write 0. 7:0 RDSFIFOSZ[7:0] Transmit RDS FIFO Size. 0 = FIFO disabled (default)
Table 8. FM/RDS Receiver Command Summary "7.2. Powerup from a Component Patch" on page 216.
Table 9. FM/RDS Receiver Property Summary Sets frequency of reference clock in Hz. disable the AFC. Default is 32768 Hz. tor. Default value is 20 kHz.
disable soft mute. Default is 16 dB. Sets SNR threshold to engage soft mute. Table 9. FM/RDS Receiver Property Summary (Continued)
Sets the bottom of the FM band for seek. 0x1401 FM_SEEK_BAND_TOP Sets the top of the FM band for seek. Selects frequency spacing for FM seek.
threshold). To force stereo, set this to 100. force mono, set to 0. The default is 60.
samples. Default value is 24 µs. impulse blanking to the original samples.
cut-off frequency. Default value is 20. frequency. Default value is 0 (disabled).
Table 10. Status Response for the FM/RDS Receiver 0 = Wait before sending next command. 1 = Clear to send next command. 5:4 Reserved Values may vary. Received Signal Quality Interrupt. 0 = Received Signal Quality measurement has not been triggered. 1 = Received Signal Quality measurement has been triggered. Radio Data System (RDS) Interrupt (Si4705/21/31/35/37/39/85 Only). 0 = Radio data system interrupt has not been triggered. 1 = Radio data system interrupt has been triggered. Seek/Tune Complete Interrupt. 0 = Tune complete has not been triggered. 1 = Tune complete has been triggered.
64 Rev. 1.0 5.2.1. FM/RDS Receiver Commands Command 0x01. POWER_UP Initiates the boot process to move the device from powerdown to powerup mode. The boot can occur from internal device memory or a system controller downloaded patch. To confirm that the patch is compatible with the internal device library revision, the library revision should be confirmed by issuing the POWER_UP command with FUNC = 15 (query library ID). The device returns the resp onse, including the library revision, and then moves into powerdown mode. The device can then be placed in powerup mode by issuing the POWER_UP command with FUNC = 0 (FM Receive) and the patch may be applied (See Section "7.2. Powerup from a Component Patch" on page 216). The POWER_UP command configures the state of ROUT (p in 13, Si474x pin 15) and LOUT (pin 14, Si474x pin 16) for analog audio mode and GPO2/INT (pin 18, Si474x pin 20) for interrupt operation. For the Si4705/21/31/35/37/39/84/85-B20, the POWER_UP command also configures the state of GPO3/DCLK (pin 17, Si474x pin 19), DFS (pin 16, Si474x pin 18), and DOUT (pin 15, Si474x pin 17) for digital audio mode. The command configures GPO2/INT interrupts (GPO2OEN) and CTS interrupts (CTSIEN). If both are enabled, GPO2/INT is driven high during normal operation and low for a minimum of 1 µs during the interrupt. The CTSIEN bit is duplicated in the GPO_IEN property. The command is complete when the CTS bit (and optional interrupt) is set. Note: To change function (e.g. FM RX to AM RX or FM RX to FM TX), issue POWER_DOWN command to stop current func- tion; then, issue POWER_UP to start new function. Note: Delay at least 500 ms between powerup command and first tu ne command to wait for the oscillator to stabilize if XOSCEN is set and crystal is used as the RCLK. Available in: All Command Arguments: Two Response Bytes: None (FUNC = 0), Seven (FUNC = 15) Command B i t D 7 D 6D 5D 4D 3D 2D 1D 0 CMD 00 0 0 0 0 0 1 ARG1 CTSIEN GPO2OEN PATCH XOSCEN FUNC[3:0] ARG2 OPMODE[7:0] ARG Bit Name Function
17 C T S I E N
CTS Interrupt Enable. 0 = CTS interrupt disabled. 1 = CTS interrupt enabled. 1 6 GPO2OEN GPO2 Output Enable. 0 = GPO2 output disabled. 1 = GPO2 output enabled. Patch Enable. 0 = Boot normally. 1 = Copy NVM to RAM, but do not boot. After CTS has been set, RAM may be patched.
Rev. 1.0 65 Response (FUNC = 0, FM Receive) Response (FUNC = 15, Query Library ID) 1 4 XOSCEN Crystal Oscillator Enable. Note: Set to 0 for Si4740/41/42/43/44/45/49 0 = Use external RCLK (crystal oscillator disabled). 1 = Use crystal oscillator (RCLK and GPO3/DCLK with external 32.768 kHz crys- tal and OPMODE=00000101). See Si47xx Data Sheet Application Schematic for external BOM details. 1 3:0 FUNC[3:0] Function. 0=F M R e c e i v e . 1–14 = Reserved. 15 = Query Library ID. 2 7:0 OPMODE[7:0] Application Setting. 00000000 = RDS output only (no audio outputs) Si4749 only 00000101 = Analog audio outputs (LOUT/ROUT). 00001011 = Digital audio output (DCLK, LOUT/DFS, ROUT/DIO) 10110000 = Digital audio outputs (DCLK, DFS, DIO) (Si4705/21/31/35/37/39/41/43/45/84/85 FMRX component 2.0 or later with XOSCEN = 0). 10110101 = Analog and digital audio outputs (LOUT/ROUT and DCLK, DFS, DIO) (Si4705/21/31/35/37/39/41/43/45/84/85 FMRX component 2.0 or later with XOSCEN = 0). Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT RDSINT X STCINT Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT RDSINT X STCINT RESP1 PN[7:0] RESP2 FWMAJOR[7:0] RESP3 FWMINOR[7:0] RESP4 RESERVED[7:0] RESP5 RESERVED[7:0] RESP6 CHIPREV[7:0] RESP7 LIBRARYID[7:0] RESP Bit Name Function 1 7:0 PN[7:0] Final 2 digits of part number (HEX). 2 7:0 FWMAJOR[7:0] Firmware Major Revision (ASCII). 3 7:0 FWMINOR[7:0] Firmware Minor Revision (ASCII). ARG Bit Name Function
66 Rev. 1.0 Command 0x10. GET_REV Returns the part number, chip revision, firmware revision, patch revision and component revision numbers. The command is complete when the CTS bit (and optional inte rrupt) is set. This command may only be sent when in powerup mode. Available in: All Command arguments: None Response bytes: Fifteen (Si4705/06 only), Eight (Si4704/2x/3x/4x) Command Response 4 7:0 RESERVED[7:0] Reserved, various values. 5 7:0 RESERVED[7:0] Reserved, various values. 6 7:0 CHIPREV[7:0] Chip Revision (ASCII). 7 7:0 LIBRARYID[7:0] Library Revision (HEX). B i t D 7 D 6 D 5 D 4D 3D 2D 1D 0 CMD 000 1 0 0 0 0 B i t D 7D 6D 5D 4D 3D 2D 1D 0 STATUS CTS ERR X X RSQINT RDSINT X STCINT RESP1 PN[7:0] RESP2 FWMAJOR[7:0] RESP3 FWMINOR[7:0] RESP4 PATCHH[7:0] RESP5 PATCHL[7:0] RESP6 CMPMAJOR[7:0] RESP7 CMPMINOR[7:0] RESP8 CHIPREV[7:0] RESP10 Reserved RESP11 Reserved RESP12 Reserved RESP13 Reserved RESP14 Reserved RESP15 CID[7:0] (Si4705 only)
Rev. 1.0 67 Command 0x11. POWER_DOWN Moves the device from powerup to powerdown mode. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Note that only the POWER_UP command is accepted in powerdown mode. If the system controller writes a command other than POWER_UP when in powerdown mode, the device does not respond. The device will only respond when a POWER_UP command is written. GPO pins are powered down and not active during this state. For optimal power down current, GPO2 must be either internally driven low through GPIO_CTL command or externally driven low. Note: In FMRX component 1.0, a reset is required when the system controller writes a command other than POWER_UP when in powerdown mode. Note: The following describes the state of all the pins when in powerdown mode: GPIO1, GPIO2, and GPIO3 = 0 ROUT, LOUT, DOUT, DFS = HiZ Available in: All Command arguments: None Response bytes: None Command Response RESP Bit Name Function 1 7:0 PN[7:0] Final 2 digits of Part Number (HEX). 2 7:0 FWMAJOR[7:0] Firmware Major Revision (ASCII). 3 7:0 FWMINOR[7:0] Firmware Minor Revision (ASCII). 47 : 0 P A T C H H[7:0] Patch ID High Byte (HEX). 57 : 0 P A T C H L[7:0] Patch ID Low Byte (HEX). 6 7:0 CMPMAJOR[7:0] Component Major Revision (ASCII). 7 7:0 CMPMINOR[7:0] Component Minor Revision (ASCII). 8 7:0 CHIPREV[7:0] Chip Revision (ASCII). 15 7:0 CID[7:0] CID (Si4705/06 only). B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 00010001 Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT RDSINT X STCINT
68 Rev. 1.0 Command 0x12. SET_PROPERTY Sets a property shown in Table 9, “FM/RDS Receiver Property Summary,” on page 56. The CTS bit (and optional interrupt) is set when it is safe to send the next co mmand. This command may only be sent when in powerup mode. See Figure 29, “CTS and SET_PROPERTY Command Complete tCOMP Timing Model,” on page 226 and Table 46, “Command Timing Parameters for the FM Receiver,” on page 228. Available in: All Command Arguments: Five Response bytes: None Command B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 00010010 ARG1 00000000 ARG2 PROPH[7:0] ARG3 PROPL[7:0] ARG4 PROPDH[7:0] ARG5 PROPDL[7:0] ARG Bit Name Function 1 7:0 Reserved Always write to 0. 27 : 0 P R O P H[7:0] Property High Byte. This byte in combination with PROPL is used to specify the property to modify. 37 : 0 P R O P L[7:0] Property Low Byte. This byte in combination with PROPH is used to specify the property to modify. 47 : 0 P R O P D H[7:0] Property Value High Byte. This byte in combination with PROPDL is used to set the property value. 57 : 0 P R O P D L[7:0] Property Value Low Byte. This byte in combination with PROPDH is used to set the property value.
Rev. 1.0 69 Command 0x13. GET_PROPERTY Gets a property as shown in Table 9, “FM/RDS Receiv er Property Summary,” on page 56. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Available in: All Command arguments: Three Response bytes: Three Command Response B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 00010011 ARG1 00000000 ARG2 PROPH[7:0] ARG3 PROPL[7:0] ARG Bit Name Function 1 7:0 Reserved Always write to 0. 27 : 0 P R O P H[7:0] Property High Byte. This byte in combination with PROPL is used to specify the property to get. 37 : 0 P R O P L[7:0] Property Low Byte. This byte in combination with PROPH is used to specify the property to get. B i tD 7D 6D 5D 4D 3D 2D 1D 0 STATUS CTS ERR X X RSQINT RDSINT X STCINT RESP1 00000000 RESP2 PROPDH[7:0] RESP3 PROPDL[7:0] RESP Bit Name Function 1 7:0 Reserved Always returns 0. 27 : 0 P R O P D H[7:0] Property Value High Byte. This byte in combination with PROPDL represents the requested property value. 37 : 0 P R O P D L[7:0] Property Value High Byte. This byte in combination with PROPDH represents the requested property value.
70 Rev. 1.0 Command 0x14. GET_INT_STATUS Updates bits 6:0 of the status byte. This command shou ld be called after any command that sets the STCINT, RDSINT, or RSQINT bits. When polling this command should be periodically called to m onitor the STATUS byte, and when using interrupts, this command should be called after the interrupt is set to update the STATUS byte. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be set when in powerup mode. Available in: All Command arguments: None Response bytes: None Command Response Command 0x20. FM_TUNE_FREQ Sets the FM Receive to tune a frequency between 64 and 108 MHz in 10 kHz units. The CTS bit (and optional interrupt) is set when it is safe to send the next command. The ERR bit (and optional interrupt) is set if an invalid argument is sent. Note that only a si ngle interrupt occurs if both the CTS and ERR bits are set. The optional STC interrupt is set when the command completes. The STCINT bit is set only after the GET_INT_STATUS command is called. This command may only be sent when in powerup mode. The command clears the STC bit if it is already set. See Figure 28, “CTS and STC Timing Model,” on page 226 and Table 46, “Command Timing Parameters for the FM Receiver,” on page 228. FM: LO frequency is 128 kHz above RF for RF frequencies <
90 MHz and 128 kHz below RF for RF frequencies >
90 MHz. For example, LO frequency is 80.128 MHz when tuning to 80.00 MHz. Note: For FMRX components 2.0 or earlier, tuning range is 76–108 MHz. Note: Fast bit is supported in FMRX components 4.0 or later. Note: Freeze bit is supported in FMRX components 4.0 or later. Available in: All Command arguments: Four Response bytes: None B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 00010100 B i tD 7D 6D 5D 4D 3D 2D 1D 0 STATUS CTS ERR X X RSQINT RDSINT X STCINT
Rev. 1.0 71 Command Response B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 00100000 ARG1 000000 F R E E Z E F A S T ARG2 FREQH[7:0] ARG3 FREQL[7:0] ARG4 ANTCAP[7:0] ARG Bit Name Function 1 7:1 Reserved Always write to 0.
11 F R E E Z E
Freeze Metrics During Alternate Frequency Jump. If set will cause the blend, hicut, and softmute to transition as a function of the associated attack/release parameters rather than instantaneously when tuning to alternate station. 1 0 FAST FAST Tuning. If set, executes fast and invalidated tune. The tune status will not be accurate. 27 : 0 F R E Q H[7:0] Tune Frequency High Byte. This byte in combination with FREQL selects the tune frequency in 10 kHz. In FM mode the valid range is from 6400 to 10800 (64–108 MHz). 37 : 0 F R E Q L[7:0] Tune Frequency Low Byte. This byte in combination with FREQH selects the tune frequency in 10 kHz. In FM mode the valid range is from 6400 to 10800 (64–108 MHz). 4 7:0 ANTCAP[7:0] Antenna Tuning Capacitor (valid only when using TXO/LPI pin as the antenna input). This selects the value of the antenna tuning capacitor manually, or automati- cally if set to zero. The valid range is 0 to 191. Automatic capacitor tuning is recommended. Note: When tuned manually, the varactor is offset by four codes. For example, if the varactor is set to a value of 5 manually, when read back the value will be 1. The four codes (1pf) delta accounts for the capacitance at the chip. Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT RDSINT X STCINT
72 Rev. 1.0 Command 0x21. FM_SEEK_START Begins searching for a valid frequency. Clears any pending STCINT or RSQINT interrupt status. The CTS bit (and optional interrupt) is set when it is safe to send the ne xt command. RSQINT status is only cleared by the RSQ status command when the INTACK bit is set. The ERR bit (and optional interrupt) is se t if an invalid argument is sent. Note that only a single interrupt occurs if both the CTS and ERR bits are set. The optional STC interrupt is set when the command completes. The STCINT bit is set only after the GET_INT_STATUS command is called. This command may only be sent when in powerup mode. The command clears the STCINT bit if it is already set. See Figure 28, “CTS and STC Timing Model,” on page 226 and Table 46, “Command Timing Parameters for the FM Receiver,” on page 228. Available in: All Command arguments: One Response bytes: None Command Response B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 00100001 ARG1 0 0 0 0 SEEKUP WRAP 0 0 ARG Bit Name Function 1 7:4 Reserved Always write to 0. 1 3 SEEKUP Seek Up/Down. Determines the direction of the search, either UP = 1, or DOWN = 0.
12 W R A P
Wrap/Halt. Determines whether the seek should Wrap = 1, or Halt = 0 when it hits the band limit. 1 1:0 Reserved Always write to 0. B i t D 7D 6D 5D 4D 3D 2D 1D 0 STATUS CTS ERR X X RSQINT RDSINT X STCINT
Rev. 1.0 73 Command 0x22. FM_TUNE_STATUS Returns the status of FM_TUNE_F REQ or FM_SEEK_START commands. Th e command return s the current frequency, RSSI, SNR, multipath, and the antenna t uning capacitance value (0-191). The command clears the STCINT interrupt bit when INTACK bit of ARG1 is set. The CTS bit (and opt ional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Available in: All Command arguments: One Response bytes: Seven Command Response B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 00100010 ARG1 000000 C A N C E L I N T A C K ARG Bit Name Function 1 7:2 Reserved Always write to 0. 11 C A N C E L Cancel seek. If set, aborts a seek currently in progress. 10 I N T A C K Seek/Tune Interrupt Clear. If set, clears the seek/tune complete interrupt status indicator. B i tD 7D 6D 5D 4D 3D 2D 1D 0 STATUS CTS ERR X X RSQINT RDSINT X STCINT RESP1 B L T F XXXXX A F C R L V A L I D RESP2 READFREQH[7:0] RESP3 READFREQL[7:0] RESP4 RSSI[7:0] RESP5 SNR[7:0] RESP6 MULT[7:0] RESP7 READANTCAP[7:0] (Si4704/05/06/2x only)
74 Rev. 1.0 RESP Bit Name Function
17 B L T F
Band Limit. Reports if a seek hit the band limit (WRAP = 0 in FM_START_SEEK) or wrapped to the original frequency (WRAP = 1). 1 6:2 Reserved Always returns 0. 1 1 AFCRL AFC Rail Indicator. Set if the AFC rails.
10 V A L I D
Valid Channel. Set if the channel is currently valid as determined by the seek/tune proper- ties (0x1403, 0x1404, 0x1108) and would have been found during a Seek. 2 7:0 READFREQ H[7:0] Read Frequency High Byte. This byte in combination with READFREQL returns frequency being tuned (10 kHz). 3 7:0 READFREQ L[7:0] Read Frequency Low Byte. This byte in combination with READFREQH returns frequency being tuned (10 kHz). 4 7:0 RSSI[7:0] Received Signal Strength Indicator. This byte contains the receive signal strength when tune is complete (dBµV). 5 7:0 SNR[7:0] SNR. This byte contains the SNR metric when tune is complete (dB). 6 7:0 MULT[7:0] Multipath. This byte contains the multipath metric when tune is complete. Multipath indi- cator is available only for Si474x, Si4706-C30 and later and Si4704/05/30/31/34/35/84/85 -D50 and later. 7 7:0 READANTCAP [7:0] Read Antenna Tuning Capacitor (Si4704/05/06/2x only). This byte contains the current antenna tuning capacitor value.
Rev. 1.0 75 Command 0x23. FM_RSQ_STATUS Returns status information about the received signal quality. The commands returns the RSSI, SNR, frequency offset, and stereo blend percentage. It also indicates valid channel (VALID), soft mute engagement (SMUTE), and AFC rail status (AFCRL). This command can be used to ch eck if the received signal is above the RSSI high threshold as reported by RSSIHINT, or below the RSSI low threshold as reported by RSSILINT. It can also be used to check if the signal is above the SNR high threshold as reported by SNRHINT, or below the SNR low threshold as reported by SNRLINT. For the Si4706/4x, it can be used to check if the detected multipath is above the multipath high threshold as reported by MULTHINT, or below the mu ltipath low threshold as reported by MULTLINT. If the PILOT indicator is set, it can also check whether the blend has crossed a threshold as indicated by BLENDINT. The command clears the RSQINT, BLENDINT, SNRHIN T, SNRLINT, RSSIHINT, RSSILINT, MULTHINT, and MULTLINT interrupt bits when INTACK bit of ARG1 is set. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Available in: All Command arguments: One Response bytes: Seven Command Response B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 00100011 ARG1 0000000 I N T A C K ARG Bit Name Function Interrupt Acknowledge. 0 = Interrupt status preserved. 1 = Clears RSQINT, BLENDINT, SNRHINT, SNRLINT, RSSIHINT, RSSILINT, MULTHINT, MULTLINT. Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT RDSINT X STCINT RESP1 BLENDINT X MULTHINT MULTLINT SNRHINT SNRLINT RSSIHINT RSSIILINT RESP2 X X X X SMUTE X AFCRL VALID RESP3 PILOT STBLEND[6:0] RESP4 RSSI[7:0] RESP5 SNR[7:0] RESP6 MULT[7:0] RESP7 FREQOFF[7:0]
76 Rev. 1.0 RESP Bit Name Function 1 7 BLENDINT Blend Detect Interrupt. 0 = Blend is within the Blend threshold settings. 1 = Blend goes above or below the Blend threshold settings. 15M U L T H I N T Multipath Detect High (Si474x, Si4706-C30 and later and Si4704/05/30/31/34/35/84/85-D50 and later only). 0 = Detected multipath value has not exceeded above the Multipath high threshold. 1 = Detected multipath value has exceeded above the Multipath high threshold. 14M U L T L I N T Multipath Detect Low (Si474x, Si4706-C30 and later and Si4704/05/30/31/34/35/84/85-D50 and later only). 0 = Detected multipath value has not fallen below the Multipath low threshold. 1 = Detected multipath value has fallen below the Multipath low threshold. 1 3 SNRHINT SNR Detect High. 0 = Received SNR has not exceeded above SNR high threshold. 1 = Received SNR has exceeded above SNR high threshold.
12 S N R L I N T
SNR Detect Low. 0 = Received SNR has not fallen below SNR low threshold. 1 = Received SNR has fallen below SNR low threshold. 1 1 RSSIHINT RSSI Detect High. 0 = RSSI has not exceeded above RSSI high threshold. 1 = RSSI has exceeded above RSSI high threshold. 1 0 RSSILINT RSSI Detect Low. 0 = RSSI has not fallen below RSSI low threshold. 1 = RSSI has fallen below RSSI low threshold. 23 S M U T E Soft Mute Indicator. Indicates soft mute is engaged. 21 A F C R L AFC Rail Indicator. Set if the AFC rails. 20 V A L I D Valid Channel. Set if the channel is currently valid and would have been found during a Seek. 37 P I L O T Pilot Indicator. Indicates stereo pilot presence. 3 6:0 STBLEND[6:0] Stereo Blend Indicator. Indicates amount of stereo blend in% (100 = full stereo, 0 = full mono). 4 7:0 RSSI[7:0] Received Signal Strength Indicator. Contains the current receive signal strength (0–127 dBµV). 5 7:0 SNR[7:0] SNR. Contains the current SNR metric (0–127 dB). 6 7:0 MULT[7:0] Multipath (Si474x, Si4706-C30 and later and Si4704/05/30/31/34/35/84/85-D50 and later only). Contains the current multipath metric. (0 = no multipath; 100 = full multipath) 7 7:0 FREQOFF[7:0] Frequency Offset. Signed frequency offset (kHz).
Rev. 1.0 77 Command 0x24. FM_RDS_STATUS Returns RDS information for current channel and reads an entry from the RDS FIFO. RDS information includes synch status, FIFO status, group data (blocks A, B, C, and D), and block er rors corrected. This command clears the RDSINT interrupt bit when INTACK bit in ARG1 is set and, if MTFIFO is set, th e entire RDS receive FIFO is cleared (FIFO is always cleared during FM_TUNE_FREQ or FM_SEEK_START). The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in power up mode. The FIFO size is 25 groups for FMRX component 2.0 or later, and 14 for FMRX component 1.0. Notes: 1. FM_RDS_STATUS is supported in FMRX component 2.0 or later. 2. MTFIFO is not supported in FMRX component 2.0. Available in: Si4705/06, Si4721, Si474x, Si4731/35/37/39, Si4785 Command arguments: One Response bytes: Twelve Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 1 0 0 1 0 0 ARG1 0 0 0 0 0 STATUSONLY MTFIFO INTACK ARG Bit Name Function
12 S T A T U S O N L Y
Status Only. Determines if data should be removed from the RDS FIFO. 0 = Data in BLOCKA, BLOCKB, BLOCKC, BLOCKD, and BLE contain the oldest data in the RDS FIFO. 1 = Data in BLOCKA will contain the last valid block A data received for the cur- rent station. Data in BLOCKB will contain the last valid block B data received for the current station. Data in BLE will describe the bit errors for the data in BLOCKA and BLOCKB. 1 1 MTFIFO Empty FIFO 0 = If FIFO not empty, read and remove oldest FIFO entry. 1 = Clear RDS Receive FIFO. 0 = RDSINT status preserved. 1 = Clears RDSINT. Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT RDSINT X STCINT RESP1 X X RDSNEWBLOCKB RDSNEWBLOCKA X RDSSYNCFOUND RDSSYNCLOST RDSRECV RESP2 X X X X X GRPLOST X RDSSYNC
78 Rev. 1.0 RESP3 RDSFIFOUSED[7:0] RESP4 BLOCKA[15:8] RESP5 BLOCKA[7:0] RESP6 BLOCKB[15:8] RESP7 BLOCKB[7:0] RESP8 BLOCKC[15:8] RESP9 BLOCKC[7:0] RESP10 BLOCKD[15:8] RESP11 BLOCKD[7:0] RESP12 BLEA[1:0] BLEB[1:0] BLEC[1:0] BLED[1:0] RESP Bit Name Function 1 5 RDSNEWBLOCKB RDS New Block B. 1 = Valid Block B data has been received. 1 4 RDSNEWBLOCKA RDS New Block A. 1 = Valid Block A data has been received. 1 2 RDSSYNCFOUND RDS Sync Found. 1 = Found RDS synchronization. 1 1 RDSSYNCLOST RDS Sync Lost. 1 = Lost RDS synchronization. 1 0 RDSRECV RDS Received. 1 = FIFO filled to minimum number of groups set by RDSFIFOCNT. 22 G R P L O S T Group Lost. 1 = One or more RDS groups discarded due to FIFO overrun. 2 0 RDSSYNC RDS Sync. 1 = RDS currently synchronized. 3 7:0 RDSFIFOUSED RDS FIFO Used. Number of groups remaining in the RDS FIFO (0 if empty). If non-zero, BLOCKA-BLOCKD contain the oldest FIFO entry and RDSFIFOUSED decre- ments by one on the next call to RDS_FIFO_STATUS (assuming no RDS data received in the interim). 4 7:0 BLOCKA[15:8] RDS Block A. Block A group data from oldest FIFO entry if STATUSONLY is 0. Last valid Block A data if STATUSONLY is 1 (Si4749, Si4706-C30 and later and Si4705/31/35/85-D50 and later only). 5 7:0 BLOCKA[7:0] 6 7:0 BLOCKB[15:8] RDS Block B. Block B group data from oldest FIFO entry if STATUSONLY is 0. Last valid Block B data if STATUSONLY is 1 (Si4749, Si4706-C30 and later and Si4705/31/35/85-D50 and later only). 7 7:0 BLOCKB[7:0] 8 7:0 BLOCKC[15:8] RDS Block C. Block C group data from oldest FIFO entry.9 7:0 BLOCKC[7:0] Bit D7 D6 D5 D4 D3 D2 D1 D0
Rev. 1.0 79 10 7:0 BLOCKD[15:8] RDS Block D. Block D group data from oldest FIFO entry.11 7:0 BLOCKD[7:0] 12 7:6 BLEA[1:0] RDS Block A Corrected Errors. 0 = No errors. 1 = 1–2 bit errors detected and corrected. 2 = 3–5 bit errors detected and corrected. 3 = Uncorrectable. 12 5:4 BLEB[1:0] RDS Block B Corrected Errors. 0 = No errors. 1 = 1–2 bit errors detected and corrected. 2 = 3–5 bit errors detected and corrected. 3 = Uncorrectable. 12 3:2 BLEC[1:0] RDS Block C Corrected Errors. 0 = No errors. 1 = 1–2 bit errors detected and corrected. 2 = 3–5 bit errors detected and corrected. 3 = Uncorrectable. 12 1:0 BLED[1:0] RDS Block D Corrected Errors. 0 = No errors. 1 = 1–2 bit errors detected and corrected. 2 = 3–5 bit errors detected and corrected. 3 = Uncorrectable. RESP Bit Name Function
80 Rev. 1.0 Command 0x27. FM_AGC_STATUS Returns the AGC setting of the device. The command re turns whether the AGC is enabled or disabled and it returns the LNA Gain index. This command may only be sent when in powerup mode. Available in: All Command arguments: None Response bytes: Two Command Response B i tD 7 D 6D 5D 4D 3D 2D 1D 0 CMD 0 0100111 B i tD 7 D 6D 5D 4D 3D 2D 1D 0 STATUS CTS ERR X X RSQINT RDSINT X STCINT RESP1 X XXXXXX READ_RF- AGCDIS RESP2 X X X READ_LNA_GAIN_INDEX[4:0] RESP Bit Name Function 1 0 READ_RFAGCDIS This bit indicates whether the RF AGC is disabled or not 0 = RF AGC is enabled 1 = RF AGC is disabled 2 4:0 READ_LNA_GAIN_INDEX These bits returns the value of the LNA GAIN index 0 = Minimum attenuation (max gain) 1 – 25 = Intermediate attenuation 26 = Maximum attenuation (min gain) Note: The max index is subject to change
Rev. 1.0 81 Command 0x28. FM_AGC_OVERRIDE Overrides AGC setting by disabling the AGC and forcing the LNA to have a certain gain that ranges between 0 (minimum attenuation) and 26 (maximum attenuation). This command may only be sent when in powerup mode. Available in: All Command arguments: Two Response bytes: None Command Response B i t D 7D 6D 5D 4D 3D 2D 1 D 0 CMD 0010100 0 ARG1 XXXXXXX R F A G C D I S ARG2 X X X LNA_GAIN_INDEX[4:0] ARG Bit Name Function
10 R F A G C D I S
This bit selects whether the RF AGC is disabled or not 0 = RF AGC is enabled 1 = RF AGC is disabled 2 4:0 LNA_GAIN_INDEX These bits set the value of the LNA GAIN index 0 = Minimum attenuation (max gain) 1 – 25 = Intermediate attenuation 26 = Maximum attenuation (min gain) Note: the max index is subject to change B i tD 7 D 6D 5D 4D 3D 2D 1D 0 STATUS CTS ERR X X RSQINT RDSINT X STCINT
82 Rev. 1.0 Command 0x80. GPIO_CTL Enables output for GPO1, 2, and 3. GPO1, 2, and 3 can be configured for output (Hi-Z or active drive) by setting the GPO1OEN, GPO2OEN, and GPO3OEN bit. The state (h igh or low) of GPO1, 2, and 3 is set with the GPIO_SET command. To avoid excessive current consumption due to oscillation, GPO pins should not be left in a high impedance state. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. The default is all GPO pins set for high impedance. Notes: 2. The use of GPO2 as an interrupt pin and/or the use of GPO3 as DCLK digital clock input will override this GPIO_CTL function for GPO2 and/or GPO3 respectively. Available in: All except Si4710-A10 Command arguments: One Response bytes: None Command Response B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 10000000 ARG1 0 0 0 0 GPO3OEN GPO2OEN GPO1OEN 0 ARG Bit Name Function 1 7:4 Reserved Always write 0. 1 3 GPO3OEN GPO3 Output Enable. 0 = Output Disabled (Hi-Z) (default). 1 = Output Enabled. 1 2 GPO2OEN GPO2 Output Enable. 0 = Output Disabled (Hi-Z) (default). 1 = Output Enabled. 1 1 GPO1OEN GPO1 Output Enable. 0 = Output Disabled (Hi-Z) (default). 1 = Output Enabled. 1 0 Reserved Always write 0. B i t D 7D 6D 5 D 4 D 3 D 2 D 1 D 0 STATUS CTS ERR X X X RDSINT ASQINT STCINT
Rev. 1.0 83 Command 0x81. GPIO_SET Sets the output level (high or low) for GPO1, 2, and 3. GP O1, 2, and 3 can be configured for output by setting the GPO1OEN, GPO2OEN, and GPO3OEN bit in the GPIO_CTL command. To avoid excessive current consumption due to oscillation, GPO pins should not be left in a high impedance state. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This prop erty may only be set or read when in powerup mode. The default is all GPO pins set for high impedance. Note: GPIO_SET is fully-supported in FMRX component 2.0 or la ter. Only bit GPO3LEVEL is supported in FMRX component 1.0. Available in: All except Si4710-A10 Command arguments: One Response bytes: None Command Response B i t D 7 D 6D 5D 4 D 3 D 2 D 1 D 0 CMD 1 0 0 0 000 1 ARG1 0 0 0 0 GPO3LEVEL GPO2LEVEL GPO1LEVEL 0 ARG Bit Name Function 1 7:4 Reserved Always write 0. 1 3 GPO3LEVEL GPO3 Output Level. 0 = Output low (default). 1 = Output high. 1 2 GPO2LEVEL GPO2 Output Level. 0 = Output low (default). 1 = Output high. 1 1 GPO1LEVEL GPO1 Output Level. 0 = Output low (default). 1 = Output high. 1 0 Reserved Always write 0. B i t D 7D 6D 5 D 4 D 3 D 2 D 1 D 0 STATUS CTS ERR X X X RDSINT ASQINT STCINT
84 Rev. 1.0 5.2.2. FM/RDS Receiver Properties Property 0x0001. GPO_IEN Configures the sources for the GPO2/INT interrupt pin. Valid sources are the lower 8 bits of the STATUS byte, including CTS, ERR, RSQINT, RDSINT (Si4705/21/31/ 35/37/39/41/43/45/85 only ), and STCINT bits. The corresponding bit is set before the interrupt occurs. The CT S bit (and optional interrupt) is set when it is safe to send the next command. The CTS interrupt enable (CTSIE N) can be set with this property and the POWER_UP command. The state of the CTSIEN bit set during the POWER_UP command can be read by reading this property and modified by writing this property. This property may only be set or read when in powerup mode. Errata:RSQIEN is non-functional on FMRX component 2.0. Available in: All Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 RSQREP RDSREP 0 STCREP CTSIEN ERRIEN 0 0 RSQIEN RDSIEN 0 STCIEN Bit Name Function 15:12 Reserved Always write to 0.
11 RSQREP
RSQ Interrupt Repeat. 0 = No interrupt generated when RSQINT is already set (default). 1 = Interrupt generated even if RSQINT is already set. RDS Interrupt Repeat (Si4705/21/31/35/37/39/41/43/45/85-C40 Only). 0 = No interrupt generated when RDSINT is already set (default). 1 = Interrupt generated even if RDSINT is already set. 9 Reserved Always write to 0. STC Interrupt Repeat. 0 = No interrupt generated when STCINT is already set (default). 1 = Interrupt generated even if STCINT is already set. 7C T S I E N CTS Interrupt Enable. After PowerUp, this bit reflects the CTSIEN bit in ARG1 of PowerUp Command. 0 = No interrupt generated when CTS is set. 1 = Interrupt generated when CTS is set. 6E R R I E N ERR Interrupt Enable. 0 = No interrupt generated when ERR is set (default). 1 = Interrupt generated when ERR is set. 5:4 Reserved Always write to 0. 3R S Q I E N RSQ Interrupt Enable. 0 = No interrupt generated when RSQINT is set (default). 1 = Interrupt generated when RSQINT is set. 2R D S I E N RDS Interrupt Enable (Si4705/21/31/35/37/39/41/43/45/85-C40 Only). 0 = No interrupt generated when RDSINT is set (default). 1 = Interrupt generated when RDSINT is set. 1 Reserved Always write to 0. 0S T C I E N Seek/Tune Complete Interrupt Enable. 0 = No interrupt generated when STCINT is set (default). 1 = Interrupt generated when STCINT is set.
Rev. 1.0 85 Property 0x0102. DIGITAL_OUTPUT_FORMAT Configures the digital audio output format. Configuration options include DCLK edge, data format, force mono, and sample precision. Available in: Si4705/06, Si4721/31/35/37/39, Si4730/34/36/38-D60 and later, Si4741/43/45, Si4784/85 Default: 0x0000 Note: DIGITAL_OUTPUT_FORMAT is supported in FM receive component 2.0 or later. B i t 1 51 41 31 21 11 098 7 6543 2 1 0 Name 000000 0 0O F A L L O M O D E [ 3 : 0 ]O M O N O O S I Z E [ 1 : 0 ] Bit Name Function 15:8 Reserved Always write to 0. 7O F A L L Digital Output DCLK Edge. 0 = use DCLK rising edge 1 = use DCLK falling edge 6:3 OMODE[3:0] Digital Output Mode. 0000 = I2S 0110 = Left-justified 1000 = MSB at second DCLK after DFS pulse 1100 = MSB at first DCLK after DFS pulse 2O M O N O Digital Output Mono Mode. 0 = Use mono/stereo blend (per blend thresholds) 1 = Force mono 1:0 OSIZE[1:0] Digital Output Audio Sample Precision. 0 = 16-bits 1 = 20-bits 2 = 24-bits 3=8 - b i t s
86 Rev. 1.0 Property 0x0104. DIGITAL_OUTPUT_SAMPLE_RATE Enables digital audio output and configures digital audio output sample rate in samples per second (sps). When DOSR[15:0] is 0, digital audio output is disabled. The over-sampling rate must be set in order to satisfy a minimum DCLK of 1 MHz. To enable digital audio output, program DOSR[15:0] with the sample rate in samples per second. The system controller must establish DCLK and DFS prior to enabling the digital audio output else the device will not respond and will require reset. The sample rate must be set to 0 before the DCLK/DFS is removed. FM_TUNE_FREQ command must be sent after the POWER_UP command to start the internal clocking before setting this property. Note: DIGITAL_OUPTUT_SAMPLE_RATE is supported in FM receive component 2.0 or later. Available in: Si4705/06, Si4721/31/35/37/39, Si4730/34/36/38-D60 and later, Si4741/43/45, Si4784/85 Default: 0x0000 (digital audio output disabled) Units: sps Range: 32–48 ksps, 0 to disable digital audio output B i t 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 Name DOSR[15:0] Bit Name Function 15:0 DOSR[15:0] Digital Output Sample Rate. 32–48 ksps. 0 to disable digital audio output.
send the next command. This property may only be set or read when in powerup mode. The default is 32768 Hz. Table 11. RCLK Gaps Frequency of Reference Clock in Hz. ±5%), or 0 (to disable AFC).
88 Rev. 1.0 Property 0x0202. REFCLK_PRESCALE Sets the number used by the prescaler to divide the external RCLK down to the internal REFCLK. The range may be between 1 and 4095 in 1 unit steps. For example, an RCLK of 13 MHz would require a prescaler value of 400 to divide it to 32500 Hz. The reference clock frequency property would then need to be set to 32500 Hz. The RCLK must be valid 10 ns before sending and 20 ns after completing the FM_TUNE_FREQ and FM_TUNE_START commands. In addition, the RCLK must be valid at all times for proper AFC operation. The RCLK may be removed or reconfigured at other times. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 1. Available in: All Default: 0x0001 Step: 1 Range: 1–4095 B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 000 RCLK SEL REFCLKP[11:0] Bit Name Function 15:13 Reserved Always write to 0. RCLKSEL. 0 = RCLK pin is clock source. 1 = DCLK pin is clock source. 11:0 REFCLKP[11:0] Prescaler for Reference Clock. Integer number used to divide clock frequency down to REFCLK frequency. The allowed REFCLK frequency range is between 31130 and 34406 Hz (32768 5%), or 0 (to disable AFC).
Rev. 1.0 89 Property 0x1100. FM_DEEMPHASIS Sets the FM Receive de-emphasis to 50 or 75 µs. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 75 µs. Available in: All except Si4749 Default: 0x0002 Property 0x1102. FM_CHANNEL_FILTER Selects bandwidth of channel filter applied at the demodulation stage. Default is automatic which means the device automatically selects proper channel filter. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 1. Available in: Si4706, Si4749, Si4704/05/30/31/34/35/84/85-D50 and later Default: 0x0001 (Si4706, Si4749, Si4705/31/35/85-D50 and later) 0x0000 (Si4704/30/34/84-D50 and later) Range: 0–4 Note: Automatic channel filter setting is not supported in FMRX component 3.0. B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2 D 1 D 0 Name 00000000000000 D E E M P H [ 1 : 0 ] Bit Name Function 15:2 Reserved Always write to 0. 1:0 DEEMPH[1:0] FM De-Emphasis. 10 = 75 µs. Used in USA (default) 01 = 50 µs. Used in Europe, Australia, Japan 00 = Reserved 11 = Reserved B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name FMCHFILT[15:0] Bit Name Function 15:0 FM_CHANNEL_FILTER 0 = Automatically select proper channel filter. 1 = Force wide (110 kHz) channel filter. 2 = Force narrow (84 kHz) channel filter. 3 = Force narrower (60 kHz) channel filter. 4 = Force narrowest (40 kHz) channel filter.
90 Rev. 1.0 Property 0x1105. FM_BLEND_STEREO_THRESHOLD Sets RSSI threshold for stereo blend (Full stereo above threshold, blend below threshold). To force stereo, set this to 0. To force mono, set this to 127. The CTS bit (and op tional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 49 dBµV. Available in: Si470x/2x, Si473x-C40 and earlier Default: 0x0031 Units: dBµV Step: 1 Range: 0–127 Property 0x1106. FM_BLEND_MONO_THRESHOLD Sets RSSI threshold for mono blend (Full mono below thre shold, blend above threshold). To force stereo, set this to 0. To force mono, set this to 127. The CTS bit (and op tional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 30 dBµV. Available in: Si470x/2x, Si473x-C40 and earlier Default: 0x001E Units: dBµV Step: 1 Range: 0–127 B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 000000000 S T T H R E S H [ 6 : 0 ] Bit Name Function 15:7 Reserved Always write to 0. 6:0 STTHRESH FM Blend Stereo Threshold. RSSI threshold below which the audio output goes into a blend mode. Above this threshold the audio output is in full stereo. Specified in units of dBµV in 1 dB steps (0–127). Default is 49 dBµV. B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 000000000 M O N O T H R E S H [ 6 : 0 ] Bit Name Function 15:7 Reserved Always write to 0. 6:0 MONOTHRESH FM Blend Mono Threshold. RSSI threshold below which the audio output goes into full mono mode. Above this threshold the audio output is in blend or full stereo. Specified in units of dBµV in 1 dB steps (0–127). Default is 30 dBµV.
Rev. 1.0 91 Property 0x1107. FM_ANTENNA_INPUT Selects what type of antenna and what pin it is connec ted to. Default is 0 which means the antenna used is a headphone (long) antenna and it is connected to the FM I pin. Setting the FMTXO bit to 1 means that the antenna used is an embedded (short) antenna and it is connected to the TXO/LPI pin. Note: To assure proper tuning, the FM_TUNE_FREQ command should be issued immediately after this property is changed. Available in: Si4704/05/06/20/21 Default: 0x0000 Property 0x1108. FM_MAX_TUNE_ERROR Sets the maximum freq error allowed before setting the AFC rail indicator (AFCRL). The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 20 kHz. Note: For FMRX components 2.0 or earlier, the default is set to 30 kHz. For best seek performance, set FM_MAX_TUNE_ER- ROR to 20 kHz. Available in: All Default: 0x001E (Si473x-B20 and earlier) 0x0014 (all others) Units: kHz Step: 1 Range: 0–255 B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1 D 0 Name 000000000000000 F M T X O Bit Name Function 15:1 Reserved Always write to 0 0F M T X O Selects what type of antenna and which pin it is connected to: 0 = Use FMI pin for headphone (long) antenna 1 = Use TXO/LPI pin for embedded (short) antenna B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 00000000 F M M A X T U N E E R R [ 7 : 0 ] Bit Name Function 15:8 Reserved Always write to 0. 7:0 FMMAXTUNEERR FM Maximum Tuning Frequency Error. Maximum tuning error allowed before setting the AFC Rail Indicator ON. Specified in units of kHz. Default is 20 kHz.
92 Rev. 1.0 Property 0x1200. FM_RSQ_INT_SOURCE Configures interrupt related to Received Signal Quality metrics. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0. Available in: All Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 000000 0 BLEN- DIEN 0 MULT HIEN MULT- LIEN SNRHIEN SNRLIEN RSSIHIEN RSSILIEN Bit Name Function 15:8 Reserved Always write to 0. 7B L E N D I E N Interrupt Source Enable: Blend. Enable blend as the source of interrupt which the threshold is set by FM_R- SQ_BLEND_THRESHOLD. 6 Reserved Always write to 0. 5M U L T H I E N Interrupt Source Enable: Multipath High (Si4706-C30 and later, Si474x and Si4704/05/30/31/34/35/84/85-D50 and later only). Enable Multipath high as the source of interrupt which the threshold is set by FM_RSQ_- MULTIPATH_HI_THRESHOLD. 4M U L T L I E N Interrupt Source Enable: Multipath Low (Si4706-C30 and later, Si474x and Si4704/05/30/31/34/35/84/85-D50 and later only). Enable Multipath low as the source of interrupt which the threshold is set by FM_RSQ_- MULTIPATH_LO_THRESHOLD.
3 SNRHIEN
Interrupt Source Enable: SNR High. Enable SNR high as the source of interrupt which the threshold is set by FM_RSQ_SN- R_HI_THRESHOLD. 2S N R L I E N Interrupt Source Enable: SNR Low. Enable SNR low as the as the source of interrupt which the threshold is set by FM_R- SQ_SNR_LO_THRESHOLD.
1 RSSIHIEN
Interrupt Source Enable: RSSI High. Enable RSSI high as the source of interrupt which the threshold is set by FM_R- SQ_RSSI_HI_THRESHOLD.
0 RSSILIEN
Interrupt Source Enable: RSSI Low. Enable RSSI low as the source of interrupt which the threshold is set by FM_R- SQ_RSSI_LO_THRESHOLD.
Rev. 1.0 93 Property 0x1201. FM_RSQ_SNR_HI_THRESHOLD Sets high threshold which triggers the RSQ interrupt if the SNR is above this threshold. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 127dB. Available in: All Default: 0x007F Units: dB Step: 1 Range: 0–127 Property 0x1202. FM_RSQ_SNR_LO_THRESHOLD Sets low threshold which triggers the RSQ interrupt if the SNR is be low this threshold. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0 dB. Available in: All Default: 0x0000 Units: dB Step: 1 Range: 0–127 B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 0 0 0 0 0 0 0 0 0 SNRH[6:0] Bit Name Function 15:7 Reserved Always write to 0. 6:0 SNRH FM RSQ SNR High Threshold. Threshold which triggers the RSQ interrupt if the SNR is above this threshold. Specified in units of dB in 1 dB steps (0–127). Default is 127 dB. B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 000000000 S N R L [ 6 : 0 ] Bit Name Function 15:7 Reserved Always write to 0. 6:0 SNRL FM RSQ SNR Low Threshold. Threshold which triggers the RSQ interrupt if the SNR is below this threshold. Specified in units of dB in 1 dB steps (0–127). Default is 0 dB.
94 Rev. 1.0 Property 0x1203. FM_RSQ_RSSI_HI_THRESHOLD Sets high threshold which triggers the RSQ interrupt if the RSSI is above this threshold. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 127 dBµV. Available in: All Default: 0x007F Units: dBµV Step: 1 Range: 0–127 Property 0x1204. FM_RSQ_RSSI_LO_THRESHOLD Sets low threshold which triggers the RSQ interrupt if the RSSI is below this threshold. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0 dBµV. Available in: All Default: 0x0000 Units: dBµV Step: 1 Range: 0–127 B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 000000000 R S S I H [ 6 : 0 ] Bit Name Function 15:7 Reserved Always write to 0. 6:0 RSSIH FM RSQ RSSI High Threshold. Threshold which triggers the RSQ interrupt if the RSSI is above this threshold. Specified in units of dBµV in 1 dB steps (0–127). Default is 127 dBµV. B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 000000000 R S S I L [ 6 : 0 ] Bit Name Function 15:7 Reserved Always write to 0. 6:0 RSSIL FM RSQ RSSI Low Threshold. Threshold which triggers the RSQ interrupt if the RSSI is below this threshold. Specified in units of dBµV in 1 dB steps (0–127). Default is 0 dBµV.
Rev. 1.0 95 Property 0x1205. FM_RSQ_MULTIPATH_HI_THRESHOLD Sets the high threshold which triggers the RSQ interrupt if the Multipath level is above this threshold. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in power up mode. The value may be the threshold multipath percent (0–100), or 127 to disable the feature. Available in: Si4706-C30 and later, Si474x, Si4704/05/30/31/34/35/84/85-D50 and later Default: 0x007F Step: 1 Range: 0–127 Property 0x1206. FM_RSQ_MULTIPATH_LO_THRESHOLD Sets the low threshold which triggers the RSQ interrupt if the Multipath level is below this threshold. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in power up mode. The default is 0. Available in: Si4706-C30 and later, Si474x, Si4704/05/30/31/34/35/84/85-D50 and later Default: 0x0000 Step: 1 Range: 0–127 B i t D 1 5D 1 4D 1 3D 1 2 D 1 1 D 1 0D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 0 0 0 0 0 0 0 0 0 MULTH[6:0] Bit Name Function 15:7 Reserved Always write to 0. 6:0 MULTH FM RSQ Multipath High Threshold. Threshold which triggers the RSQ interrupt if the Multipath is above this threshold. Default is 127. B i t D 1 5 D 1 4D 1 3D 1 2D 1 1 D 1 0D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 000000 0 0 0 M U L T L [ 6 : 0 ] Bit Name Function 15:7 Reserved Always write to 0 6:0 MULTL FM RSQ Multipath Low Threshold. Threshold which triggers the RSQ interrupt if the Multipath is below this threshold. Default is 0.
96 Rev. 1.0 Property 0x1207. FM_RSQ_BLEND_THRESHOLD Sets the blend threshold for blend interrupt when boundary is crossed. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This prop erty may only be set or read when in powerup mode. The default is 1%. Available in: All except Si4749 Default: 0x0081 Units: % Step: 1 Range: 0–100 Property 0x1300. FM_SOFT_MUTE_RATE Sets the attack and decay rates when entering and leaving soft mute. Later values increase rates, and lower values decrease rates. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0x0040. Available in: Si4706/07/20/21/84/85-B20 and earlier, Si4704/05/3x-C40 and earlier Default: 64 Step: 1 Range: 1—255 B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9 D 8 D 7 D 6D 5D 4D 3D 2D 1D 0 Name 00000000 P I L O T B L E N D [ 6 : 0 ] Bit Name Function 15:8 Reserved Always write to 0. 7P I L O T Pilot Indicator. This bit has to be set to 1 (there has to be a pilot present) in order for FM_R- SQ_BLEND_THRESHOLD to trigger an interrupt. Without a pilot tone, the part is always in full mono mode and never goes into blend. 6:0 BLEND FM RSQ Blend Threshold. This is a boundary cross threshold. If the blend cross from above to below, or the other way around from below to above this threshold, it will trigger an interrupt. Specified in units of % in 1% steps (0–100). Default is 1%. B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 00000000 S M R A T E [ 7 : 0 ]
Rev. 1.0 97 Property 0x1301. FM_SOFT_MUTE_SLOPE Configures attenuation slope during soft mute in dB attenuation per dB SNR below the soft mute SNR threshold. Soft mute attenuation is the minimum of SMSLOPE x (SMTHR – SNR) and SMATTN. The recommended SMSLOPE value is CEILING(SMATTN/SMTHR) . SMATTN and SMTHR are set via the FM_SOFT_MUTE_MAX_ATTENUATION and FM_SOFT_MU TE_SNR_THRESHOLD properties. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in power up mode. The default soft mute slope pr operty setting is 2 dB/dB in supported devices. The soft mute slope is not configurable in Si4704/05/3x-B20 devices (those with FMRX component 2.0) and is 2 dB/dB. The soft mute slope is not configurable in Si4710/20-A10 devices (those with FMRX component 1.0), and is 0 dB/dB (disabled). Available in: Si4704/05/06/3x-C40 and later, Si4740/41/42/43/44/45 Default: 0x0002 Range: 0–63 Property 0x1302. FM_SOFT_MUTE_MAX_ATTENUATION Sets maximum attenuation during soft mute (dB). Set to 0 to disable soft mute. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 16 dB. Available in: All except Si4749 Default: 0x0010 Units: dB Step: 1 Range: 0–31 B i t D 1 5D 1 4D 1 3D 1 2D 1 1D 1 0D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 0000000 0 S M S L O P E [ 7 : 0 ] B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 00000000000 S M A T T N [ 4 : 0 ] Bit Name Function 15:5 Reserved Always write to 0. 4:0 SMATTN FM Soft Mute Maximum Attenuation. Set maximum attenuation during soft mute. If set to 0, then soft mute is disabled. Speci- fied in units of dB in 1 dB steps (0–31). Default is 16 dB.
98 Rev. 1.0 Property 0x1303. FM_SOFT_MUTE_SNR_THRESHOLD Sets SNR threshold to engage soft mute. Whenever the SNR for a tuned frequency drops below this threshold, the FM reception will go in so ft mute, provided soft mute max attenuat ion property is non-zero. The CTS bit (and optional interrupt) is set when it is sa fe to send the next command. This property may only be set or read when in powerup mode. The default is 4 dB. Available in: All except Si4749 Default: 0x0004 Units: dB Step: 1 Range: 0–15 Property 0x1304. FM_SOFT_MUTE_RELEASE_RATE Sets the soft mute release rate. Smaller values provide slower release and larger values provide faster release. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 8192 (approximately 8000 dB/s). Release Rate (dB/s) = RELEASE[14:0]/1.024 Available in: Si4706-C30 and later, Si4740/41/42/43/44/45, Si4704/05/30/31/34/35/84/85-D50 and later Default: 0x2000 Range: 1–32767 B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 000000000000 S M T H R [ 3 : 0 ] Bit Name Function 15:4 Reserved Always write to 0. 3:0 SMTHR FM Soft Mute SNR Threshold. Threshold which will engage soft mute if the SNR falls below this. Specified in units of dB in 1 dB steps (0–15). Default is 4 dB. B i t D 1 5D 1 4D 1 3D 1 2D 1 1D 1 0D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 0 RELEASE[14:0]
read when in powerup mode. The default is 8192 (approximately 8000 dB/s). Figure 3. Softmute Gain (dB)
100 Rev. 1.0 Property 0x1400. FM_SEEK_BAND_BOTTOM Sets the bottom of the FM band for seek. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 87.5 MHz. Available in: All Default: 0x222E Units: 10 kHz Step: 50 kHz Range: 64–108 MHz Note: For FMRX components 2.0 or earlier, range is 76–108 MHz. B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name FMSKFREQL[15:0] Bit Name Function 15:0 FMSKFREQL FM Seek Band Bottom Frequency. Selects the bottom of the FM Band during Seek. Specified in units of 10 kHz. Default is 8750 (87.5 MHz).
Rev. 1.0 101 Property 0x1401. FM_SEEK_BAND_TOP Sets the top of the FM band for seek. The CTS bit (and opti onal interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 107.9 MHz. Available in: All Default: 0x2A26 Units: 10 kHz Step: 50 kHz Range: 64–108 MHz Note: For FMRX components 2.0 or earlier, range is 76–108 MHz. Property 0x1402. FM_SEEK_FREQ_SPACING Selects frequency spacing for FM seek. There are only 3 valid values: 5, 10, and 20. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 100 kHz. Available in: All Default: 0x000A B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name FMSKFREQH[15:0] Bit Name Function 15:0 FMSKFREQH FM Seek Band Top Frequency. Selects the top of the FM Band during Seek. Specified in units of 10 kHz. Default is 10790 (107.9 MHz). B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 00000000000 S K S P A C E [ 4 : 0 ] Bit Name Function 15:5 Reserved Always write to 0. 4:0 SKSPACE FM Seek Frequency Spacing. Selects the frequency spacing during Seek function. Specified in units of 10 kHz. There are only 3 valid values: 5 (50 kHz), 10 (100 kHz), and 20 (200 kHz). Default is 10.
102 Rev. 1.0 Property 0x1403. FM_SEEK_TUNE_SNR_THRESHOLD Sets the SNR threshold for a valid FM Seek/Tune. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 3 dB. Available in: All Default: 0x0003 Units: dB Step: 1 Range: 0–127 Property 0x1404. FM_SEEK_TUNE_RSSI_THRESHOLD Sets the RSSI threshold for a valid FM Seek/Tune. The CT S bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 20 dBµV. Available in: All Default: 0x0014 Units: dBµV Step: 1 Range: 0–127 B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 0 0 0 0 0 0 0 0 0 SKSNR[6:0] Bit Name Function 15:7 Reserved Always write to 0. 6:0 SKSNR FM Seek/Tune SNR Threshold. SNR Threshold which determines if a valid channel has been found during Seek/Tune. Specified in units of dB in 1 dB steps (0–127). Default is 3 dB. B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 000000000 S K R S S I [ 6 : 0 ] Bit Name Function 15:7 Reserved Always write to 0. 6:0 SKRSSI FM Seek/Tune Received Signal Strength Threshold. RSSI threshold which determines if a valid channel has been found during seek/tune. Specified in units of dBµV in 1 dBµV steps (0–127). Default is 20 dBµV.
Rev. 1.0 103 Property 0x1500. FM_RDS_INT_SOURCE Configures interrupt related to RDS. The CTS bit (and opti onal interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0. Available in: Si4705/06, Si4721, Si4731/35/37/39, Si4741/43/45/49 Default: 0x0000 Property 0x1501. FM_RDS_INT_FIFO_COUNT Sets the minimum number of RDS groups stored in the RDS FIFO before RDSRECV is set. The maximum value is 25 for FRMX component 2.0 or later, and 14 for FMRX component 1.0. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. Default is Note: FM_RDS_INT_FIFO_COUNT is supported in FMRX component 2.0 or later. Available in: Si4705/06, Si4721, Si4731/35/37/39, Si4741/43/45/49 Default: 0x0000 Range: 0–25 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 RDSNEW- BLOCKB RDSNEW- BLOCKA 0 RDSSYNC- FOUND RDSSYN- CLOST RDSRECV Bit Name Function 15:6 Reserved Always write to 0.
5 RDSNEWBLOCKB
RDS New Block B Found (Si4706, Si474x, and Si4705/31/35/85-D50 and later only) If set, generate an interrupt when Block B data is found or subsequently changed.
4 RDSNEWBLOCKA RDS New Block A Found (Si4706,Si474x and Si4705/31/35/85-D50 and later only)
If set, generate an interrupt when Block A data is found or subsequently changed 3 Reserved Always write to 0. 2 RDSSYNCFOUND RDS Sync Found. If set, generate RDSINT when RDS gains synchronization. 1 RDSSYNCLOST RDS Sync Lost. If set, generate RDSINT when RDS loses synchronization.
0 RDSRECV
RDS Received. If set, generate RDSINT when RDS FIFO has at least FM_RDS_INT_FIFO_COUNT entries. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 RDSFIFOCNT[7:0] Bit Name Function 7:0 RDSFIFOCNT RDS FIFO Count. Minimum number of RDS groups stored in the RDS FIFO before RDSRECV is set.
104 Rev. 1.0 Property 0x1502. FM_RDS_CONFIG Configures RDS settings to enable RDS processing (R DSEN) and set RDS block error thresholds. When a RDS Group is received, all block errors must be less than or equal the associated block error threshold for the group to be stored in the RDS FIFO. If blocks with errors are pe rmitted into the FIFO, the block error information can be reviewed when the group is read using the FM_RDS_STA TUS command. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This prope rty may only be set or read when in powerup mode. The default is 0x0000. Note: FM_RDS_CONFIG is supported in FMRX component 2.0 or later. Available in: Si4705/06, Si4721, Si4731/35/37/39, Si4741/43/45/49 Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name BLETHA[1:0] BLETHB[1:0] BLETHC[1:0] BLETHD[1:0] 0 0 0 0 0 0 0 RDSEN Bit Name Function 15:14 BLETHA[1:0] Block Error Threshold BLOCKA. 0 = No errors. 1 = 1–2 bit errors detected and corrected. 2 = 3–5 bit errors detected and corrected. 3 = Uncorrectable. 13:12 BLETHB[1:0] Block Error Threshold BLOCKB. 0 = No errors. 1 = 1–2 bit errors detected and corrected. 2 = 3–5 bit errors detected and corrected. 3 = Uncorrectable. 11:10 BLETHC[1:0] Block Error Threshold BLOCKC. 0 = No errors. 1 = 1–2 bit errors detected and corrected. 2 = 3–5 bit errors detected and corrected. 3 = Uncorrectable. 9:8 BLETHD[1:0] Block Error Threshold BLOCKD. 0 = No errors. 1 = 1–2 bit errors detected and corrected. 2 = 3–5 bit errors detected and corrected. 3 = Uncorrectable.
0 RDSEN
RDS Processing Enable. 1 = RDS processing enabled.
Rev. 1.0 105 Recommended Block Error Threshold options: 2,2,2,2 = No group stored if any errors are uncorrected. 3,3,3,3 = Group stored regardless of errors. 0,0,0,0 = No group stored containing corrected or uncorrected errors. 3,2,3,3 = Group stored with corrected errors on B, regardless of errors on A, C, or D. Property 0x1503. FM_RDS_CONFIDENCE Selects the confidence level requirement for each RDS block. A higher confidence requirement will result in fewer decoder errors (% of blocks with BLE<3 that contains incorrect information) but more block errors (% of blocks with BLE=3). The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0x1111. Available in: Si4706-C30 and later, Si474x, Si4704/05/30/31/34/35/84/85-D50 and later Default: 0x1111 Property 0x1700. FM_AGC_ATTACK_RATE Sets the AGC attack rate. Larger values provide slower attack and smaller values provide faster attack. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 4 (approximately 1500 dB/s). Nominal “6000” is based on 50 source impedance and will vary with source impedance. In most systems, an exact value is not important. However, to calculate for a different source impedance, perform the following steps: 1. Drive antenna input with desired source impedance (via antenna or antenna dummy). 2. Increase RF level until AGC index changes from 0 to 1. Record last RF level with index equal 0. 3. Increase RF level until AGC index reaches 20. Record RF level with index equal 20. 4. Replace “6000” in rate equation with “(RF20 – RF0)/0.00667”. Available in: Si4740/41/42/43/44/45/49 Default: 0x0004 Step: 4 Range: 4–248 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name X X X X CONFIDENCEB[3:0] CONFIDENCEC[3:0] CONFIDENCED[3:0] Bit Name Function 11:8 CONFIDENCEB Selects decoder er ror rate threshold for Block B. 7:4 CONFIDENCEC Selects decoder er ror rate threshold for Block C. 3:0 CONFIDENCED Selects decoder er ror rate threshold for Block D. AGC Attack Rate (dB/s) 6000
106 Rev. 1.0 Note: Was property 0x4100 in FW2.B. Property 0x1701. FM_AGC_RELEASE_RATE Sets the AGC release rate. Larger valu es provide slower release and smaller values provide faster release. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 140 (approximately 43 dB/s). Nominal “6000” is based on 50 source impedance and will vary with source impedance. In most systems, an exact value is not important. However, to calculate for a different source impedance, perform the following steps: 1. Drive antenna input with desired source impedance (via antenna or antenna dummy). 2. Increase RF level until AGC index changes from 0 to 1. Record last RF level with index equal 0. 3. Increase RF level until AGC index reaches 20. Record RF level with index equal 20. 4. Replace “6000” in rate equation with “(RF20 – RF0)/0.00667”. Available in: Si4740/41/42/43/44/45/49 Default: 0x008C Step: 4 Range: 4–248 Note: Was property 0x4101 in FW2.B. Property 0x1800. FM_BLEND_RSSI_STEREO_THRESHOLD Sets RSSI threshold for stereo blend (Full stereo above threshold, blend below threshold). To force stereo, set to 0. To force mono, set to 127. The CTS bit (and optional inte rrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 49 dBμV. Available in: Si4706-C30 and later, Si4740/41/42/43/44/45, Si4704/05/30/31/34/35/84/85-D50 and later Default: 0x0031 Units: dBμV Step: 1 Range: 0–127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 ATTACK[7:0] Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 RELEASE[7:0] Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 STRTHRESH[6:0] AGC Release Rate (dB/s) 6000
Rev. 1.0 107 Property 0x1801. FM_BLEND_RSSI_MONO_THRESHOLD Sets RSSI threshold for mono blend (Full mono below thre shold, blend above threshold). To force stereo, set this to 0. To force mono, set this to 127. The CTS bit (and op tional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 30 dBμV. Available in: Si4706-C30 and later, Si4740/41/42/43/44/45, Si4704/05/30/31/34/35/84/85-D50 and later Default: 0x001E Units: dBμV Step: 1 Range: 0–127 Property 0x1802. FM_BLEND_RSSI_ATTACK_RATE Sets the stereo to mono attack rate for RSSI based ble nd. Smaller values provide slower attack and larger values provide faster attack. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in poweru p mode. The default is 4000 (approximately 16 ms). ATTACK[15:0] = 65536/time, where time is the desired transition time in ms. Available in: Si4706-C30 and later, Si4740/41/42/43/44/45, Si4704/05/30/31/34/35/84/85-D50 and later Default: 0x0FA0 Step: 1 Range: 0 (disabled), 1–32767 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 MONOTHRESH[6:0] Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name ATTACK[15:0]
values provide faster release. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in po werup mode. The default is 400 (approximately 164 ms). RELEASE[15:0] = 65536/time, where time is the desired transition time in ms. Figure 4. RSSI Blend
Rev. 1.0 109 Property 0x1804. FM_BLEND_SNR_STEREO_THRESHOLD Sets SNR threshold for stereo blend (Full stereo above threshold, blend below threshold). To force stereo, set this to 0. To force mono, set this to 127. The CTS bit (and op tional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 27 dB. Available in: Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later Default: 0x001B Units: dB Step: 1 Range: 0–127 Property 0x1805. FM_BLEND_SNR_MONO_THRESHOLD Sets SNR threshold for mono blend (Full mono below threshold, blend above threshold). To force stereo, set to 0. To force mono, set to 127. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 14 dB. Available in: Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later Default: 0x000E Units: dB Step: 1 Range: 0–127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 STRTHRESH[6:0] Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 MONOTHRESH[6:0]
110 Rev. 1.0 Property 0x1806. FM_BLEND_SNR_ATTACK_RATE Sets the stereo to mono attack rate for SNR based blend. Smaller values provide slower attack and larger values provide faster attack. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in poweru p mode. The default is 4000 (approximately 16 ms). ATTACK[15:0] = 65536/time, where time is the desired transition time in ms. Available in: Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later Default: 0x0FA0 Step: 1 Range: 0 (disabled), 1–32767 Property 0x1807. FM_BLEND_SNR_RELEASE_RATE Sets the mono to stereo release rate for SNR based bl end. Smaller values provide slower release and larger values provide faster release. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in po werup mode. The default is 400 (approximately 164 ms). RELEASE[15:0] = 65536/time, where time is the desired transition time in ms. Available in: Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later Default: 0x0190 Step: 1 Range: 0 (disabled), 1–32767 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name ATTACK[15:0] Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name RELEASE[15:0]
Figure 5. SNR Blend command. This property may only be set or read when in powerup mode. The default is 20.
112 Rev. 1.0 Property 0x1809. FM_BLEND_MULTIPATH_MONO_THRESHOLD Sets Multipath threshold for mono blend (Full mono above threshold, blend below threshold). To force stereo, set to 100. To force mono, set to 0. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 60. Available in: Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later Default: 0x003C Step: 1 Range: 0–100 Property 0x180A. FM_BLEND_MULTIPATH_ATTACK_RATE Sets the stereo to mono attack rate for Multipath based blend. Smaller values provid e slower attack and larger values provide faster attack. The CTS bit (and optional inte rrupt) is set when it is safe to send the next command. This property may only be set or read when in po werup mode. The default is 4000 (approximately 16 ms). ATTACK[15:0] = 65536/time, where time is the desired transition time in ms. Available in: Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later Default: 0x0FA0 Step: 1 Range: 0 (disabled), 1–32767 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 MONOTHRESH[6:0] Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name ATTACK[15:0]
values provide faster release. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powe rup mode. The default is 40 (approximately 1.64 s). RELEASE[15:0] = 65536/time, where time is the desired transition time in ms. Figure 6. MP Blend
114 Rev. 1.0 Property 0x180C. FM_BLEND_MAX_STEREO_SEPARATION Sets the maximum allowable stereo separation. The default is 0, disabling the feature so that there is no limit on stereo separation. Available in: Si474x Default: 0x0000 B i t D 1 5D 1 4D 1 3D 1 2D 1 1D 1 0D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 0 0 0 0 0 0 0000000 M A X _ S E P [ 2 : 0 ] Bit Name Function 15:3 Reserved Always write to 0. 2:0 MAX_SEP Maximum Stereo Separation. 0 = disabled (default) 1 = 12 dB of separation, maximum 2 = 15 dB of separation, maximum 3 = 18 dB of separation, maximum 4 = 21 dB of separation, maximum 5 = 24 dB of separation, maximum 6 = 27 dB of separation, maximum 7 = 30 dB of separation, maximum
Rev. 1.0 115 Property 0x1900. FM_NB_DETECT_THRESHOLD Sets the threshold for detecting impulses in dB above the noise floor. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This prop erty may only be set or read when in powerup mode. The default is 16 dB. To disable the noise blanker featur e, set the FM_NB_DETECT_THRESHOLD property (0x1900) to 0. Available in: Si4742/43/44/45 Default: 0x0010 Range: 0–90 Note: Was property 0x4106 in FW2.B. Property 0x1901. FM_NB_INTERVAL Interval in micro-seconds that original samples are re placed by interpolated clean samples. The CTS bit (and optional interrupt) is set when it is sa fe to send the next command. This property may only be set or read when in powerup mode. The default is 24 µs. Available in: Si4742/43/44/45 Default: 0x0018 Range: 8–48 Note: Was property 0x4107 in FW2.B. Property 0x1902. FM_NB_RATE Noise blanking rate in 100 Hz units. The CTS bit (and op tional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 64 (6400 Hz). Available in: Si4742/43/44/45 Default: 0x0040 Range: 1–64 Note: Was property 0x4108 in FW2.B. B i t D 1 5D 1 4D 1 3D 1 2D 1 1D 1 0D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name NB_DETECT_THRESHOLD [15:0] B i t D 1 5D 1 4D 1 3D 1 2D 1 1D 1 0D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name NB_INTERVAL [15:0] B i t D 1 5D 1 4D 1 3D 1 2D 1 1D 1 0D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name NB_RATE [15:0]
116 Rev. 1.0 Property 0x1903. FM_NB_IIR_FILTER Sets the bandwidth of the noise floor estimator. The CTS bi t (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 300 (465 Hz). Bandwidth (Hz) = NB_IIR_FILTER[15:0] x 1.55 Available in: Si4742/43/44/45 Default: 0x012C Range: 300–1600 Note: Was property 0x4109 in FW2.B. Property 0x1904. FM_NB_DELAY Delay in micro-seconds before applying impulse blanking to the original samples. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 170 µs. Available in: Si4742/43/44/45 Default: 0x00AA Range: 125–219 Note: Was property 0x410A in FW2.B. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name NB_IIR_FILTER [15:0] Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name NB_DELAY [15:0]
Figure 7. FM Noise Blanker FM_NB_RATE: sets maximum repeat rate NB is allowed to fire.
118 Rev. 1.0 Property 0x1A00. FM_HICUT_SNR_HIGH_THRESHOLD Sets the SNR level at which hi-cut begins to band limit. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read in POWERUP mode. The default is 24 dB. Available in: Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later Default: 0x0018 Range: 0–127 Note: Was property 0x180C in FW2.B. Property 0x1A01. FM_HICUT_SNR_LOW_THRESHOLD Sets the SNR level at which hi-cut reaches maximum band limiting. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property ma y only be set or read in POWERUP mode. The default is 15 dB. Available in: Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later Default: 0x000F Range: 0–127 Note: Was property 0x180D in FW2.B. Property 0x1A02. FM_HICUT_ATTACK_RATE Sets the rate at which hi-cut lowers the transition frequen cy. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read in POWERUP mode. The default is 20000 (approximately 3 ms). ATTACK[15:0] = 65536/time, were time is the desired transition time in ms. Available in: Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later Default: 0x4E20 Range: 0 (disabled), 1–32767 Note: Was property 0x180E in FW2.B. B i t D 1 5D 1 4D 1 3D 1 2D 1 1D 1 0D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 0000000 00 S N R _ H I G H [ 6 : 0 ] B i t D 1 5D 1 4D 1 3D 1 2D 1 1D 1 0D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 0000000 00 S N R _ L O W [ 6 : 0 ] B i t D 1 5D 1 4D 1 3D 1 2D 1 1D 1 0D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name ATTACK[15:0]
Rev. 1.0 119 Property 0x1A03. FM_HICUT_RELEASE_RATE Sets the rate at which hi-cut increases the transition frequency. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read in POWERUP mode. The default is 20 (approximately 3.3 s). RELEASE[15:0] = 65536/time, were time is the desired transition time in ms. Available in: Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later Default: 0x0014 Range: 0 (disabled), 1–32767 Note: Was property 0x180F in FW2.B. Property 0x1A04. FM_HICUT_MULTIPATH_TRIGGER_THRESHOLD Sets the MULTIPATH level at which hi-cut begins to band limit. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read in POWERUP mode. The default is 20%. Available in: Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later Default: 0x0014 Range: 0–100 Note: Was property 0x1810 in FW2.B. Property 0x1A05. FM_HICUT_MULTIPATH_END_THRESHOLD Sets the MULTIPATH level at which hi-cut reaches maximum band limiting. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This pr operty may only be set or read in POWERUP mode. The default is 60%. Available in: Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later Default: 0x003C Range: 0–100 Note: Was property 0x1811 in FW2.B. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name RELEASE[15:0] Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 00 00 0 0 000 M U L T _ T R I G G E R [ 6 : 0 ] Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0000 0 0 000 M U L T _ E N D [ 6 : 0 ]
120 Rev. 1.0 Property 0x1A06. FM_HICUT_CUTOFF_FREQUENCY Sets the maximum band limit frequency for hi-cut and also sets the maximum audio frequency. The CTS bit (optional interrupt) is set when it is safe to send the next command. This property may only be set or read in POWERUP mode. The default is 0(disabled). Available in: Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later Default 0x0000 Range: 0–7 (maximum band limit frequency for Hi-Cut) 0–7 (maximum audio frequency) Note: Was property 0x1812 in FW2.B. The maximum audio frequency was not programmable in FW2.B. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0000000 0 0 MAXIMUM AUDIO FREQ[2:0] 0 FREQUENCY[2:0] Bit Name Function 6:4 MAXIMUM AUDIO FREQUENCY[2:0] Maximum Audio Frequency. 0 = Maximum Audio transition frequency =Max Audio BW 1 = Maximum Audio transition frequency = 2 kHz 2 = Maximum Audio transition frequency = 3 kHz 3 = Maximum Audio transition frequency = 4 kHz 4 = Maximum Audio transition frequency = 5 kHz 5 = Maximum Audio transition frequency = 6 kHz 6 = Maximum Audio transition frequency = 8 kHz 7 = Maximum Audio transition frequency = 11 kHz 2:0 FREQUENCY[2:0] Frequency. 0 = Hi-Cut disabled 1 = Hi-cut transition frequency = 2 kHz 2 = Hi-cut transition frequency = 3 kHz 3 = Hi-cut transition frequency = 4 kHz 4 = Hi-cut transition frequency = 5 kHz 5 = Hi-cut transition frequency = 6 kHz 6 = Hi-cut transition frequency = 8 kHz 7 = Hi-cut transition frequency = 11 kHz
Rev. 1.0 123 Property 0x4000. RX_VOLUME Sets the audio output volume. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 63. Available in: All except Si4749 Default: 0x003F Step: 1 Range: 0–63 Property 0x4001. RX_HARD_MUTE Mutes the audio output. L and R audio outputs may be muted independently. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This prope rty may only be set or read when in powerup mode. The default is unmute (0x0000). Available in: All except Si4749 Default: 0x0000 B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 0000000000 V O L [ 5 : 0 ] Bit Name Function 15:6 Reserved Always write to 0. 5:0 VOL Output Volume. Sets the output volume level, 63 max, 0 min. Default is 63. B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2 D 1 D 0 Name 000000 0 0 000000 L M U T E R M U T E Bit Name Function 15:2 Reserved Always write to 0. 1 LMUTE Mutes L Audio Output. 0 RMUTE Mutes R Audio Output.
Table 12. AM/LW/SW Receiver Command Summary file, see "7.2. Powerup from a Component Patch" on page 216.
Table 13. AM/SW/LW Receiver Property Summary is 31130 to 34406 Hz, or 0 to disable the AFC. (kHz). The default bandwidth is 2 kHz.
- The 1 kHz option, 1.8 kHz option, and 100 Hz high-pass Line Noise Rejection filter are supported on Si473x-C40 and later
devices and Si474x devices (AM_SW_LW component 3.0 or later).
- The 2.5 kHz option is supported on Si473x-C40 and later devices (AM_SW_LW component 5.0 or later).
- Component 1.0 incorrectly reports 0x06B9 (1721 kHz) as default for AM_SEEK_BAND_TOP. After POWER_UP command is
complete, set AM_SEEK_BAND_TOP to 0x06AE (1710 kHz) using the SET_PROPERTY command.
Sets maximum attenuation during soft mute (dB). Set to 0 to disable soft mute. Default is 8 dB. Table 13. AM/SW/LW Receiver Property Summary (Continued)
- The 1 kHz option, 1.8 kHz option, and 100 Hz high-pass Line Noise Rejection filter are supported on Si473x-C40 and later
devices and Si474x devices (AM_SW_LW component 3.0 or later).
- The 2.5 kHz option is supported on Si473x-C40 and later devices (AM_SW_LW component 5.0 or later).
- Component 1.0 incorrectly reports 0x06B9 (1721 kHz) as default for AM_SEEK_BAND_TOP. After POWER_UP command is
complete, set AM_SEEK_BAND_TOP to 0x06AE (1710 kHz) using the SET_PROPERTY command.
detector must be exceeded before decreasing gain. Default value is 4 (approximately 1400 dB/s). 0x3903 AM_NB_IIR_FILTER Sets the bandwidth of the noise floor estimator.
- The 1 kHz option, 1.8 kHz option, and 100 Hz high-pass Line Noise Rejection filter are supported on Si473x-C40 and later
devices and Si474x devices (AM_SW_LW component 3.0 or later).
- The 2.5 kHz option is supported on Si473x-C40 and later devices (AM_SW_LW component 5.0 or later).
- Component 1.0 incorrectly reports 0x06B9 (1721 kHz) as default for AM_SEEK_BAND_TOP. After POWER_UP command is
complete, set AM_SEEK_BAND_TOP to 0x06AE (1710 kHz) using the SET_PROPERTY command.
Table 14. Status Response for the AM/SW/LW Receiver 0 = Wait before sending next command. 1 = Clear to send next command. 5:4 Reserved Values may vary. Received Signal Quality Interrupt. 0 = Received Signal Quality measurement has not been triggered. 1 = Received Signal Quality measurement has been triggered. 2:1 Reserved Values may vary. Seek/Tune Complete Interrupt. 0 = Tune complete has not been triggered. 1 = Tune complete has been triggered.
Rev. 1.0 129 5.3.1. AM/SW/LW Receiver Commands Command 0x01. POWER_UP Initiates the boot process to move the device from powerdown to powerup mode. The boot can occur from internal device memory or a system controller downloaded patch. To confirm that the patch is compatible with the internal device library revision, the library revision should be confirmed by issuing the POWER_UP command with FUNC = 15 (query library ID). The device returns the resp onse, including the library revision, and then moves into powerdown mode. The device can then be placed in powerup mode by issuing the POWER_UP command with FUNC = 1 (AM/SW/LW Receive) and the patch may be ap plied. See Section "7.2. Powerup from a Component Patch" on page 216 for more information. The POWER_UP command configures the state of ROUT (pin 13) and LOUT (pin 14) for analog audio mode and GPO2/INT (pin 18) for interrupt operation. For the Si4731/ 35/37, the POWER_UP command also configures the state of GPO3/DCLK (pin 17), DFS (pin 16), and DOUT (pin 15) for digital audio mode. The command configures GPO2/INT interrupts (GPO2OEN) and CTS interrupts (CTSIEN). If both are enabled, GPO2/INT is driven high during normal operation and low for a minimum of 1 µs duri ng the interrupt. The CTSIEN bit is duplicated in the GPO_IEN property. The command is complete when the CTS bit (and optional interrupt) is set. Note: To change function (e.g. AM/SW/LW RX to FM RX), i ssue POWER_DOWN command to stop current function; then, issue POWER_UP to start new function. Note: Delay at least 500 ms between powerup command and first tu ne command to wait for the oscillator to stabilize if XOSCEN is set and crystal is used as the RCLK. Available in: All Command Arguments: Two Response Bytes: None (FUNC = 1), Seven (FUNC = 15) Command B i t D 7D 6D 5 D 4 D 3 D 2D 1D 0 CMD 000 0 0 001 ARG1 CTSIEN GPO2OEN PATCH XOSCEN FUNC[3:0] ARG2 OPMODE[7:0] ARG Bit Name Function 1 7 CTSIEN CTS Interrupt Enable. 0 = CTS interrupt disabled. 1 = CTS interrupt enabled. 1 6 GPO2OEN GPO2 Output Enable. 0 = GPO2 output disabled (Hi-Z). 1 = GPO2 output enabled. Patch Enable. 0 = Boot normally 1 = Copy NVM to RAM, but do not boot. After CTS has been set, RAM may be patched.
130 Rev. 1.0 Response (to FUNC = 1, AM Receive) Response (to FUNC = 15, Query Library ID) 1 4 XOSCEN Crystal Oscillator Enable. 0 = Use external RCLK (crystal oscillator disabled). 1 = Use crystal oscillator (RCLK and GPO3/DCLK with external 32.768 kHz crystal and OPMODE = 00000101). See Si473x Data Sheet Application Schematic for external BOM details. 1 3:0 FUNC[3:0] Function. 0=R e s e r v e d . 1 = AM/SW/LW Receive. 2–14 = Reserved. 15 = Query Library ID. 2 7:0 OPMODE[7:0] Application Setting 00000101 = Analog audio outputs (LOUT/ROUT). 00001011 = Digital audio output (DCLK, LOUT/DFS, ROUT/DIO) 10110000 = Digital audio outputs (DCLK, DFS, DIO) (Si4731/35/37 only with XOSCEN = 0). 10110101 = Analog and digital audio outputs (LOUT/ROUT and DCLK, DFS, DIO) (Si4731/35/37 only with XOSCEN = 0). B i t D 7D 6D 5D 4D 3D 2D 1D 0 STATUS CTS ERR X X RSQINT X X STCINT Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT X X STCINT RESP1 PN[7:0] RESP2 FWMAJOR[7:0] RESP3 FWMINOR[7:0] RESP4 RESERVED[7:0] RESP5 RESERVED[7:0] RESP6 CHIPREV[7:0] RESP7 LIBRARYID[7:0] RESP Bit Name Function 1 7:0 PN[7:0] Final 2 digits of part number (HEX). 2 7:0 FWMAJOR[7:0] Firmware Major Revision (ASCII). 3 7:0 FWMINOR[7:0] Firmware Minor Revision (ASCII). 4 7:0 RESERVED[7:0] Reserved, various values. 5 7:0 RESERVED[7:0] Reserved, various values. 6 7:0 CHIPREV[7:0] Chip Revision (ASCII). 7 7:0 LIBRARYID[7:0] Library Revision (HEX). ARG Bit Name Function
Rev. 1.0 131 Command 0x10. GET_REV Returns the part number, chip revision, firmware revision, patch revision and component revision numbers. The command is complete when the CTS bit (and optional inte rrupt) is set. This command may only be sent when in powerup mode. Available in: All Command arguments: None Response bytes: Eight Command Response B i t D 7D 6D 5 D 4 D 3 D 2 D 1 D 0 CMD 000 1 0 0 0 0 B i t D 7D 6D 5D 4D 3D 2D 1D 0 STATUS CTS ERR X X RSQINT X X STCINT RESP1 PN[7:0] RESP2 FWMAJOR[7:0] RESP3 FWMINOR[7:0] RESP4 PATCHH[7:0] RESP5 PATCHL[7:0] RESP6 CMPMAJOR[7:0] RESP7 CMPMINOR[7:0] RESP8 CHIPREV[7:0] RESP Bit Name Function 1 7:0 PN[7:0] Final 2 digits of Part Number (HEX). 2 7:0 FWMAJOR[7:0] Firmware Major Revision (ASCII). 3 7:0 FWMINOR[7:0] Firmware Minor Revision (ASCII). 4 7:0 PATCH H[7:0] Patch ID High Byte (HEX). 5 7:0 PATCH L[7:0] Patch ID Low Byte (HEX). 6 7:0 CMPMAJOR[7:0] Component Major Revision (ASCII). 7 7:0 CMPMINOR[7:0] Component Minor Revision (ASCII). 8 7:0 CHIPREV[7:0] Chip Revision (ASCII).
132 Rev. 1.0 Command 0x11. POWER_DOWN Moves the device from powerup to powerdown mode. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Note that only the POWER_UP command is accepted in powerdown mode. If the system controller writes a command other than POWER_UP when in powerdown mode, the device does not respond. The device will only respond when a POWER_UP command is written. GPO pins are powered down and not active during this state. For optimal power down current, GPO2 must be either internally driven low through GPIO_CTL command or externally driven low. Note: In AMRX component 1.0, a reset is required when the system controller writes a command other than POWER_UP when in powerdown mode. Note: The following describes the state of all the pins when in powerdown mode: GPIO1, GPIO2, GPIO3 = 0 ROUT, LOUT, DOUT, DFS = HiZ Available in: All Command arguments: None Response bytes: None Command Response B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 00010001 B i t D 7D 6D 5D 4D 3D 2D 1D 0 STATUS CTS ERR X X RSQINT X X STCINT
Rev. 1.0 133 Command 0x12. SET_PROPERTY Sets a property shown in Table 13, “AM/SW/LW Receiv er Property Summary,” on page 125. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. See Figure 29, “CTS and SET_PROPERTY Command Complete tCOMP Timing Model,” on page 226 and Table 47, “Command Timing Parameters for the AM Receiver,” on page 229. Available in: All Command Arguments: Five Response bytes: None Command Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 00 0 1 0 0 1 0 ARG1 00 0 0 0 0 0 0 ARG2 PROPH[7:0] ARG3 PROPL[7:0] ARG4 PROPDH[7:0] ARG5 PROPDL[7:0] ARG Bit Name Function 1 7:0 Reserved Always write to 0. 27 : 0 P R O P H[7:0] Property High Byte. This byte in combination with PROPL is used to specify the property to 37 : 0 P R O P L[7:0] Property Low Byte. This byte in combination with PROPH is used to specify the property to 47 : 0 P R O P D H[7:0] Property Value High Byte. This byte in combination with PROPDL is used to set the property value. See Section "5.3.2. AM/SW/LW Receiver Properties" on page 146. 57 : 0 P R O P D L[7:0] Property Value Low Byte. This byte in combination with PROPDH is used to set the property value. See Section "5.3.2. AM/SW/LW Receiver Properties" on page 146.
134 Rev. 1.0 Command 0x13. GET_PROPERTY Gets a property shown in Table 13, “AM/SW/LW Receiv er Property Summary,” on page 125. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Available in: All Command arguments: Three Response bytes: Three Command Response B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 00010011 ARG1 00000000 ARG2 PROPH[7:0] ARG3 PROPL[7:0] ARG Bit Name Function 1 7:0 Reserved Always write to 0. 27 : 0 P R O P H[7:0] Property High Byte. This byte in combination with PROPL is used to specify the property to get. 37 : 0 P R O P L[7:0] Property Low Byte. This byte in combination with PROPH is used to specify the property to get. B i tD 7D 6D 5D 4D 3D 2D 1D 0 STATUS CTS ERR X X RSQINT X X STCINT RESP1 00000000 RESP2 PROPDH[7:0] RESP3 PROPDL[7:0] RESP Bit Name Function 1 7:0 Reserved Alwa ys returns 0. 27 : 0 P R O P D H[7:0] Property Value High Byte. This byte in combination with PROPDL represents the requested property value. 37 : 0 P R O P D L[7:0] Property Value High Byte. This byte in combination with PROPDH represents the requested property value.
Rev. 1.0 135 Command 0x14. GET_INT_STATUS Updates bits 6:0 of the status byte. This command shou ld be called after any command that sets the STCINT or RSQINT bits. When polling this command should be periodically called to monitor the STATUS byte, and when using interrupts, this command should be called after the in terrupt is set to update the STATUS byte. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be set when in powerup mode. Available in: All Command arguments: None Response bytes: None Command Response Command 0x40. AM_TUNE_FREQ Tunes the AM/SW/LW receive to a frequency between 149 and 23 MHz in 1 kHz steps. In AM only mode, the valid frequency is between 520 and 1710 kHz in 1 kHz steps. The CTS bit (and optional interrupt) is set when it is safe to send the next command. The ERR bit (and optional interrupt) is set if an invalid argument is sent. Note that only a single interrupt occurs if both the CTS and ERR bits are set. The optional STC interrupt is set when the command completes. The STCINT bit is set only after the GET_INT_STATUS command is called. This command may only be sent when in powerup mode. The command clears the STC bit if it is already set. See Figure 28, “CTS and STC Timing Model,” on page 226 and Table 47, “Command Timing Parameters for the AM Receiver,” on page 229. AM: LO frequency is 45 kHz above RF for RF frequencies < 1000 kHz and 45 kHz below RF for RF frequencies > 1000 kHz. For example, LO frequency is 945 kHz when tuning to 900 kHz. Note: FAST bit is supported in Si473x-C40 and later devices and Si474x devices (AMRX component 3.0 or later). ANTCAP bits are supported in AMRX component 2.0 or later (all devices except Si4730-A10). Available in: All Command arguments: Five Response bytes: None Command B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 00010100 B i tD 7D 6D 5D 4D 3D 2D 1D 0 STATUS CTS ERR X X RSQINT X X STCINT B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 01000000 ARG1 0000000 F A S T ARG2 FREQH[7:0]
136 Rev. 1.0 Response ARG3 FREQL[7:0] ARG4 ANTCAPH[15:8] ARG5 ANTCAPL[7:0] ARG Bit Name Function 1 7:1 Reserved Always write to 0. 1 0 FAST FAST Tuning. If set, executes fast and invalidated tune. The tune status will not be accurate. 27 : 0 FREQH [7:0] Tune Frequency High Byte. This byte in combination with FREQL selects the tune frequency in kHz. In AM/SW/LW mode, the valid range is from 149 to 23000 (149 kHz–23 MHz). In AM only mode the valid range is from 520 to 1710 (520–1710 kHz). 37 : 0 FREQ L [7:0] Tune Frequency Low Byte. This byte in combination with FREQH selects the tune frequency in kHz. In AM/SW/LW mode, the valid range is from 149 to 23000 (149 kHz–23 MHz). In AM only mode the valid range is from 520 to 1710 (520–1710 kHz). 41 5 : 8 ANTCAP H [15:8] Antenna Tuning Capacitor High Byte. This byte in combination with ANTCAPL selects the tuning capacitor value. If both bytes are set to zero, the tuning capacitor value is selected automatically. If the value is set to anything other than 0, the tuning capacitance is manually set as 95 fF x ANTCAP + 7 pF. ANTCAP manual range is 1–6143. Automatic capacitor tuning is recom- mended. Note: In SW mode, ANTCAPH[15:8] needs to be set to 0 and ANTCAPL[7:0] needs to be set to 1. 57 : 0 ANTCAPL [7:0] Antenna Tuning Capacitor Low Byte. This byte in combination with ANTCAPH selects the tuning capacitor value. If both bytes are set to zero, the tuning capacitor value is selected automatically. If the value is set to anything other than 0, the tuning capacitance is manually set as 95 fF x ANTCAP + 7 pF. ANTCAP manual range is 1–6143. Automatic capacitor tuning is recommended. Note: In SW mode, ANTCAPH[15:8] needs to be set to 0 and ANTCAPL[7:0] needs to be set to 1. Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT X X STCINT
Rev. 1.0 137 Command 0x41. AM_SEEK_START Initiates a seek for a channel that meets the RSSI and SNR criteria for AM. Clears any pending STCINT or RSQINT interrupt status. RSQINT is only cleared by the RSQ status command when the INTACK bit is set. The CTS bit (and optional interrupt) is set when it is safe to send the next command. The ERR bit (and optional interrupt) is set if an invalid argument is sent. Note that only a single interrupt occurs if both the CTS and ERR bits are set. The optional STC interrupt is set when the command completes. The STCINT bit is set only after the GET_INT_STATUS command is called. This command ma y only be sent when in powerup mode. The command clears the STCINT bit if it is already set. See Figure 28, “CTS and STC Timing Model,” on page 226 and Table 47, “Command Timing Parameters for the AM Receiver,” on page 229. Note: ANTCAP bits are supported in AMRX component 2.1 or later. Available in: All Command arguments: Five Response bytes: None Command B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 01000001 ARG1 0 0 0 0 SEEKUP WRAP 0 0 ARG2 00000000 ARG3 00000000 ARG4 ANTCAPH[15:8] ARG5 ANTCAPL[7:0]
138 Rev. 1.0 Response ARG Bit Name Function 1 7:4 Reserved Always write to 0. 1 3 SEEKUP Seek Up/Down. Determines the direction of the search, either UP = 1, or DOWN = 0. Wrap/Halt. Determines whether the seek should Wrap = 1, or Halt = 0 when it hits the band limit. 1 1:0 Reserved Always write to 0. 2 7:0 Reserved Always write to 0. 3 7:0 Reserved Always write to 0. 4 15:8 ANTCAP H[15:8] Antenna Tuning Capacitor High Byte. This byte in combination with ANTCAPL selects the tuning capacitor value. If both bytes are set to zero, the tuning capacitor value is selected automati- cally. If the value is set to anything other than 0, the tuning capacitance is manually set as 95 fF x ANTCAP + 7 pF. ANTCAP manual range is 1–6143. Automatic capacitor tuning is recommended. Note: In SW mode, ANTCAPH[15:8] needs to be set to 0 and ANTCAPL[7:0] needs to be set to 1. 5 7:0 ANTCAP L[7:0] Antenna Tuning Capacitor Low Byte. This byte in combination with ANTCAPH selects the tuning capacitor value. If both bytes are set to zero, the tuning capacitor value is selected automati- cally. If the value is set to anything other than 0, the tuning capacitance is manually set as 95 fF x ANTCAP + 7 pF. ANTCAP manual range is 1–6143. Automatic capacitor tuning is recommended. Note: In SW mode, ANTCAPH[15:8] needs to be set to 0 and ANTCAPL[7:0] needs to be set to 1. Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT X X STCINT
Rev. 1.0 139 Command 0x42. AM_TUNE_STATUS Returns the status of AM_TUNE_F REQ or AM_SEEK_START commands. Th e commands returns the current frequency, RSSI, SNR, and the antenna tuning capaci tance value (0–6143). The command clears the STCINT interrupt bit when INTACK bit of ARG1 is set. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Note: AFCRL bit does not work properly on AMRX component 2.1 or earlier. Available in: All Command arguments: One Response bytes: Seven Command Response B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 01000010 ARG1 000000 C A N C E L I N T A C K ARG Bit Name Function 1 7:2 Reserved Always write to 0. 11 C A N C E L Cancel seek. If set, aborts a seek currently in progress. 10 I N T A C K Seek/Tune Interrupt Clear. If set, clears the seek/tune complete interrupt status indicator. B i t D 7 D 6D 5D 4 D 3 D 2 D 1 D 0 STATUS CTS ERR X X RSQINT X X STCINT RESP1 BLTF X X X X X AFCRL VALID RESP2 READFREQH[7:0] RESP3 READFREQL[7:0] RESP4 RSSI[7:0] RESP5 SNR[7:0] RESP6 READANTCAPH [15:8] RESP7 READANTCAPL [7:0]
140 Rev. 1.0 RESP Bit Name Function Band Limit. Reports if a seek hit the band limit (WRAP = 0 in AM_START_SEEK) or wrapped to the original frequency (WRAP = 1). 1 6:2 Reserved Always returns 0. 1 1 AFCRL AFC Rail Indicator. Set if the AFC rails. Valid Channel. Set if the channel is currently valid and would have been found during a seek. 2 7:0 READFREQ H[7:0] Read Frequency High Byte. This byte in combination with READFREQL returns frequency being tuned (kHz). 3 7:0 READFREQ L[7:0] Read Frequency Low Byte. This byte in combination with READFREQH returns frequency being tuned (kHz). 4 7:0 RSSI[7:0] Received Signal Strength Indicator. This byte contains the receive signal strength when tune is completed (dBµV). 5 7:0 SNR[7:0] SNR. This byte contains the SNR metric when tune is completed (dB). 6 7:0 READANTCAP H [15:8] Read Antenna Tuning Capacitor High Byte. This byte in combination with READANTCAPL returns the current antenna tuning capacitor value. The tuning capacitance is 95 fF x READANTCAP + 7p F . 7 7:0 READANTCAP L [7:0] Read Antenna Tuning Capacitor Low Byte. This byte in combination with READANTCAPH returns the current antenna tuning capacitor value. The tuning capacitance is 95 fF x READANTCAP + 7p F .
Rev. 1.0 141 Command 0x43. AM_RSQ_STATUS Returns status information about the received signal quality. The commands returns RSSI and SNR. It also indicates valid channel (VALID), soft mute engagement (SMUTE), and AFC rail status (AFCRL). This command can be used to check if the received signal is above th e RSSI high threshold as repo rted by RSSIHINT, or below the RSSI low threshold as reported by RSSILINT. It can also be used to check if the signal is above the SNR high threshold as reported by SNRHINT, or below the SNR low threshold as reported by SNRLINT. The command clears the RSQINT, SNRHINT, SNRLINT, RSSIHINT, and RSSILINT interrupt bits when INTACK bit of ARG1 is set. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Note: AFCRL bit does not work properly on AMRX component 2.1 or earlier. Available in: All Command arguments: One Response bytes: Five Command Response B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 01000011 ARG1 0000000 I N T A C K ARG Bit Name Function 10I N T A C K Interrupt Acknowledge. 0 = Interrupt status preserved. 1 = Clears RSQINT, SNRHINT, SNRLINT, RSSIHINT, RSSILINT Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT X X STCINT RESP1 X X X X SNRHINT SNRLINT RSSI- HINT RSSIILINT RESP2 X X X X SMUTE X AFCRL VALID RESP3 XX X X X X X X RESP4 RSSI[7:0] RESP5 SNR[7:0]
142 Rev. 1.0 Command 0x47. AM_AGC_STATUS Returns the AM AGC setting of the device. The command returns whether the AGC is enabled or disabled and it returns the gain index. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in power up mode. Available in: All Command arguments: None Response bytes: Two Command Response RESP Bit Name Function 1 3 SNRHINT SNR Detect High. 0 = Received SNR has not exceeded above SNR high threshold. 1 = Received SNR has exceeded above SNR high threshold. 1 2 SNRLINT SNR Detect Low. 0 = Received SNR has not exceeded below SNR low threshold. 1 = Received SNR has exceeded below SNR low threshold. 1 1 RSSIHINT RSSI Detect High. 0 = RSSI has not exceeded above RSSI high threshold. 1 = RSSI has exceeded above RSSI high threshold. 1 0 RSSILINT RSSI Detect Low. 0 = RSSI has not exceeded below RSSI low threshold. 1 = RSSI has exceeded below RSSI low threshold. 23 S M U T E Soft Mute Indicator. Indicates soft mute is engaged. 2 1 AFCRL AFC Rail Indicator. Set if the AFC rails.
20 V A L I D
Valid Channel. Set if the channel is currently valid and would have been found during a seek. 4 7:0 RSSI[7:0] Received Signal Strength Indicator. Contains the current receive signal strength (dBµV). 57 : 0 S N R [ 7 : 0 ] SNR. Contains the current SNR metric (dB). B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 01000111 B i tD 7D 6D 5D 4D 3 D 2 D 1D 0 STATUS CTS ERR X X RSQINT X X STCINT RESP1 XXXXXX X A M A G C D I S RESP2 AMAGCNDX[7:0]
Rev. 1.0 143 Command 0x48. AM_AGC_OVERRIDE Overrides the AM AGC setting by disabling the AGC and forcing the gain index that ranges between 0 (minimum attenuation) and 37+ATTN_BACKUP (maximum attenuation). The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in power up mode. Available in: All Command arguments: Two Response bytes: None Command Response RESP Bit Name Function 1 0 AMAGCDIS AM AGC Disable This bit indicates if the AGC is enabled or disabled. 0 = AGC enabled. 1 = AGC disabled. 2 7:0 AMAGCNDX AM AGC Index This byte reports the current AGC gain index. 0 = Minimum attenuation (max gain) 1 – 36+ATTN_BACKUP = Intermediate attenuation 37+ATTN_BACKUP = Maximum attenuation (min gain) Note: The max index is subject to change. See Property 0x3705 AM_FRONTEND_AGC_CONTROL for details on ATTN_BACKUP. B i t D 7D 6D 5D 4D 3D 2D 1 D 0 CMD 0100100 0 ARG1 0000000 A M A G C D I S ARG2 AMAGCNDX[7:0] ARG Bit Name Function 1 0 AMAGCDIS AM AGC Disable This bit selects whether the AGC is enabled or disabled. 0 = AGC enabled. 1 = AGC disabled. 2 7:0 AMAGCNDX AM AGC Index If AMAGCDIS = 1, this byte forces the AGC gain index. 0 = Minimum attenuation (max gain) 1 – 36+ATTN_BACKUP = Intermediate attenuation 37+ATTN_BACKUP = Maximum attenuation (min gain) *Note: The max index is subject to change. See Property 0x3705 AM_FRONTEND_AGC_CONTROL for details on ATTN_BACKUP. B i tD 7D 6D 5D 4D 3 D 2 D 1D 0 STATUS CTS ERR X X RSQINT X X STCINT
144 Rev. 1.0 Command 0x80. GPIO_CTL Enables output for GPO1, 2, and 3. GPO1, 2, and 3 can be configured for output (Hi-Z or active drive) by setting the GPO1OEN, GPO2OEN, and GPO3OEN bit. The state (h igh or low) of GPO1, 2, and 3 is set with the GPIO_SET command. To avoid excessive current consumption due to oscillation, GPO pins should not be left in a high impedance state. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. The default is all GPO pins set for high impedance. Notes: 1. GPIO_CTL is supported in AM_SW_LW component 2.0 or later. 2. The use of GPO2 as an interrupt pin and/or the use of GPO3 as DCLK digital clock input will override this GPIO_CTL function for GPO2 and/or GPO3 respectively. Available in: All Command arguments: One Response bytes: None Command Response B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 10000000 ARG1 0 0 0 0 GPO3OEN GPO2OEN GPO1OEN 0 ARG Bit Name Function 1 7:4 Reserved Always write 0. 1 3 GPO3OEN GPO3 Output Enable. 0 = Output Disabled (Hi-Z) (default). 1 = Output Enabled. 1 2 GPO2OEN GPO2 Output Enable. 0 = Output Disabled (Hi-Z) (default). 1 = Output Enabled. 1 1 GPO1OEN GPO1 Output Enable. 0 = Output Disabled (Hi-Z) (default). 1 = Output Enabled. 1 0 Reserved Always write 0. B i t D 7D 6D 5 D 4 D 3 D 2 D 1 D 0 STATUS CTS ERR X X X RDSINT ASQINT STCINT
Rev. 1.0 145 Command 0x81. GPIO_SET Sets the output level (high or low) for GPO1, 2, and 3. GP O1, 2, and 3 can be configured for output by setting the GPO1OEN, GPO2OEN, and GPO3OEN bit in the GPIO_CTL command. To avoid excessive current consumption due to oscillation, GPO pins should not be left in a high impedance state. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This prop erty may only be set or read when in powerup mode. The default is all GPO pins set for high impedance. Note: GPIO_SET is supported in AM_SW_LW component 2.0 or later. Available in: All Command arguments: One Response bytes: None Command Response B i t D 7 D 6D 5D 4 D 3 D 2 D 1 D 0 CMD 1 0 0 0 000 1 ARG1 0 0 0 0 GPO3LEVEL GPO2LEVEL GPO1LEVEL 0 ARG Bit Name Function 1 7:4 Reserved Always write 0. 1 3 GPO3LEVEL GPO3 Output Level. 0 = Output low (default). 1 = Output high. 1 2 GPO2LEVEL GPO2 Output Level. 0 = Output low (default). 1 = Output high. 1 1 GPO1LEVEL GPO1 Output Level. 0 = Output low (default). 1 = Output high. 1 0 Reserved Always write 0. B i t D 7D 6D 5 D 4 D 3 D 2 D 1 D 0 STATUS CTS ERR X X X RDSINT ASQINT STCINT
146 Rev. 1.0 5.3.2. AM/SW/LW Receiver Properties Property 0x0001. GPO_IEN Configures the sources for the GPO2/INT interrupt pin. Valid sources are the lower 8 bits of the STATUS byte, including CTS, ERR, RSQINT, and STCINT bits. The corresponding bit is set before the interrupt occurs. The CTS bit (and optional interrupt) is set when it is safe to send the next command. The CTS interrupt enable (CTSIEN) can be set with this property and the POWER_UP command. The state of the CTSIEN bit set during the POWER_UP command can be read by reading this property and modified by writing this property. This property may only be set or read when in powerup mode. Available in: All Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 RSQREP 0 0 STCREP CTSIEN ERRIEN 0 0 RSQIEN 0 0 STCIEN Bit Name Function 15:12 Reserved Always write to 0. RSQ Interrupt Repeat. 0 = No interrupt generated when RSQINT is already set (default) 1 = Interrupt generated even if RSQINT is already set 10:9 Reserved Always write to 0. STC Interrupt Repeat. 0 = No interrupt generated when STCINT is already set (default) 1 = Interrupt generated even if STCINT is already set 7C T S I E N CTS Interrupt Enable. After PowerUp, this bit reflects the CTSIEN bit in ARG1 of PowerUp Command. 0 = No interrupt generated when CTS is set 1 = Interrupt generated when CTS is set 6E R R I E N ERR Interrupt Enable. 0 = No interrupt generated when ERR is set (default) 1 = Interrupt generated when ERR is set 5:4 Reserved Always write to 0. 3R S Q I E N RSQ Interrupt Enable. 0 = No interrupt generated when RSQINT is set (default) 1 = Interrupt generated when RSQINT is set 2:1 Reserved Always write to 0. 0S T C I E N Seek/Tune Complete Interrupt Enable. 0 = No interrupt generated when STCINT is set (default) 1 = Interrupt generated when STCINT is set
Rev. 1.0 147 Property 0x0102. DIGITAL_OUTPUT_FORMAT Configures the digital audio output format. Configuration options include DCLK edge, data format, force mono, and sample precision. Note: DIGITAL_OUTPUT_FORMAT is supported in AM_SW_LW component 2.0 or later. Available in: Si4705/06, Si4731/35/37/39, Si4730/34/36/38-D60 and later, Si4741/43/45, Si4784/85 Default: 0x0000 B i t 1 51 41 31 21 11 098 7 65432 1 0 Name 000000 0 0O F A L L O M O D E [ 3 : 0 ] 0O S I Z E [ 1 : 0 ] Bit Name Function 15:8 Reserved Always write to 0. 7O F A L L Digital Output DCLK Edge. 0 = use DCLK rising edge 1 = use DCLK falling edge 6:3 OMODE[3:0] Digital Output Mode. 0000 = I2S 0110 = Left-justified 1000 = MSB at second DCLK after DFS pulse 1100 = MSB at first DCLK after DFS pulse 2 Reserved Always write to 0. 1:0 OSIZE[1:0] Digital Output Audio Sample Precision. 0=1 6 - b i t s 1=2 0 - b i t s 2=2 4 - b i t s 3 = 8-bits
148 Rev. 1.0 Property 0x0104. DIGITAL_OUTPUT_SAMPLE_RATE Enables digital audio output and configures digital audio output sample rate in samples per second (sps). When DOSR[15:0] is 0, digital audio output is disabled. To enable digital audio output, program DOSR[15:0] with the sample rate in samples per second. The over-sampling ra te must be set in order to satisfy a minimum DCLK of 1M H z . The system controller must establish DCLK and DFS prior to enabling the digital audio output else the device will not respond and will require reset. The sample rate must be set to 0 before DCLK/DFS is removed. AM_TUNE_FREQ command must be sent after the POWER_UP command to start the internal clocking before setting this property. Note: DIGITAL_OUTPUT_SAMPLE_RATE is supported in AM_SW_LW component 2.0 or later. Available in: Si4705/06, Si4731/35/37/39, Si4730/34/36/38-D60 and later, Si4741/43/45, Si4784/85 Default: 0x0000 (digital audio output disabled) Units: sps Range: 32–48 ksps, 0 to disable digital audio output B i t 1 51 41 31 21 11 0 9 8 7 6 5 4 3 2 1 0 Name DOSR[15:0] Bit Name Function 15:0 DOSR[15:0] Digital Output Sample Rate. 32–48 ksps. 0 to disable digital audio output.
Figure 12. REFCLK Prescaler or reconfigured at other times. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. The default is 32768 Hz. Table 15. RCLK Gaps
150 Rev. 1.0 Property 0x0202. REFCLK_PRESCALE Sets the number used by the prescaler to divide the external RCLK down to the internal REFCLK. The range may be between 1 and 4095 in 1 unit steps. For example, an RCLK of 13 MHz would require a prescaler value of 400 to divide it to 32500 Hz. The reference clock frequency property would then need to be set to 32500 Hz. The RCLK must be valid 10 ns before sending and 20 ns after completing the AM_TUNE_FREQ and AM_SEEK_START commands. In addition, the RCLK must be valid at all times for proper AFC operation. The RCLK may be removed or reconfigured at other times. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 1. Available in: All Default: 0x0001 Step: 1 Range: 1–4095 *Note: For shortwave frequencies, choose a prescalar value such that you can limit the REFCLK frequency range to 31130– 32768* Hz. Bit Name Function 15:0 REFCLKF[15:0] Frequency of Reference Clock in Hz. The allowed REFCLK frequency range is between 31130 and 34406 Hz (32768 5%), or 0 (to disable AFC). B i tD 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 000 RCLK SEL RCLKP[11:0] Bit Name Function 15:13 Reserved Always write to 0. RCLKSEL. 0 = RCLK pin is clock source. 1 = DCLK pin is clock source. 11:0 RCLKP[11:0] Prescaler for Reference Clock. Integer number used to divide the RCLK frequency down to REFCLK frequency. The allowed REFCLK frequency range is between 31130 and 34406* Hz (32768 ±5%), or 0 (to disable AFC).
Rev. 1.0 151 Property 0x3100. AM_DEEMPHASIS Sets the AM Receive de-emphasis to 50 µs. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is disabled. Available in: All Default: 0x0000 Property 0x3102. AM_CHANNEL_FILTER Selects the bandwidth of the AM channel filter. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 2 kHz bandwidth channel filter. Note: The 1 kHz option, 1.8 kHz option, and 100 Hz high-pass Line Noise Rejection filter are supported on Si473x-C40 and later devices and Si474x devices (AM_SW_LW component 3.0 or later). The 2.5 kHz option is supported on Si473x-C40 and later devices (AM_SW_LW component 5.0 or later). Available in: All Default: 0x0003 B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1 D 0 Name 000000000000000 D E E M P H Bit Name Function 15:1 Reserved Always write to 0.
0 DEEMPH
AM De-Emphasis. 1=5 0µ s . 0 = Disabled. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 000000 A M P L F L T 0 000A M C H F L T [ 0 3 : 0 ] Bit Name Function 15:9 Reserved Always write to 0.
8 AMPLFLT Enables the AM Power Line Noise Rejection Filter
7:4 Reserved Always write to 0. 3:0 AMCHFILT AM Channel Filter. Selects the bandwidth of the AM channel filter. The following choices are available: 0=6k H z B a n d w i d t h 1=4k H z B a n d w i d t h 2=3k H z B a n d w i d t h 3=2k H z B a n d w i d t h 4=1k H z B a n d w i d t h 5=1 . 8k H z B a n d w i d t h 6 = 2.5 kHz Bandwidth, gradual roll off 7–15 = Reserved (Do not use)
152 Rev. 1.0 Property 0x3103. AM_AUTOMATIC_VOLUME_CONTROL_MAX_GAIN Sets the maximum gain for automatic volume control. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 16 dB. The maximum AVC gain affects audio output level, especially under weak signal conditions. It amplifies the signal as well as noise. When a signal is very weak (needs a lot of gain) then the maximum gain will be applied, and may make the noise too harsh for the listener, even the soft mute functions. The user can reduce the noise further by adjusting the maximum AVC gain. The property allows th e user to optimize the trade-off between maintaining output level and suppressing noise. Note: The maximum AVC gain is not configurable in Si473x-B20 dev ices (FMRX component 2.1 and earlier), and is 90.3 dB. This would be equivalent to AM_AUTOMATIC_VOLUME_CONT ROL_MAX_GAIN property value 0x7800, which is the maximum value. Available in: Si473x-C40 and later, Si474x Default: 0x1543 (Si473x-C40 and later) 0x7800 (Si474x) Step: 1 Range: 0X1000 ~ 0x7800 Property 0x3104. AM_MODE_AFC_SW_PULL_IN_RANGE Sets the SW AFC pull-in or tracking range. The value PULL_IN_RANGE is relative to the tuned frequency and is specified as 1/(PPM×10–6). For example to program a pull-in range of 115 ppm, PULL_IN_RANGE = 1/(115×10–6) = 8695. The command is complete when the CTS bit (and optional interrupt) is set. Available in: Si4734/35-C40 and later, Si4742/43/44/45 Default: 0x21F7 (115 ppm) B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7 D 6D 5D 4D 3D 2D 1 D 0 Name 0 AVC_MAXGAIN [14:0] Bit Name Function 15 Reserved Always write to 0. 14:0 AVC_MAXGAIN Automatic Volume Control Max Gain. Maximum gain for automatic volume control. The max gain value is given by AVC_MAXGAIN = g * 340.2 where g is the desired maximum AVC gain in dB. Minimum of 12 dB is recommend when SOFTMUTE is enabled. B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7 D 6D 5D 4D 3D 2D 1 D 0 Name SWPIR[15:0]
Rev. 1.0 153 Property 0x3105. AM_MODE_AFC_SW_LOCK_IN_RANGE Sets the SW AFC lock-in or capture range. The value LO CK_IN_RANGE is relative to the tuned frequency and is specified as 1/( PPM×10–6). For example to program a lock-in range of 85 ppm, LOCK_IN_RANGE = 1/(85×10–6) = 11765. The command is complete when the CTS bit (and optional interrupt) is set. Available in: Si4734/35-C40 and later, Si4742/43/44/45 Default: 0x2DF5 (85 ppm) Property 0x3200. AM_RSQ_INT_SOURCE Configures interrupt related to Received Signal Quality metrics. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. Available in: All Default: 0x0000 Bit Name Function 15:0 SWPIR[15:0] SW Pull-In Range The SW pull-in range expressed relative to the tuned frequency. B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7 D 6D 5D 4D 3D 2D 1 D 0 Name SWPIR[15:0] Bit Name Function 15:0 SWPIR[15:0] SW Pull-In Range The SW lock-in range expressed relative to the tuned frequency. B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4 D 3 D 2 D 1 D 0 Name 0 0 0 0 0 0 0 0 0 0 0 0 SNRHIEN SNRLIEN RSSIHIEN RSSILIEN
154 Rev. 1.0 Bit Name Function 15:4 Reserved Always write 0. Interrupt Source Enable: SNR High. Enable SNR high as the source of interrupt which the threshold is set by AM_RSQ_SN- R_HI_THRESHOLD.
2 SNRLIEN
Interrupt Source Enable: SNR Low. Enable SNR low as the as the source of interrupt which the threshold is set by AM_R- SQ_SNR_LO_THRESHOLD. Interrupt Source Enable: RSSI High. Enable RSSI low as the source of interrupt which the threshold is set by AM_R- SQ_RSSI_HI_THRESHOLD. Interrupt Source Enable: RSSI Low. Enable RSSI low as the source of interrupt which the threshold is set by AM_R- SQ_RSSI_LO_THRESHOLD.
Rev. 1.0 155 Property 0x3201. AM_RSQ_SNR_HI_THRESHOLD Sets high threshold which triggers the RSQ interrupt if the SNR is above this threshold. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 127 dB. Available in: All Default: 0x007F Units: dB Step: 1 Range: 0–127 Property 0x3202. AM_RSQ_SNR_LO_THRESHOLD Sets low threshold which triggers the RSQ interrupt if the SNR is be low this threshold. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0 dB. Available in: All Default: 0x0000 Units: dB Step: 1 Range: 0–127 B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7 D 6D 5D 4D 3D 2D 1D 0 Name 0 0 0 0 0 0 0 0 0 SNRH[6:0] Bit Name Function 15:7 Reserved Always write to 0. 6:0 SNRH AM RSQ SNR High Threshold. Threshold which triggers the RSQ interrupt if the SNR goes above this threshold. Specified in units of dB in 1 dB steps (0–127). Default is 0 dB. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 SNRL[6:0] Bit Name Function 15:7 Reserved Always write to 0. 6:0 SNRL AM RSQ SNR Low Threshold. Threshold which triggers the RSQ interrupt if the SNR goes below this threshold. Specified in units of dB in 1 dB steps (0–127). Default is 0 dB.
156 Rev. 1.0 Property 0x3203. AM_RSQ_RSSI_HI_THRESHOLD Sets high threshold which triggers the RSQ interrupt if the RSSI is above this threshold. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 127 dB. Available in: All Default: 0x007F Units: dBµV Step: 1 Range: 0–127 Property 0x3204. AM_RSQ_RSSI_LO_THRESHOLD Sets low threshold which triggers the RSQ interrupt if the RSSI is below this threshold. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0 dB. Available in: All Default: 0x0000 Units: dBµV Step: 1 Range: 0–127 B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7 D 6D 5D 4D 3D 2D 1D 0 Name 0 0000000 0 R S S I H [ 6 : 0 ] Bit Name Function 15:7 Reserved Always write to 0. 6:0 RSSIH AM RSQ RSSI High Threshold. Threshold which triggers the RSQ interrupt if the RSSI goes above this threshold. Spec- ified in units of dBµV in 1 dB steps (0–127). Default is 0 dBµV. B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7 D 6D 5D 4D 3D 2D 1D 0 Name 0 0000000 0 R S S I L [ 6 : 0 ] Bit Name Function 15:7 Reserved Always write to 0. 6:0 RSSIL AM RSQ RSSI Low Threshold. Threshold which triggers the RSQ interrupt if the RSSI goes below this threshold. Spec- ified in units of dBµV in 1 dB steps (0–127). Default is 0 dBµV.
Rev. 1.0 157 Property 0x3300. AM_SOFT_MUTE_RATE Sets the attack and decay rates when entering or leaving soft mute. The value specified is multiplied by 4.35 dB/s to come up with the actual attack rate. The CTS bit (and optio nal interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default rate is 278 dB/s. Available in: All Default: 0x0040 Actual Rate: SMRATE x 4.35 Units: dB/s Step: 1 Range: 1–255 Property 0x3301. AM_SOFT_MUTE_SLOPE Configures attenuation slope during soft mute in dB attenuation per dB SNR below the soft mute SNR threshold. Soft mute attenuation is the minimum of SMSLOPE x (SMTHR – SNR) and SMATTN. The recommended SMSLOPE value is CEILING(SMATTN/SMTHR) . SMATTN and SMTHR are set via the AM_SOFT_MUTE_MAX_ATTENUATION and AM_SOFT_MU TE_SNR_THRESHOLD properties. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default slope is 1 dB/dB for AMRX component 5.0 or later and 2 dB/dB for AMRX component 3.0 or earlier. Available in: All Default: 0x0002 (Si4730/31/34/35/36/37-B20 and earlier, Si4740/41/42/43/44/45-C10 and earlier) 0x0001 (all others) Units: dB/dB Range: 1–5 B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name SMRATE[15:0] Bit Name Function 15:0 SMRATE AM Soft Mute Rate. Determines how quickly the AM goes into soft mute when soft mute is enabled. The actual rate is calculated by taking the value written to the field and multiplying it with 4.35 dB/s. The default rate is 278 dB/s (SMRATE[15:0] = 0x0040). B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 0 00000000000 S M S L O P E [ 3 : 0 ] Bit Name Function
158 Rev. 1.0 Property 0x3302. AM_SOFT_MUTE_MAX_ATTENUATION Sets maximum attenuation during soft mute (dB). Set to 0 to disable soft mute. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default attenuation is 8 dB for AMRX component 5.0 or later and 16 dB for AMRX component 3.0 or earlier. Available in: All Default: 0x0010 (Si4730/31/34/35/36/37-B20 and earlier, Si4740/41/42/43/44/45-C10 and earlier) 0x0008 (all others) Units: dB Step: 1 Range: 0–63 Property 0x3303. AM_SOFT_MUTE_SNR_THRESHOLD Sets the SNR threshold to engage soft mute. Whenever the SNR for a tuned frequency drops below this threshold the AM reception will go in soft mute , provided soft mute max attenuation pr operty is non-zero. The CTS bit (and optional interrupt) is set when it is sa fe to send the next command. This property may only be set or read when in powerup mode. The default SNR threshold is 8 dB fo r AMRX component 5.0 or later and 10 dB for AMRX component 3.0 or earlier. Available in: All Default: 0x000A (Si4730/31/34/35/36/37-B20 and earlier, Si4740/41/42/43/44/45-C10 and earlier) 0x0008 (all others) Units: dB Step: 1 Range: 0–63 15:4 Reserved Always write to 0. 3:0 SMSLOPE[3:0] AM Slope Mute Attenuation Slope. Set soft mute attenuation slope in dB attenuation per dB SNR below the soft mute SNR threshold. B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 0 000000000 S M A T T N [ 5 : 0 ] Bit Name Function 15:6 Reserved Always write to 0. 5:0 SMATTN AM Soft Mute Max Attenuation. Maximum attenuation to apply when in soft mute. Specified in units of dB. Default maximum attenuation is 8 dB. B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 0 000000000 S M T H R [ 5 : 0 ]
Rev. 1.0 159 Property 0x3304. AM_SOFT_MUTE_RELEASE_RATE Sets the soft mute release rate. Smaller values provide slower release and larger values provide faster release. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 8192 (approximately 8000 dB/s). Release Rate (dB/s) = RELEASE[14:0]/1.024 Available in: Si4740/41/42/43/44/45 Default: 0x2000 Range: 1–32767 Bit Name Function 15:6 Reserved Always write to 0. 5:0 SMTHR AM Soft Mute SNR Threshold. The SNR threshold for a tuned frequency below which soft mute is engaged provided the value written to the AM_SOFT_MUTE_MAX_ATTENUATION property is not zero. Default SNR threshold is 8 dB. B i t D 1 5D 1 4D 1 3D 1 2D 1 1D 1 0D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 0 RELEASE[14:0]
read when in powerup mode. The default is 8192 (approximately 8000 dB/s). Figure 13. AM Softmute SNR
Rev. 1.0 161 Property 0x3400. AM_SEEK_BAND_BOTTOM Sets the lower boundary for the AM band in kHz. This value is used to determine when the lower end of the AM band is reached when performing a seek. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 520 kHz (0x0208). Available in: All Default: 0x0208 Units: kHz Step: 1 kHz Valid Range: 149–23000 kHz Recommended Range: AM in US: 520–1710 kHz AM in Asia: 522–1710 kHz SW: 2300–23000 kHz LW: 153–279 kHz B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name AMSKFREQL[15:0] Bit Name Function 15:0 AMSKFREQL AM Seek Band Bottom. Specify the lower boundary of the AM band when performing a seek. The seek either stops at this limit or wraps based on the parameters of AM_SEEK_START command that was issued to initiate a seek. The default value for the lower boundary of the AM band is 520 kHz.
162 Rev. 1.0 Property 0x3401. AM_SEEK_BAND_TOP Sets the upper boundary for the AM band in kHz. This value is used to determine when the higher end of the AM band is reached when performing a seek. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 1710 kHz (0x06AE). Available in: All Default: 0x06AE Note: Firmware 1.0 incorrectly reports 0x06B9 (1721 k Hz) as default for AM_SEEK_BAND_TOP. After POWER_UP command is complete, set AM_SEEK_BAND_TOP to 0x06AE (1710 kHz) using the SET_PROPERTY command. Units: kHz Step: 1 kHz Valid Range: 149–23000 kHz Recommended Range: AM in US: 520–1710 kHz AM in Asia: 522–1710 kHz SW: 2300–23000 kHz LW: 153–279 kHz B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name AMSKFREQH[15:0] Bit Name Function 15:0 AMSKFREQH AM Seek Band Top. Specify the higher boundary of the AM band when performing a seek. The seek either stops at this limit or wraps based on the parameters of AM_SEEK_START command that was issued to initiate a seek. The default value for the upper boundary of the AM band is 1710 kHz.
Rev. 1.0 163 Property 0x3402. AM_SEEK_FREQ_SPACING Sets the frequency spacing for the AM Band when perfo rming a seek. The frequency spacing determines how far the next tune is going to be from the currently tuned frequency. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may on ly be set or read when in powerup mode. The default frequency spacing is 10 kHz. Available in: All Default: 0x000A Units: kHz Valid Values: 1 (1 kHz), 5 (5 kHz), 9 (9 kHz), and 10 (10 kHz). Recommended Value: AM in US: 10 (10 kHz) AM in Asia: 9 (9 kHz) SW: 5 (5 kHz) LW: 9 (9 kHz) B i t D 1 5D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1 D 0 Name 0 0 0 0 0 0 0 0 0 0 0 0 AMSKSPACE[3:0] Bit Name Function 15:4 Reserved Always write to 0. 3:0 AMSKSPACE AM Seek Frequency Spacing. Sets the frequency spacing when performing a seek in the AM band. The default fre- quency spacing is 10 kHz.
164 Rev. 1.0 Property 0x3403. AM_SEEK_TUNE_SNR_THRESHOLD Sets the SNR threshold for a valid AM Seek/Tune. If the value is zero, then SNR is not used as a valid criteria when doing a seek for AM. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default threshold is 5 dB. Available in: All Default: 0x0005 Units: dB Step: 1 Range: 0–63 Property 0x3404. AM_SEEK_TUNE_RSSI_THRESHOLD Sets the RSSI threshold for a valid AM Seek/Tune. If the value is zero then RSSI is not used as a valid criteria when doing a seek for AM. The CTS bit (and optional interr upt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 25 dBµV. Available in: All Default: 0x0019 Units: dBµV Step: 1 Range: 0–63 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 AMSKSNR[5:0] Bit Name Function 15:6 Reserved Always write to 0. 5:0 AMSKSNR AM Seek/Tune SNR Threshold. SNR Threshold which determines if a valid channel has been found during Seek/Tune. Specified in units of dB in 1 dB steps (0–63). Default threshold is 5 dB. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 AMSKRSSI[5:0] Bit Name Function 15:6 Reserved Always write to 0. 5:0 AMSKRSSI AM Seek/Tune Received Signal Strength Threshold. RSSI Threshold which determines if a valid channel has been found during Seek/Tune. Specified in units of dBµV in 1 dBµV steps (0–63). Default threshold is 25 dBµV.
Rev. 1.0 165 Property 0x3702. AM_AGC_ATTACK_RATE Sets the AGC attack rate. Large values provide slower at tack, and smaller values provide faster attack. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read in POWERUP mode. The default is 4 (approximately 1400 dB/s). Nominal "5600" is based on Silabs ' AM antenna dummy and Si474xEVB referenc e design and may vary with source impedance and design changes. In most systems, an exact value is not important. However, to calculate for a different source impedance and/or design: 1. Drive antenna input with desired source impedance (via antenna or antenna dummy). 2. Increase RF level until AGC index changes from 19 to 20. Record last RF level with index equal 19. 3. Increase RF level until AGC index reaches 39. Record RF level with index equal 39. 4. Replace “5600” in rate equation with “(RF39 – RF19)/0.00667”. Available in: Si4740/41/42/43/44/45 Default: 0x0004 Step: 4 Range: 4–248 Notes: 1. Was property 0x4102 in FW2.C. 2. For FW2.E, attack rate may be faster than programmed depending on initial and final RF levels. B i t D 1 5D 1 4D 1 3D 1 2D 1 1D 1 0D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 0000000 0 A T T A C K [ 7 : 0 ] AGC Attack Rate (dB/s) 5600
166 Rev. 1.0 Property 0x3703. AM_AGC_RELEASE_RATE Sets the AGC release rate. Larger values provide slower release, and smaller values provide faster release. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read in POWERUP mode. The default is 140 (approximately 40 dB/s). Nominal "5600" is based on Silabs ' AM antenna dummy and Si474xEVB referenc e design and may vary with source impedance and design changes. In most systems, an exact value is not important. However, to calculate for a different source impedance and/or design: 1. Drive antenna input with desired source impedance (via antenna or antenna dummy). 2. Increase RF level until AGC index changes from 19 to 20. Record last RF level with index equal 19. 3. Increase RF level until AGC index reaches 39. Record RF level with index equal 39. 4. Replace "5600" in rate equation with "(RF39 – RF19)/0.00667". Available in: Si4740/41/42/43/44/45 Default: 0x008C Step: 4 Range:4–248 Note: Was property 0x4103 in FW2.C. Property 0x3705. AM_FRONTEND_AGC_CONTROL Adjusts the AM AGC for external front-end attenuator and external front-end cascode LNA. This property contains two fields: MIN_GAIN_INDEX and ATTN_BACKUP . The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0x130C (MIN_AGC_INDEX=19 and ATTN_BACKUP=12). Available in: Si4740/41/42/43/44/45 Default: 0x130C MIN_GAIN_INDEX impacts sensitivity a nd U/D performance. Lower values im prove sensitivity, but degrade far away blocker U/D performance. [Note: Values below 19 have minimal sensitivity improvement.] Higher values degrade sensitivity, but improve U/D. With MIN_GA IN_INDEX=19 and Si4743 EVB re ference design, the Si474x provides sensitivity of 28dBuV typical and U/D exceeding 55dB on far away blockers. With MIN_GAIN_INDEX=24, the Si474x provides sensitivity of 34dBuV typical and U/D approaching 70dB on far away blockers. The recommended MIN_GAIN_INDEX optimization procedure is: 1. Determine source impedance and AM antenna dummy. B i t D 1 5D 1 4D 1 3D 1 2D 1 1D 1 0D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 0000000 00 R E L E A S E [ 7 : 0 ] B i t D 1 5D 1 4D 1 3D 1 2D 1 1D 1 0D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name MIN_GAIN_INDEX[7:0] ATTN_BACKUP[7:0] AGC Release Rate (dB/s) 5600
- Determine sensitivity RF in put and SINAD requirements.
- Set frequency to 1000kHz.
- With source impedance in #1 and RF input in #2, adjust MIN_GAIN_INDEX until SINAD requirements are
achieved with minimum necessary margin.
- Program this value into Si474x MIN_GAIN_INDEX as part of initialization after POWERUP command.
via GPO1/AGC2. The actual attenuation achieved depen ds on the source impedance or AM antenna dummy.
- Determine source impedance and AM antenna dummy.
- Determine maximum RF input and associated SINAD requirements.
- Set frequency to 1710kHz.
- With ATTN_BACKUP set to 12 (default), disabl e the AGC at AMAGCNDX=47 using AM_AGC_OVERRIDE
- With source impedance in #1 and RF input in #2, adj ust attenuator impedance until SINAD requirements are
antenna sources and R8 (1 ohm) attenuates against active (50 ohm) sources.
- Enable the AGC using AM_AGC_OVERRIDE.
- Sweep the RF input from 0 to 126 dBuV and then from 126 to 0 dBuV in 1 dB steps and observe the
AMAGCNDX at each RF level using AM_AGC_STATUS command.
- If AMAGCNDX is observed to oscillate at any RF leve l, increase ATTN_BACKUP by 1 and repeat from step 7.
- If AMAGCNDX is observed not to oscillate at any RF level, decrease ATTN_BACKUP by one and repeat from
- Add one to smallest ATTN_BACKUP for which no oscillations are observed and program this value into Si474x
ATTN_BACKUP as part of initialization after POWERUP command. Table 16. Recommended Values for MIN_GAIN_INDEX and ATTN_BACKUP with FW2.E and later,
168 Rev. 1.0 Property 0x3900. AM_NB_DETECT_THRESHOLD Sets the threshold for detecting impulses in dB above the noise floor. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read in POWERUP mode. The default is 12 dB. Available in: Si4742/43/44/45 Default: 0x000C Range: 0–90 Note: Was property 0x4105 in FW2.C. Property 0x3901. AM_NB_INTERVAL Interval in micro-seconds that original samples are re placed by sample-hold clean samples. The CTS bit (and optional interrupt) is set when it is safe to send the next co mmand. This property may only be set or read in POWERUP mode. The default is 55 µs. Available in: Si4742/43/44/45 Default: 0x0037 Range: 15–110 Note: Was property 0x4106 in FW2.C. Property 0x3902. AM_NB_RATE Noise blanking rate in 100 Hz units. The CTS bit (and optiona l interrupt) is set when it is safe to send the next command. This property may only be set or read in POWERUP mode. The default is 64 (6400 Hz). Available in: Si4742/43/44/45 Default: 0x0040 Range: 1–64 Note: Was property 0x4107 in FW2.C. B i t D 1 5D 1 4D 1 3D 1 2D 1 1D 1 0D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name NB_DETECT_THRESHOLD [15:0] B i t D 1 5D 1 4D 1 3D 1 2D 1 1D 1 0D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name NB_INTERVAL [15:0] B i t D 1 5D 1 4D 1 3D 1 2D 1 1D 1 0D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name NB_RATE [15:0]
Rev. 1.0 169 Property 0x3903. AM_NB_IIR_FILTER Sets the bandwidth of the noise floor estimator. The CTS bi t (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read in POWERUP mode. The default is 300 (465 Hz). Bandwidth (Hz) = NB_IIR_FILTER[15:0] x 1.55 Available in: Si4742/43/44/45 Default: 0x012C Range: 300–1600 Note: Was property 0x4108 in FW2.C. Property 0x3904. AM_NB_DELAY Delay in micro-seconds before applying impulse blanking to the original samples. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read in POWERUP mode. The default is 172 µs. Available in: Si4742/43/44/45 Default: 0x00AC Range: 125–219 Note: Was property 0x4109 in FW2.C. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name NB_IIR_FILTER [15:0] Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name NB_DELAY [15:0]
Figure 14. AM Noise Blanker Sets the audio output volume. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 63. 15:6 Reserved Always write to 0. Sets the output volume level, 63 max, 0 min. Default is 63. AM_NB_RATE: sets maximum repeat rate NB is allowed to fire.
Rev. 1.0 171 Property 0x4001. RX_HARD_MUTE Mutes the audio output. L and R audio outputs may not be muted independently. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is unmute (0x0000). Available in: All Default: 0x0000 B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2 D 1 D 0 Name 000000 0 0000000 L M U T E R M U T E Bit Name Function 15:2 Reserved Always write to 0. 1 LMUTE Mutes both L and R Audio Outputs. 0 RMUTE Mutes both L and R Audio Outputs.
component applicable to Si4707/36/37/38/39/42/43. Table 17. WB Receiver Command Summary file, see "7.2. Powerup from a Component Patch" on page 216.
Table 18. WB Receive Property Summary 34406 Hz, or 0 to disable the AFC.
Table 19. Status Response for the WB Receiver 0 = Wait before sending next command. 1 = Clear to send next command. 5:4 Reserved Values may vary. Received Signal Quality Interrupt. 0 = Received Signal Quality measurement has not been triggered. 1 = Received Signal Quality measurement has been triggered. SAME Interrupt (Si4707 Only). 0 = SAME interrupt has not been triggered. 1 = SAME interrupt has been triggered. Audio Signal Quality Interrupt. 0 = Audio Signal Quality measurement has not been triggered. 1 = Audio Signal Quality measurement has been triggered. Seek/Tune Complete Interrupt. 0 = Tune complete has not been triggered. 1 = Tune complete interrupt has been triggered.
Rev. 1.0 175 5.4.1. WB Receiver Commands Command 0x01. POWER_UP Initiates the boot process to move the device from powerdown to powerup mode. The boot can occur from internal device memory or a system controller downloaded patch. To confirm that the patch is compatible with the internal device library revision, the library revision should be confirmed by issuing the POWER_UP command with FUNC = 15 (query library ID). The device returns the response , including the library revision, and then moves into powerdown mode. The device can then be placed in powerup mode by issuing the POWER_UP command with FUNC = 3 (WB Receive) and the patch may be applied. The POWER_UP command configures the state of ROUT (pin 13), LOUT (pin 14) for analog audio mode. For Si4743 component 2A or higher, the POWER_UP command also configures the state of GPO3/DCLK (pin 19), DFS (pin 18), and DOUT (pin 17) for digital audio mode. The command configures GPO2/INT~ interrupts (GPO2OEN) and CTS interrupts (CTSIEN). If both are enabled, GPO2/IRQ is driven high during normal operation and low for a minimum of 1 μs during the interrupt. The CTSIEN bit is duplicated in the GPO_IEN property. The command is complete when the CTS bit (and optional interrupt) is set. To change function (e.g., WB RX to FM RX), issue POWER_DOWN command to stop current function; then, issue POWER_UP to start new function. Note: Delay at least 500 ms between powerup command and first tu ne command to wait for the oscillator to stabilize if XOSCEN is set and crystal is used as the RCLK Available in: All Command Arguments: Two Response Bytes: None (FUNC=3), Seven (FUNC=15) Command Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 000 0 0 0 0 1 ARG1 CTSIEN GPO2OEN PATCH XOSCEN FUNC[3:0] ARG2 OPMODE[7:0]
176 Rev. 1.0 Arg Bit Name Function 1 7 CTSIEN CTS Interrupt Enable. 0 = CTS interrupt disabled. 1 = CTS interrupt enabled. 1 6 GPO2OEN GPO2 Output Enable. 0 = GPO2 output disabled. 1 = GPO2 output enabled. 15 P A T C H Patch Enable. 0 = Boot normally 1 = Copy NVM to RAM, but do not boot. After CTS has been set, RAM may be patched 1 4 XOSCEN Crystal Oscillator Enable. 0 = Use external RCLK (crystal oscillator disabled) 1 = Use crystal oscillator (RCLK and GPO3/DCLK with external 32.768kHz crystal and OPMODE = 00000101) See Si47xx Data Sheet Application Schematic for external BOM details. 1 3:0 FUNC[3:0] Function. 3=W B R e c e i v e . 0–2, 4–14 = Reserved 15 = Query Library ID. 2 7:0 OPMODE[7:0] Application Setting 00000101 = Analog audio outputs (LOUT/ROUT) 00001011 = Digital audio output (DCLK, LOUT/DFS, ROUT/DIO) 10110000 = Digital audio outputs (DCLK, DFS, DIO) (Si4743 component 2.A or higher with XOSCEN = 0) 10110101 = Analog and digital outputs (LOUT/ROUT and DCLK, DFS, DIO) (Si4743 component 2.A or higher with XOSCEN = 0)
Rev. 1.0 177 Response (FUNC = 3, WB Receive) Response (FUNC = 15, Query Library ID) Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT SAMEINT ASQINT STCINT Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT SAMEINT ASQINT STCINT RESP1 PN[7:0] RESP2 FWMAJOR[7:0] RESP3 FWMINOR[7:0] RESP4 RESERVED[7:0] RESP5 RESERVED[7:0] RESP6 CHIPREV[7:0] RESP7 LIBRARYID[7:0] RESP Bit Name Function 1 7:0 PN[7:0] Final 2 digits of part number (HEX). 2 7:0 FWMAJOR[7:0] Firmware Major Revision (ASCII). 3 7:0 FWMINOR[7:0] Firmware Minor Revision (ASCII). 4 7:0 RESERVED[7:0] Reserved, various values. 5 7:0 RESERVED[7:0] Reserved, various values. 6 7:0 CHIPREV[7:0] Chip Revision (ASCII). 7 7:0 LIBRARYID[7:0] Library Revision (HEX).
178 Rev. 1.0 Command 0x10. GET_REV Returns the part number, chip revision, firmware revision, patch revision and component revision numbers. The command is complete when the CTS bit (and optional inte rrupt) is set. This command may only be sent when in powerup mode. Available in: All Command arguments: None Response bytes: Eight Command Response B i t D 7D 6D 5 D 4 D 3 D 2 D 1 D 0 CMD 000 1 0 0 0 0 B i t D 7D 6D 5D 4D 3D 2D 1D 0 STATUS CTS ERR X X RSQINT SAMEINT ASQINT STCINT RESP1 PN[7:0] RESP2 FWMAJOR[7:0] RESP3 FWMINOR[7:0] RESP4 PATCHH[7:0] RESP5 PATCHL[7:0] RESP6 CMPMAJOR[7:0] RESP7 CMPMINOR[7:0] RESP8 CHIPREV[7:0] RESP Bit Name Function 1 7:0 PN[7:0] Final 2 digits of Part Number 2 7:0 FWMAJOR[7:0] Firmware Major Revision 3 7:0 FWMINOR[7:0] Firmware Minor Revision 4 7:0 PATCH H[7:0] Patch ID High Byte 5 7:0 PATCH L[7:0] Patch ID Low Byte 6 7:0 CMPMAJOR[7:0] Component Major Revision 7 7:0 CMPMINOR[7:0] Component Minor Revision 8 7:0 CHIPREV[7:0] Chip Revision
Rev. 1.0 179 Command 0x11. POWER_DOWN Moves the device form powerup to powerdown mode. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Note that only the POWER_UP command is accepted in powerdown mode. If the system controller writes a command other than POWER_UP when in powerdown mode, the device does not respond. The device will only respond when a POWER_UP command is written. Note: The following describes the state of all the pins when in powerdown mode: GPIO1, GPIO2, and GPIO3 = 0 ROUT, LOUT, DOUT, DFS = Hiz. Available in: All Command arguments: None Response bytes: None Command Response Command 0x12. SET_PROPERTY Sets a property shown in Table 18, “WB Receive Property Summary,” on page 173. The CTS bit (and optional interrupt) is set when it is safe to send the next co mmand. This command may only be sent when in powerup mode. Available in: All Command Arguments: Five Response bytes: None Command Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 000 1 0 0 0 1 B i t D 7D 6D 5D 4D 3D 2D 1D 0 STATUS CTS ERR X X RSQINT SAMEINT ASQINT STCINT Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 00 0 1 0 0 1 0 ARG1 00 0 0 0 0 0 0 ARG2 PROPH[7:0] ARG3 PROPL[7:0] ARG4 PROPVH[7:0] ARG5 PROPVL[7:0]
180 Rev. 1.0 Command 0x13. GET_PROPERTY Gets a property as shown in Table 18, “WB Receive Property Summary,” on page 173. The CTS bit (and optional interrupt) is set when it is safe to send the next co mmand. This command may only be sent when in powerup mode. Available in: All Command arguments: Three Response bytes: Three Command Arg Bit Name Function 1 7:0 Reserved Always write to 0. 27 : 0 P R O P H[7:0] Property High Byte. This byte in combination with PROPL is used to specify the property to modify. 37 : 0 P R O P L[7:0] Property Low Byte. This byte in combination with PROPH is used to specify the property to modify. 47 : 0 P R O P V H[7:0] Property Value High Byte. This byte in combination with PROPVL is used to set the property value. 57 : 0 P R O P V L[7:0] Property Value Low Byte. This byte in combination with PROPVH is used to set the property value. B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 00010011 ARG1 00000000 ARG2 PROPGH[7:0] ARG3 PROPGL[7:0] Arg Bit Name Function 1 7:0 Reserved Always write to 0. 27 : 0P R O P G H[7:0] Property High Byte. This byte in combination with PROPL is used to specify the property to get. 37 : 0 P R O P G L[7:0] Property Low Byte. This byte in combination with PROPH is used to specify the property to get.
Rev. 1.0 181 Response Command 0x14. GET_INT_STATUS Updates bits 6:0 of the status byte . This command should be called afte r any command that sets the STCINT, RSQINT, SAMEINT (Si4707 only), or ASQINT bits. When polling this comm and should be periodically called to monitor the status byte, and when us ing interrupts, this command should be called after the interrupt is set to updated the status byte. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Available in: All Command arguments: None Response bytes: One Command Response B i tD 7D 6D 5D 4D 3D 2D 1D 0 STATUS CTS ERR X X RSQINT SAMEINT ASQINT STCINT RESP1 00000000 RESP2 PROPVH[7:0] RESP3 PROPVL[7:0] RESP Bit Name Function 1 7:0 Reserved Always returns 0. 27 : 0 P R O P V H[7:0] Property Value High Byte. This byte in combination with PROPVL will represent the requested property value. 37 : 0 P R O P V L[7:0] Property Value High Byte. This byte in combination with PROPVH will represent the requested property value. B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 00010100 B i tD 7D 6D 5D 4D 3D 2D 1D 0 STATUS CTS ERR X X RSQINT SAMEINT ASQINT STCINT
182 Rev. 1.0 Command 0x50. WB_TUNE_FREQ Sets the WB Receive to tune the frequency between 1 62.4 MHz and 162.55 MHz in 2.5 kHz units. For example 162.4 MHz = 64960 and 162.55 MHz = 65020. The CTS bit (and optional interrupt) is set when it is safe to send the next command. The ERR bit (and optional interrupt) is set if an invalid argument is sent. Note that only a single interrupt occurs if both the CTS and ERR bits are se t. The optional STC interrupt is set when the command completes. The STCINT bit is set only after the GET_INT_STATUS command is called. This command may only be sent when in powerup mode. The command clears the STC bit if it is already set. Available in: All Command arguments: Three Response bytes: None Command B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 01010000 ARG1 00000000 ARG2 FREQH[7:0] ARG3 FREQL[7:0] Arg Bit Name Function 1 7:0 Reserved Always write to 0. 27 : 0 F R E Q H[7:0] Tune Frequency High Byte. This byte in combination with FREQL selects the tune frequency in kHz. In WB mode the valid range is from 64960 to 65020 (162.4–162.55 MHz). 37 : 0 F R E Q L[7:0] Tune Frequency Low Byte. This byte in combination with FREQH selects the tune frequency in kHz. In WB mode the valid range is from 64960 to 65020 (162.4–162.55 MHz).
Rev. 1.0 183 Command 0x52. WB_TUNE_STATUS Returns the status of WB_TUNE_FREQ. The commands returns the current frequen cy, and RSSI/SNR at the moment of tune. The command clears the STCINT interrupt bit when INTACK bit of ARG1 is set. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Available in: All Command arguments: One Response bytes: Five Command Response B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 01010010 ARG1 0000000 I N T A C K Arg Bit Name Function 1 7:1 Reserved Always write to 0. 10 I N T A C K Seek/Tune Interrupt Clear. If set this bit clears the seek/tune complete interrupt status indicator. B i tD 7D 6D 5D 4D 3D 2D 1D 0 STATUS CTS ERR X X RSQINT SAMEINT ASQINT STCINT RESP1 XXXXXX A F C R L V A L I D RESP2 READFREQH[7:0] RESP3 READFREQL[7:0] RESP4 RSSI[7:0] RESP5 SNR[7:0]
184 Rev. 1.0 Command 0x53. WB_RSQ_STATUS Returns status information about the received signal quality. The commands returns the RSSI, SNR, and frequency offset. It also indicates whether the frequency is a currently valid frequency as indicated by VALID, and whether the AFC is railed or not as indicated by AFCRL. This command can be used to check if the received signal is above the RSSI high threshold as reported by RSSIHINT, or below the RSSI low threshold as reported by RSSILINT. It can also be used to check if the received signal is above the SNR high threshold as reported by SNRHINT, or below the SNR low threshold as reported by SNRLINT. The command clears the STCINT interrupt bit when INTACK bit of ARG1 is set. The CTS bit (and optional interrupt) is set wh en it is safe to send the next command. This command may only be sent when in powerup mode. Available in: All Command arguments: One Response bytes: Seven Command Data Bit Name Function 1 7:2 Reserved Always returns 0. 1 1 AFCRL AFC Rail Indicator. This bit will be set if the AFC rails. 10 V A L I D Valid Channel. Confirms if the tuned channel is currently valid. 2 7:0 READFREQ H[7:0] Read Frequency High Byte. This byte in combination with READFREQL returns frequency being tuned. 37 : 0 R E A D F R E Q L[7:0] Read Frequency Low Byte. This byte in combination with READFREQH returns frequency being tuned. 4 7:0 RSSI[7:0] Received Signal Strength Indicator. This byte will contain the receive signal strength at the tuned frequency. 5 7:0 SNR[7:0] SNR. This byte will contain the SNR metric at the tuned frequency. B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 01010011 ARG1 0000000 I N T A C K Arg Bit Name Function
10 I N T A C K Interrupt Acknowledge
0 = Interrupt status preserved. 1 = Clears RSQINT, SNRHINT, SNRLINT, RSSIHINT, RSSILINT
Rev. 1.0 185 Response B i t D 7 D 6D 5D 4D 3 D 2 D 1 D 0 STATUS CTS ERR X X RSQINT SAMEINT ASQINT STCINT RESP1 X XXX S N R H I NT SNRLINT RSSIHI NT RSSIILINT RESP2 X XXXX X A F C R L V A L I D RESP3 X XXXX X X X RESP4 RSSI[7:0] RESP5 ASNR[7:0] RESP6 X XXXX X X X RESP7 FREQOFF[7:0] Data Bit Name Function 1 3 SNRHINT SNR Detect High. 0 = Received SNR has not exceeded above SNR high threshold. 1 = Received SNR has exceeded above SNR high threshold. 1 2 SNRLINT SNR Detect Low. 0 = Received SNR has not exceeded below SNR low threshold. 1 = Received SNR has exceeded below SNR low threshold. 1 1 RSSIHINT RSSI Detect High. 0 = RSSI has not exceeded above RSSI high threshold. 1 = RSSI has exceeded above RSSI high threshold. 1 0 RSSILINT RSSI Detect Low. 0 = RSSI has not exceeded below RSSI low threshold. 1 = RSSI has exceeded below RSSI low threshold. 2 1 AFCRL AFC Rail Indicator. This bit will be set if the AFC rails. 2 0 VALID Valid Channel. Confirms if the channel is currently valid. 4 7:0 RSSI[7:0] Received Signal Strength Indicator. This byte will contain the receive signal strength at the tuned frequency. 5 7:0 SNR[7:0] SNR. This byte will contain the SNR metric at the tuned frequency. 7 7:0 FREQOFF[7:0] Frequency Offset. Signed frequency offset in kHz.
186 Rev. 1.0 Command 0x54. WB_SAME_STATUS Retrieves SAME information, acknow ledges SAMEINT interrupts and clears the message buffer. The command indicates whether the start of message, end of message or pr eamble is detected and if the header buffer is ready. The state of the decoder, message length, and 8 bytes of the message buffer with corresponding confidence level is returned. The byte at ad dress 0 will be the first byte following the header block identifier "ZCZC", typically "-" (Dash). Each byte has an associated confidence metric ranging from 0 (low confidence) to 3 (high confidence). Available in: Si4707 Command Arguments: Two Response Bytes: Thirteen Command B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 01010100 ARG1 000000 C L R B U F I N T A C K ARG2 READADDR[7:0] Arg Bit Name Function 1 7:2 Reserved Always write to 0. 1 1 CLRBUF Clear Buffer 0 = Message Buffer preserved. 1 = Clears the contents of the SAME Message Buffer. Clears the contents of the SAME Message Buffer if set. The buffer will always be cleared during WB_TUNE_FREQ. If the buffer is not cleared then each message received will be combined with the previously received mes- sage to increase the certainty of the message content. After receipt of an End-of-Message, this buffer must be cleared by the user. To prevent different headers from being combined into an incorrect message, the user must clear the buffer before a new header is transmitted. As there is no indication that a new header is about to be transmitted, the user must rely on other events to indicate when to clear the buffer. The buffer should be cleared after receipt of three headers, after the end-of-message marker, when the 1050 Hz alert tone has been detected or 6 seconds after the reception of the last header was completed and no new preamble has been detected. Once the buffer has been cleared, it will remain empty until the next start-of-message is received. Alternatively, the user may clear the buffer after each header is received and rely on a traditional best 2-of-3 voting method. In this case, no message combining is performed. 0 = Interrupt status preserved. 1=C l e a r s S A M E I N T . 2 [7:0] READADDR[7:0] Byte in the message buffer to start reading from. Note that 8 bytes will always be returned, however the WB_SAME_STATUS:MSGLEN will report the total length of the message and the user must disregard bytes past this length.
Rev. 1.0 187 Response B i t D 7D 6D 5D 4 D 3 D 2 D 1 D 0 STATUS CTS ERR X X RSQINT SAMEINT ASQINT STCINT RESP1 XXXX E O M D E T S O M D E T P R E D E T H D RRDY RESP2 STATE[7:0] RESP3 MSGLEN[7:0] RESP4 CONF7[1:0] CONF6[1:0] CONF5[1:0] CONF4[1:0] RESP5 CONF3[1:0] CONF2[1:0] CONF1[1:0] CONF0[1:0] RESP6 DATA0[7:0] RESP7 DATA1[7:0] RESP8 DATA2[7:0] RESP9 DATA3[7:0] RESP10 DATA4[7:0] RESP11 DATA5[7:0] RESP12 DATA6[7:0] RESP13 DATA7[7:0] RESP Bit Name Function 1 3 EOMDET End Of Message Detected 1 = End of message is detected. 1 2 SOMDET Start Of Message Detected 1 = start of message is detected. 1 1 PREDET Preamble Detected 1 = Preamble is detected. 1 0 HDRRDY Header Buffer Ready 1 = Header buffer is ready. 2 [7:0] STATE[7:0] State Machine Status 0 = End of message. 1 = Preamble detected. 2 = Receiving SAME header message. 3 = SAME header message complete. 3 [7:0] MSGLEN[7:0] SAME Message Length SAME Message length in bytes. This length excludes the preamble and the header code block identifier "ZCZC". If message combining is used, the value reported is the length of the longest message received.
188 Rev. 1.0 4 [7:6] CONF7[1:0] Confidence Metric for DATA7 represented as a number between 0 (low) and 3 (high). 4 [5:4] CONF6[1:0] Confidence Metric for DATA6 represented as a number between 0 (low) and 3 (high). 4 [3:2] CONF5[1:0] Confidence Metric for DATA5 represented as a number between 0 (low) and 3 (high). 4 [1:0] CONF4[1:0] Confidence Metric for DATA4 represented as a number between 0 (low) and 3 (high). 5 [7:6] CONF3[1:0] Confidence Metric for DATA3 represented as a number between 0 (low) and 3 (high). 5 [5:4] CONF2[1:0] Confidence Metric for DATA2 represented as a number between 0 (low) and 3 (high). 5 [3:2] CONF1[1:0] Confidence Metric for DATA1 represented as a number between 0 (low) and 3 (high). 5 [1:0] CONF0[1:0] Confidence Metric for DATA0 represented as a number between 0 (low) and 3 (high). 6 [7:0] DATA0[7:0] Byte of message read at address, READADDR + 0 7 [7:0] DATA1[7:0] Byte of message read at address, READADDR + 1 8 [7:0] DATA2[7:0] Byte of message read at address, READADDR + 2 9 [7:0] DATA3[7:0] Byte of message read at address, READADDR + 3 10 [7:0] DATA4[7:0] Byte of message read at address, READADDR + 4 11 [7:0] DATA5[7:0] Byte of message read at address, READADDR + 5 12 [7:0] DATA6[7:0] Byte of message read at address, READADDR + 6 13 [7:0] DATA7[7:0] Byte of message read at address, READADDR + 7 RESP Bit Name Function
Rev. 1.0 189 Command 0x55. WB_ASQ_STATUS Returns status information about the 1050kHz alert tone in Weather Band. The commands returns the alert on/off Interrupt and the present state of the alert tone. The command clears the ASQINT bit when INTACK bit of ARG1 is set. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Available in: All Command arguments: One Response bytes: Two Command Response B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 01010101 ARG1 0000000 I N T A C K Arg Bit Name Function 1 7:1 Reserved Always write to 0. 0 = Interrupt status preserved. 1 = Clears ASQINT, ALERTOFF_INT, ALERTON_INT Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT SAMEINT ASQINT STCINT RESP1 X X X X X X ALERTOFF_INT ALERTON_INT RESP2 XX X X X X X A L E R T
190 Rev. 1.0 Command 0x57. WB_AGC_STATUS Returns the AGC setting of the device. The command returns whether the AGC is enabled or disabled. This command may only be sent when in powerup mode. Available in: All Command arguments: None Response bytes: One Command Response Data Bit Name Function 1 1 ALERTOFF_INT ALERTOFF_INT. 0 = 1050 Hz alert tone has not been detected to be absent since the last WB_TUNE_FREQ or WB_RSQ_STATUS with INTACK = 1. 1 = 1050 Hz alert tone has been detected to be absent since the last WB_TUNE_FREQ or WB_RSQ_STATUS with INTACK = 1. 1 0 ALERTON_INT ALERTON_INT. 0 = 1050 Hz alert tone has not been detected to be present since the last WB_TUNE_FREQ or WB_RSQ_STATUS with INTACK = 1. 1 = 1050 Hz alert tone has been detected to be present since the last WB_TUNE_FREQ or WB_RSQ_STATUS with INTACK = 1. 2 0 ALERT ALERT. 0 = 1050 Hz alert tone is currently not present. 1 = 1050 Hz alert tone is currently present. B i tD 7 D 6D 5D 4D 3D 2D 1D 0 CMD 0 1010111 Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT SAMEINT ASQINT STCINT RESP1 X X X X X X X READ_RFAGCDIS RESP Bit Name Function 1 0 READ_RFAGCDIS This bit indicates whether the RF AGC is disabled or not 0 = RF AGC is enabled. 1 = RF AGC is disabled.
Rev. 1.0 191 Command 0x58. WB_AGC_OVERRIDE Overrides AGC setting by disabling the AGC and forcing the LNA to have a certain gain that ranges between 0 (minimum attenuation) and 26 (maximum attenuation). This command may only be sent when in powerup mode. Available in: All Command arguments: One Response bytes: None Command Response B i tD 7 D 6D 5D 4D 3D 2D 1 D 0 CMD 0 101100 0 ARG1 X XXXXXX R F A G C D I S ARG Bit Name Function 1 7:1 Reserved Always write to 0. 1 0 RFAGCDIS This bit selects whether the RF AGC is disabled or not 0 = RF AGC is enabled. 1 = RF AGC is disabled. B i tD 7 D 6D 5D 4D 3D 2D 1D 0 STATUS CTS ERR X X RSQINT SAMEINT ASQINT STCINT
192 Rev. 1.0 Command 0x80. GPIO_CTL Enables output for GPO1, 2, and 3. GPO1, 2, and 3 can be configured for output (Hi-Z or active drive) by setting the GPO1OEN, GPO2OEN, and GPO3OEN bit. The state (h igh or low) of GPO1, 2, and 3 is set with the GPIO_SET command. To avoid excessive current consumption due to oscillation, GPO pins should not be left in a high impedance state. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. The default is all GPO pins set for high impedance. Notes: 1. The use of GPO2 as an inte rrupt pin will override this GPIO_CTL function for GPO2. 2. GPO1 is not configurable as an output for Si4740/41/42/43/44/45. Available in: All Command arguments: One Response bytes: None Command Response B i t D 7D 6D 5D 4D 3D 2D 1D 0 CMD 10000000 ARG1 0 0 0 0 GPO3OEN GPO2OEN GPO1OEN 0 ARG Bit Name Function 1 7:4 Reserved Always write 0. 1 3 GPO3OEN GPO3 Output Enable. 0 = Output Disabled (Hi-Z) (default). 1 = Output Enabled. 1 2 GPO2OEN GPO2 Output Enable. 0 = Output Disabled (Hi-Z) (default). 1 = Output Enabled. 1 1 GPO1OEN GPO1 Output Enable. 0 = Output Disabled (Hi-Z) (default). 1 = Output Enabled. 1 0 Reserved Always write 0. B i t D 7D 6D 5 D 4 D 3 D 2 D 1 D 0 STATUS CTS ERR X X RSQINT SAMEINT ASQINT STCINT
Rev. 1.0 193 Command 0x81. GPIO_SET Sets the output level (high or low) for GPO1, 2, and 3. GP O1, 2, and 3 can be configured for output by setting the GPO1OEN, GPO2OEN, and GPO3OEN bit in the GPIO_CTL command. To avoid excessive current consumption due to oscillation, GPO pins should not be left in a high impedance state. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This prop erty may only be set or read when in powerup mode. The default is all GPO pins set for high impedance. Available in: All Command arguments: One Response bytes: None Command Response B i t D 7 D 6D 5D 4 D 3 D 2 D 1 D 0 CMD 1 0 0 0 000 1 ARG1 0 0 0 0 GPO3LEVEL GPO2LEVEL GPO1LEVEL 0 ARG Bit Name Function 1 7:4 Reserved Always write 0. 1 3 GPO3LEVEL GPO3 Output Level. 0 = Output low (default). 1 = Output high. 1 2 GPO2LEVEL GPO2 Output Level. 0 = Output low (default). 1 = Output high. 1 1 GPO1LEVEL GPO1 Output Level. 0 = Output low (default). 1 = Output high. 1 0 Reserved Always write 0. B i t D 7D 6D 5 D 4 D 3 D 2 D 1 D 0 STATUS CTS ERR X X RSQINT SAMEINT ASQINT STCINT
194 Rev. 1.0 5.4.2. WB Receiver Properties Property 0x0001. GPO_IEN Configures the sources for the GPO2/IRQ interrupt pin. Valid sources are the lower 8 bits of the STATUS byte, including CTS, ERR, RSQINT, SAMEINT (Si4707 only), ASQ INT, and STCINT bits. The corresponding bit is set before the interrupt occurs. The CTS bit (and optional interr upt) is set when it is safe to send the next command. The CTS interrupt enable (CTSIEN) can be set with this property and the POWER_UP command. The state of the CTSIEN bit set during the POWER_UP command can be read by reading the this property and modified by writing this property. This command may only be sent when in powerup mode. Errata:RSQIEN is non-functional on WB component 2.0. Available in: All Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0000 RSQREP SAMEREP ASQREP STCREP CTSIEN ERRIEN RSQIEN SAMEIEN ASQIEN STCIEN Bit Name Function 15:12 Reserved Always write to 0. RSQ Interrupt Repeat. 0 = No interrupt generated when RSQINT is already set (default). 1 = Interrupt generated even if RSQINT is already set.
10 SAMEREP
SAME Interrupt Repeat (Si4707 Only). 0 = No interrupt generated when SAMEINT is already set (default). 1 = Interrupt generated even if SAMEINT is already set. 9A S Q R E P ASQ Interrupt Repeat. 0 = No interrupt generated when ASQINT is already set (default). 1 = Interrupt generated even if ASQINT is already set. STC Interrupt Repeat. 0 = No interrupt generated when STCINT is already set (default). 1 = Interrupt generated even if STCINT is already set. 7C T S I E N CTS Interrupt Enable. After PowerUp, this bit will reflect the CTSIEN bit in ARG1 of PowerUp Command. 0 = No interrupt generated when CTS is set. 1 = Interrupt generated when CTS is set. ERR Interrupt Enable. 0 = No interrupt generated when ERR is set (default). 1 = Interrupt generated when ERR is set. 5:4 Reserved Always write to 0.
Rev. 1.0 195 Property 0x0102. DIGITAL_OUTPUT_FORMAT Configures the digital audio output format. Configuration options include DCLK edge, data format, force mono, and sample precision. Available in: Si4737/39/43 Default: 0x0000 Note: DIGITAL_OUTPUT_FORMAT is supported in WBRX component 3.0 or later. 3R S Q I E N RSQ Interrupt Enable 0 = No interrupt generated when RSQINT is set (default). 1 = Interrupt generated when RSQINT is set.
2 SAMEIEN
SAME Interrupt Enable (Si4707 Only). 0 = No interrupt generated when SAMEINT is set (default). 1 = Interrupt generated when SAMEINT is set. 0 = No interrupt generated when ASQINT is set (default) 1 = Interrupt generated when ASQINT is set 0S T C I E N Seek/Tune Complete Interrupt Enable. 0 = No interrupt generated when TCINT is set (default) 1 = Interrupt generated when TCINT is set B i t 1 51 41 31 21 11 098 7 6543 2 1 0 Name 000000 0 0O F A L L O M O D E [ 3 : 0 ]O M O N O O S I Z E [ 1 : 0 ] Bit Name Function 15:8 Reserved Always write to 0. 7O F A L L Digital Output DCLK Edge. 0 = use DCLK rising edge 1 = use DCLK falling edge 6:3 OMODE[3:0] Digital Output Mode. 0000 = I2S 0110 = Left-justified 1000 = MSB at second DCLK after DFS pulse 1100 = MSB at first DCLK after DFS pulse 2O M O N O Digital Output Mono Mode. 0 = Use mono/stereo blend (per blend thresholds) 1 = Force mono 1:0 OSIZE[1:0] Digital Output Audio Sample Precision. 0 = 16-bits 1 = 20-bits 2 = 24-bits 3=8 - b i t s Bit Name Function
196 Rev. 1.0 Property 0x0104. DIGITAL_OUTPUT_SAMPLE_RATE Enables digital audio output and configures digital audio output sample rate in samples per second (sps). When DOSR[15:0] is 0, digital audio output is disabled. The over-sampling rate must be set in order to satisfy a minimum DCLK of 1 MHz. To enable digital audio output, program DOSR[15:0] with the sample rate in samples per second. The system controller must establish DCLK and DFS prior to enabling the digital audio output else the device will not respond and will require reset. The sample rate must be set to 0 before the DCLK/DFS is removed. WB_TUNE_FREQ command must be sent after the POWER_UP command to start the internal clocking before setting this property. Note: DIGITAL_OUPTUT_SAMPLE_RATE is supported in WBRX component 3.0 or later. Available in: Si4737/39/43 Default: 0x0000 (digital audio output disabled) Units: sps Range: 32–48 ksps, 0 to disable digital audio output B i t 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 Name DOSR[15:0] Bit Name Function 15:0 DOSR[15:0] Digital Output Sample Rate. 32–48 ksps. 0 to disable digital audio output.
or reconfigured at other times. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. The default is 32768 Hz. Table 20. RCLK Gaps
198 Rev. 1.0 Property 0x0202. REFCLK_PRESCALE Sets the number used by the prescaler to divide the external RCLK down to the internal REFCLK. The range may be between 1 and 1023 in 1 unit steps. For example, an RCLK of 13MHz would require a prescaler value of 400 to divide it to 32500 Hz. The reference clock frequency property would then need to be set to 32500 Hz. The RCLK must be valid 10 ns before and 10 ns after completing the WB_TUNE_FREQ command. In addition, the RCLK must be valid at all times when the carrier is enabled for proper AFC operation. The RCLK may be removed or reconfigured at other times. The CTS bit (and optional interr upt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. The default is 1. Available in: All Default: 0x0001 Step: 1 Range: 1-4095 Bit Name Function 15:0 REFCLKF[15:0] Frequency of Reference Clock in Hz. The allowed REFCLK frequency range is between 31130 and 34406 Hz (32768 5%), or 0 (to disable AFC). B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 000 RCLK SEL REFCLKP[11:0] Bit Name Function 15:13 Reserved Always write to 0. 12 RCLKSEL RCLKSEL. 0 = RCLK pin is clock source. 1 = DCLK pin is clock source. 11:0 REFCLKP[11:0] Prescaler for Reference Clock. Integer number used to divide clock frequency down to REFCLK frequency. The allowed REFCLK frequency range is between 31130 and 34406 Hz (32768 +/- 5%), or 0 (to disable AFC).
Rev. 1.0 199 Property 0x5108. WB_MAX_TUNE_ERROR Sets the maximum freq error allowed before setting the AFC_RAIL indicator.The CTS bit (and optional interrupt) is set when it is safe to send the next command. This prope rty may only be set or read when in powerup mode. The default is 10 kHz. Available in: All Default: 0x000A Units: kHz Step: 1 Range: 0–15 Property 0x5200. WB_RSQ_INT_SOURCE Configures interrupt related to Received Signal Quality metrics. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0. Available in: All Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name WBMAXTUNEERR[15:0] Bit Name Function 15:0 WBMAXTUNEERR WB Maximum Tuning Frequency Error. Maximum tuning error allowed before setting the AFC Rail Indicator ON. Specified in units of kHz. Default is 10 kHz. B i t D 1 5D 1 4D 1 3D 1 2 D 1 1D 1 0D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name XXXXXX X X X X X X SNRHIEN SNRLIEN RSSIHIEN RSSILIEN
200 Rev. 1.0 Property 0x5201. WB_RSQ_SNR_HI_THRESHOLD Sets high threshold which will trigger the RSQ interrupt if the Audio SNR is above this threshold. The CTS bit (and optional interrupt) is set when it is sa fe to send the next command. This property may only be set or read when in powerup mode. The default is 127 dB. Available in: All Default: 0x007F Units: dB Step: 1 Range: 0-127 Bit Name Function 3 SNRHIEN Interrupt Source Enable: Audio SNR High. Enable SNR high as the source of interrupt which the threshold is set by WB_RSQ_SNR_HI_THRESHOLD. 2 SNRLIEN Interrupt Source Enable: Audio SNR Low. Enable SNR low as the as the source of interrupt which the threshold is set by WB_RSQ_SNR_LO_THRESHOLD. 1 RSSIHIEN Interrupt Source Enable: RSSI High. Enable RSSI high as the source of interrupt which the threshold is set by WB_RSQ_RSSI_HI_THRESHOLD. 0 RSSILIEN Interrupt Source Enable: RSSI Low. Enable RSSI low as the source of interrupt which the threshold is set by WB_RSQ_RSSI_LO_THRESHOLD. B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name SNRH[15:0] Bit Name Function 15:0 SNRH WB RSQ Audio SNR High Threshold. Threshold which will trigger the RSQ interrupt if the Audio SNR is above this threshold. Specified in units of dB in 1 dB steps (0…127). Default is 127 dB.
Rev. 1.0 201 Property 0x5202. WB_RSQ_SNR_LO_THRESHOLD Sets low threshold which will trigger t he RSQ interrupt if the Audio SNR is be low this threshold. The CTS bit (and optional interrupt) is set when it is sa fe to send the next command. This property may only be set or read when in powerup mode. The default is 0 dB. Available in: All Default: 0x0000 Units: dB Step: 1 Range: 0-127 Property 0x5203. WB_RSQ_RSSI_HI_THRESHOLD Sets high threshold which will trigger the RSQ interrupt if the RSSI is abo ve this threshold. The CTS bit (and optional interrupt) is set when it is sa fe to send the next command. This property may only be set or read when in powerup mode. The default is 127 dB. Available in: All Default: 0x007F Units: dBµV Step: 1 Range: 0-127 B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name SNRL[15:0] Bit Name Function 15:0 SNRL WB RSQ Audio SNR Low Threshold. Threshold which will trigger the RSQ interrupt if the Audio SNR is below this threshold. Specified in units of dB in 1 dB steps (0…127). Default is 0 dB. B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name RSSIH[15:0] Bit Name Function 15:0 RSSIH WB RSQ RSSI High Threshold. Threshold which will trigger the RSQ interrupt if the RSSI is above this threshold. Specified in units of dB in 1 dB steps (0…127). Default is 127 dB.
202 Rev. 1.0 Property 0x5204. WB_RSQ_RSSI_LO_THRESHOLD Sets low threshold which will trigger the RSQ interrupt if the RSSI is below this threshold. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0 dB. Available in: All Default: 0x0000 Units: dBµV Step: 1 Range: 0-127 Property 0x5403. WB_VALID_SNR_THRESHOLD Sets the SNR threshold which the WB_RSQ_STATUS and WB_TUNE_STATUS will consider the channel valid if the received SNR is at or above this value. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 3 dB. Available in: All Default: 0x0003 Units: dBµV Step: 1 Range: 0-127 B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name RSSIL[15:0] Bit Name Function 15:0 RSSIL WB RSQ RSSI Low Threshold. Threshold which will trigger the RSQ interrupt if the RSSI is below this threshold. Specified in units of dB in 1 dB steps (0…127). Default is 0 dB. B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name WB_VALID_SNR_THRESHOLD[15:0] Bit Name Function 15:0 WB_VALID_S NR_THRESH OLD WB Valid SNR Threshold. SNR value at or above which WB_RSQ_STATUS and WB_TUNE_STATUS will consider the channel VALID. Specified in units of dB in 1 dB steps (0…127). Default is 3d B .
Rev. 1.0 203 Property 0x5404. WB_VALID_RSSI_THRESHOLD Sets the RSSI threshold which the WB_RSQ_STATUS and WB_TUNE_STATUS will consider the channel valid if the received RSSI is at or above this value. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 20 dB. Available in: All Default: 0x0014 Units: dBµV Step: 1 Range: 0-127 Property 0x5500. WB_SAME_INTERRUPT_SOURCE Configures the SAME interrupt sources. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0. Available in: Si4707 Default: 0x0000 B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name WB_VALID_RSSI_THRESHOLD [15:0] Bit Name Function 15:0 WB_VALID_RSSI_ THRESHOLD WB Valid RSSI Threshold. RSSI value at or above which WB_RSQ_STATUS and WB_TUNE_STATUS will consider the channel VALID. Specified in units of dB in 1 dB steps (0…127). Default is 20 dB. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 000000 0 0 0000 EOMDET SOMDET PREDET HDRRDY Bit Name Function 15:4 Reserved Always write to 0. 3 EOMDET Enable EOMDET as the source of SAME Interrupt. 2 SOMDET Enable SOMDET as the source of SAME Interrupt. 1 PREDET Enable PREDET as th e source of SAME Interrupt. 0 HDRRDY Enable HDRRDY as the source of SAME Interrupt.
204 Rev. 1.0 Property 0x5600. WB_ASQ_INT_SOURCE Configures interrupt related to the 1050 kHz alert tone. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0. Available in: All Default: 0x0000 Property 0x4000. RX_VOLUME Sets the audio output volume. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 63. Available in: All Default: 0x003F Step: 1 Range: 0-63 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name XXXXXX X X X X X X X X ALERTOFF_IEN ALERTON_IEN Bit Name Function 1 ALERTOFF_IEN Interrupt Source Enable: Alert OFF. Enable 1050 kHz alert tone disappeared as the source of interrupt. 0 ALERTON_IEN Interrupt Source Enable: Alert ON. Enable 1050 kHz alert tone appeared as the source of interrupt. B i t D 1 5D 1 4D 1 3D 1 2D 1 1D 1 0D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name VOL[15:0] Bit Name Function 15:0 VOL Output Volume. Sets the output volume level, 63 max, 0 min. Default is 63.
Rev. 1.0 205 Property 0x4001. RX_HARD_MUTE Mutes the audio output. L and R audio outputs may not be muted independently. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is unmute (0x0000). Available in: All Default: 0x0000 B i t D 1 5D 1 4D 1 3D 1 2D 1 1D 1 0D 9D 8D 7D 6D 5D 4D 3D 2 D 1 D 0 Name 000000 0 0000000 L M U T E R M U T E Bit Name Function 15:2 Reserved Always write to 0. 1 LMUTE Mutes both L and R Audio Outputs. 0 RMUTE Mutes both L and R Audio Outputs.
Si471x data sheet for specific reset timing requirements. device will not accept commands wh ile in powerdown mode, with the e xception of the powerup command. not respond, and a reset is required. control interface; registers are set to their default settings, and the control bus is disabled. respectively. Refer to the Si471x data sheet for timing parameter values. Figure 16. 2-wire Control Interface Read and Write Timing Parameters Table 21. Bus Mode Selection
Figure 17. 2-wire Control Interface Read and Write Timing Diagram SDIO low on the next falling edge of SCLK. unpredictable device behavior. transaction. These bytes contain the status byte and response data from the device. A 2-wire transaction ends with the STOP condition, which occurs when SDIO rises while SCLK is high. wire bus mode. In this example the TX_TUNE_FREQ command is demonstrated. Table 22. Command and Response Procedure - 2-Wire Bus Mode 0x80 Reply Status. Clear-to-send high.
208 Rev. 1.0 To send the TX_TUNE_FREQ command and arguments, the system controller sends the START condition, followed by the 8-bit control word, which consis ts of a seven-bit device address (0010001b SEN = 0 or 1100011b SEN = 1) and the write bit (0b) indicated by AD DR+W = 00100010b = 0x22. In this example, SEN = 0 resulting in the control word ADDR+W = 00100010b = 0x22. If instead SEN = 1, the resulting control word would be ADDR+W = 11000110b = 0xC6. The device acknowledges the control word by setting SDIO = 0, indicated by ACK = 0. The system controller then sends the CMD byte , 0x30, and again the device acknowledges by setting ACK = 0. The system controller and device repeat this process for the ARG1, ARG2, and ARG3 bytes. Commands may take up to seven argument byte s, and this flexibility should be designed into the 2-wire bus mode implementation. Alternatively, all seven argument byte s may be sent for all commands, but unusual arguments must be 0x00. Unpredictable device behavior will result if more than seven arguments are sent. To read the status and response from the device, the system controller sends the START condition, followed by the eight-bit control word, which consists of the seven bi t device address and the read bit (1b). In this example, SEN = 0 and the write control word is ADDR+R = 00100011b = 0x23. If SEN = 1, the write control word would be ADDR+R = 11000111b = 0xC7. The device acknowledges the control word by setting ACK = 0. Next the system controller reads the STATUS byte. In this example, the STATUS byte is 0x00, indicating that the CTS bit, bit 8, has not been set. The response bytes are not ready for reading and that the device is not ready to accept another command. The system controller sets SDIO = 1, indicated by NACK = 1, to signal to the device the 2-wire transfer will end. The system cont roller should set the STOP cond ition. This process is rep eated until the STATUS byte indicates that CTS bit is set, 0x80 in this example. When the STATUS byte returns CTS bit set, 0x80 in th is example, the system controller may read the response bytes from the device. The controller sets ACK = 0 to indicate to the device that additi onal bytes will be read. The RESP1 byte is read by the system controller, followed by the system controller se tting ACK = 0. This is repeated for RESP2. RESP3 is read by the system controller followed by the system controller setting NACK = 1, indicating that RESP3 is the last byte to be read. The system controller then sets the STOP condition. Responses may be up to 15 bytes in length (RESP1–RESP15) depending on the command. It is acceptable to read all 15 response bytes. However, unused response bytes return random data and must be ignored. Note that the TX_TUNE_FREQ command returns only the STATUS byte and response bytes are shown only for completeness. START ADDR+W ACK CMD ACK ARG1 ACK ARG2 ACK ARG3 ACK STOP START 0x22 00 x 3 0 00 x 0 0 00 x 2 7 00 x 7 E 0S T O P START ADDR+R ACK STATUS NACK STOP START 0x23 0 0x00 1 STOP START ADDR+R ACK STATUS ACK RESP1 ACK RESP2 ACK RESP3 NACK STOP START 0x23 0 0x80 0 0x00 0 0x00 0 0x00 1 STOP
wire bus mode. In this example the TX_TUNE_FREQ command is demonstrated. Table 23. Register Map for 3-Wire Mode Table 24. Command and Response Procedure - 3-Wire Bus Mode STATUS 0x80 Reply Status. Clear-to-send high.
Rev. 1.0 211 To send the TX_TUNE_FREQ command and arguments, the system controller sets SEN = 0. Next, the controller drives the 9-bit control word on SD IO, consisting of the device address (A7:A5 = 101b), the write bit (0b), the device address (A4 = 0), and the register address for the COMMAND2 register (A3:A0 = 0001b). The control word is followed by a 16-bit data word, consisting of ARG2 followed by ARG3. The system controller then sets SEN =1 and pulses the SCLK high and then low one final time . For commands requiring additional arguments, in the COMMAND3 (ARG3, ARG4) and COMMAND 4 (ARG5, ARG6) registers, the system controller would send these next. Next the system controller initiates the command by setting SEN = 0 and driving the 9-bit control word on SDIO, consisting of the device address (A7:A5 = 101b), the writ e bit (0b), the device address (A4 = 0), and the register address for the COMMAND1 register (A3:A0 = 0000b). Th e control word is followed by a 16-bit data word, consisting of the CMD byte followed by ARG1 byte. The system controller then sets SEN = 1 and pulses the SCLK high and then low one final time. To read the status and response from the device, the system controller sets SEN= 0. Next, the controller drives the 9-bit control word 101101000b on SDIO, consisting of th e device address (A7:A5 = 101b), the read bit (1b), the device address (A4 = 0), and the regi ster address for the STATUS/RESPON SE1 register (A3:A0 = 1000b). The control word is followed by a 16-bit data word, c onsisting of STATUS followed by RESPONSE1. The system controller then sets SEN = 1 and pulses the SCLK high and then low one final time. In this example, the STATUS byte is 0x00, indicating that the CTS bit, bit 8, has not been set and that the response bytes are not ready for reading and that the device is not ready to accept another command. RESP1 will be ra ndom until the CTS bit is set. This process should be repeated until the STATUS byte indicates that CTS bit is set, 0x80 in this example. When the STATUS byte indicates that the CTS bit has been set, 0x80 in this example, the system controller may read the RESPONSE bytes from the device in any order. SEN CTL ARG2 ARG3 SEN SCLK 1 0 101000001b 0x27 0x7E 0 1P u l s e SEN CTL CMD ARG1 SEN SCLK 1 0 101000000b 0x30 0x00 0 1P u l s e SEN CTL STATUS RESP1 SEN SCLK 1 0 101101000b 0x00 0x00 0 1P u l s e SEN CTL STATUS RESP1 SEN SCLK 1 0 101101000b 0x80 0x00 0 1P u l s e
Figures 20 and 21 show the SPI Control Interface Read and Write Timing Parameters and Diagrams, respectively. Refer to the Si471x data sheet for timing parameter values. Figure 20. SPI Control Interface Write Timing Parameters Figure 21. SPI Control Interface Read Timing Parameters SEN = 0. The system controller then pulses SCLK eight times, while driving an 8-bit control byte serially on SDIO. after the control byte. The data is captured by the device on the rising edge of SCLK.
16 Data Bytes Out
specified) on the falling edge of SCLK. Data must be captured by the system controller on the rising edge of SCLK. toggling SCLK high and then low. Commands will be ignored by the device if the transaction is aborted. controller to use the SPI bus mode. In this example the TX_TUNE_FREQ command is demonstrated. STATUS byte indicates that CTS bit is set, 0x80 in this example. RESP1–RESP15 bytes are shown only for completeness. Table 25. Command and Response Procedure - SPI Bus Mode 0x80 Reply Status. Clear-to-send high.
written from the system controller to the device.
- Supply VDD and VIO while keeping the RST = 0.
Power supplies may be sequenced in any order. is in the VIO supply domain and therefore RST = 0 must be maintained before VIO is supplied.
- Set GPO1 and GPO2 for the desired bus mode.
controller and 100 µs if the internal 1 M resistor is allowed to set the default GPO1 (high) and GPO2 (low).
- Write POWER_UP to the command register.
carrier is enabled. The RCLK may be removed or reconfigured when the carrier is disabled. Figure 22. Device Power Up Timing
- Send the POWER_UP command by writing the CMD field with value 0x01.
- Send argument 1 of the power up command 0x02 (no patch, CTS and GPO2 interrupts disabled, FM transmit
Section “5. Commands and Properties”.
- Send argument 2 of the power up command 0x50 (analog input selected)
- Poll the CTS bit until it has been set high, or until a CT S interrupt is received if CTS interrupt is enabled.
- Send the POWER_UP command by writing the CMD field with value 0x01.
- Send ARG1, 0x00 (no patch, CTS and GPO2 interrupt s disabled, FM receive selected). Optionally various
- Send ARG2, 0x05 (analog output is selected)
- Poll the CTS bit until it has been set high, or until a CT S interrupt is received (if CTS interrupt is enabled).
- Send the POWER_UP command by writing the CMD field with value 0x01.
- Send ARG1, 0x01 (no patch, CTS and GPO2 interrupt s disabled, AM/SW/LW receive selected). Optionally
various interrupts such as the CTS interrupt can be enabled by varying this argument, see Section “5.
- Send ARG2, 0x05 (analog output selected)
- Poll the CTS bit until it has been set high, or until a CT S interrupt is received (if CTS interrupt is enabled).
Table 26. Using the POWER_UP Command for the FM Transmitter ARG1 0x02 Set to FM Transmit. ARG2 0x50 Set to Analog Line Input. RESP1 0x80 Reply Status. Clear-to-send high. Table 27. Using the POWER_UP command for the FM Receiver ARG1 0x00 Set to FM Receive. ARG2 0x05 Set to Analog Out. 0x80 Reply Status. Clear-to-send high. Table 28. Using the POWER_UP Command for the AM/SW/LW Receiver ARG1 0x01 Set to AM/SW/LW Receive. ARG2 0x05 Set to Analog Out. 0x80 Reply Status. Clear-to-send high.
- Send the POWER_UP command by writing the CMD field with value 0x01.
- Send ARG1, 0x03 (no patch, CTS and GPO2 interrupts disabled, weather band receive selected). Optionally
various interrupts such as the CTS interrupt can be enabled by varying this argument. See Section “5.
- Send ARG2, 0x05 (analog output selected).
- Poll the CTS bit until it has been set high or until a CTS interrupt is received (if CTS interrupt is enabled).
and cannot be generated by customers. receiving programmed parts). customer to use a tag when downloading to allow the Si47xx to decrypt the patch. through 35 summarize the library and firmware mapping and compatibility. Table 29. Using the POWER_UP Command for the FM Transmitter ARG1 0x03 Set to Weather Band Receive. ARG2 0x05 Set to Analog Out. STATUS 0x80 Reply Status. Clear-to-send high. Table 30. Si4704/05 Firmware, Library, and Component Compatibility
Table 31. Si4706 Firmware, Library, and Component Compatibility Table 32. Si4707 Firmware, Library, and Component Compatibility Table 33. Si4710/11/12/13 Firmware, Library, and Component Compatibility Table 34. Si4720/21 Firmware, Library, and Component Compatibility Table 35. Si4730/31 Firmware, Library, and Component Compatibility Table 36. Si4740/41/42/43/44/45 Firmware, Library, and Component Compatibility
Table 37. Si4749 Firmware, Library, and Component Compatibility Table 38. Si4734/35 Firmware, Library, and Component Compatibility Table 39. Si4736/37 Firmware, Library, and Component Compatibility Table 40. Si4738/39 Firmware, Library, and Component Compatibility Table 41. Si4784/85 Firmware, Library, and Component Compatibility
Rev. 1.0 219 7.2.2. Patching Procedure Patching is accomplished by sending a series of commands to the device. These commands are sent in the same manner as any other device commands and can be sent over any of the command busses (2-wire, 3-wire, SPI). The first command that is sent to the device is the PO WER_UP command to confirm that the patch is compatible with the internal device library revision. The device mo ves into the powerup mode, returns the reply, and moves into the powerdown mode. The POWER_UP command is sent to the device again to configure the mode of the device and additionally is used to start the patching pr ocess. When applying the patch, the PATCH bit in ARG1 of the POWER_UP command must be set to 1 to begin the patching process. Once the POWER_UP command is sent and the device is plac ed in patch mode, the patch file can be sent to the device. The patch file typically has a .csg extension. It is formatted into 8 columns, consisting of a leading command (0x15 or 0x16), and 7 arguments. The controlling system must send each line of 8 bytes, wait for a CTS, then send the next set of 8, etc., until the entire patch has been sent. An example showing the first few lines and final line of a patch file is shown below. The patch download mechanism is verified with a c hecksum embedded in the patch download. If the checksum fails, the part issues an error code, ERR (bit 6 of the one byte reply that is available after each 8-byte transfer), and halts. The part must be reset to recover from this error condition. The following is an example of a patch file. # Copyright 2006 Silicon Laboratories, Inc. # Patch generated 21:09 August 09 2006 # fmtx version 0.0 alpha 0x15,0x00,0x0B,0x1D,0xBB,0x14,0xC4,0xA1 0x16,0x98,0x81,0xD9,0x71,0xED,0x0E,0xAC [up to 1979 additional lines] 0x15,0x00,0x00,0x00,0x00,0x00,0x49,0xFD A full memory patch requires 15856 bytes of system controller memory, however, most patches require significantly less memory. In 2-wire mode, a full memory patch do wnload requires approximately 500 ms at a 400 kHz clock rate. The following is an example of the commands requir ed to boot the device from powerdown mode using the patch file in the previous example. The device has completed the boot process when the CTS bit is set high after the last byte in the file is tran sferred and is ready to accept addi tional commands and proceed with normal operation. Table 42 provides an example of using the POWER_UP command with patching enabled. The table is broken into three columns. The first column lists the action taking place: command (CMD), argument (ARG), status (STATUS) or response (RESP). The seco nd column lists the data byte or bytes in hexadecimal that are being sent or received. An arrow preceding the data indicates data being sent from the device to the system controller. The third column describes the action.
Table 42. Example POWER_UP Command with Patching Enabled Set to Read Library ID, Enable Interrupts. Reply Status. Clear-to-send high. Set to FM Transmit, set patch enable, enable interrupts. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high.
- Write TX_TUNE_POWER to the command register to disable the carrier.
the carrier is enabled for proper AGC operation. The RCLK may be removed or reconfigured at other times. reconfigured when the carrier is disabled.
- Write POWER_DOWN to the command register.
Note that all register contents will be lost. Note that RST must be held high for 10 ns after the completion of the POWER_DOWN command. Note that VIO must not be removed without removing VDD. Unexpected device operation may result. Figure 23. Device Power Down Timing Table 43. Using the POWER_DOWN command Reply Status. Clear-to-send high.
the Right Channel is transferred when the DFS is high. high, and the Right Channel is transferred when the DFS is low. cycles after the LSB of each word before the next DFS transition and MSB of the next word. The number of audio bits can be configured for 8, 16, 20, or 24 bits. Figure 24. I2S Digital Audio Format Figure 25. Left-Justified Digital Audio Format Figure 26. DSP Digital Audio Format
1 DCLK 1 DCLK
1 DCLK
digital audio input/output. Note that digital audio is not supported in WB Receiver.
- Property 0x0101: DIGITAL_INPUT_FORMAT
- Property 0x0103: DIGITAL_INPUT_SAMPLE_RATE
- Property 0x0102: DIGITAL_OUTPUT_FORMAT
- Property 0x0104: DIGITAL_OUTPUT_SAMPLE_RATE
- When the device is powered up, the default value for DIGITAL_INPUT_SAMPLE_RATE or
DIGITAL_OUTPUT_SAMPLE_RATE is 0 (disable digital audio in/out).
- User then must supply DCLK and DFS prior to setting the DIGITAL_INPUT_SAMPLE_RATE or
DIGITAL_OUTPUT_SAMPLE_RATE property.
- This procedure can be applied anyti me after the chip is powered up.
- User may also change or disable DCLK/DFS during oper ation. Prior to changing or disabling DCLK/DFS, user
changing or re-enabling DCLK/DFS, user then can set the sample rate property again.
- The property DIGITAL_INPUT_FORMAT and DIGITAL_OU TPUT_FORMAT does not have a condition, thus it
can be set anywhere after power up.
- Failure to provide DCLK and DFS prior to setting the sample rate property may cause the chip to go into an unknown
state and user must reset the chip.
- The DIGITAL_INPUT_SAMPLE_RATE or DIGITAL_OUTPUT_SAMPLE_RATE is the audio sampling rate (DFS rate)
and is valid between 32 kHz and 48 kHz. The following table is a programming example of how to use digital audio. Table 44. Digital Audio Programming Example Action: User can send other commands or properties here. Action: Supply DCLK and DFS. Reply Status. Clear-to-send high.
Reply Status. Clear-to-send high. Action: User can send other commands or properties here. Action: User needs to change or disable DCLK/DFS. Reply Status. Clear-to-send high. Action: User now is allowed to change or disabling DCLK/DFS. Action: DCLK/DFS has been changed or re-enabled. Reply Status. Clear-to-send high. Action: User can send other commands or properties here.
been accepted and execution completed by the part.
- POWER_UP, POWER_DOWN, GET_REV, GET_PROPERTY, GPIO_CTL, GPIO_SET
- On FM Transmitter component: TX_TUNE_STATUS, TX_ASQ_STATUS, TX_RDS_BUFF, TX_RDS_PS
- On FM Receive component: FM_TUNE_STATUS, FM_RSQ_STATUS, FM_RDS_STATUS
- On AM/SW/LW Receive component: AM_TUNE_STATUS, AM_RSQ_STATUS
- On WB Receive component: WB_TUNE_ STATUS, WB_RSQ_STATUS, WB_ASQ_STATUS
The CTS timing model is shown in Figure 27 and the timing parameters for each command are shown in Table 45. Figure 27. CTS Timing Model the GET_INT_STATUS command until the STC bit has been set before sending the next command.
- On FM Transmitter component: TX_TUN E_FREQ, TX_TUNE_POWER, TX_TUNE_MEASURE
- On FM Receive component: FM_TUNE_FREQ, FM_SEEK_START
- On AM/SW/LW Receive componen t: AM_TUNE_FREQ, AM_SEEK_START
- On WB Receive component: WB_TUNE_FREQ
Table 45. Command Timing Parameters for the FM Transmitter
Table 46. Command Timing Parameters for the FM Receiver
- tSTC for FM_TUNE_FREQ / FM_SEEK_START commands is 80 ms on FMRX component 2.0 and earlier.
- tSTC is seek time per channel. Total seek time depends on bandwidth, channel spacing, and number of channels to next
Table 47. Command Timing Parameters for the AM Receiver channel spacing, and number of channels to next valid channel.
Table 48. Command Timing Parameters for the WB Receiver Table 49. Command Timing Parameters for the Stereo Audio ADC Mode
The FM Transmitter audio signal chain involves Audio Dynamic Range Control, Pre-emphasis and Limiter function. Gain = 20 dB relative to an uncompressed transfer function. Figure 30. Audio Dynamic Range Transfer Function threshold and gain is zero, or less, as not to distort or overmodulate.
Note: Limiter is enabled by default. Figure 33. Audio Input Chain
- Set the input line attenuation, line level and audio deviation.
audio source, either 190, 301, 416 or 636 mVPK. Table 50. Line Input Headroom
234 Rev. 1.0 The audio deviation should be set as high as possible, with the constraint that the sum of the audio, pilot and RDS deviation must be 75 kHz or less. Typical settings are 66.25 kHz audio deviation, 6.75 kHz pilot deviation and 2 kHz RDS deviation. Example 1: An application providing a 150 mVPK input to the device on RIN/LIN would set Line Attenuation = 00, resulting in a maximum permissible input level of 190 mVPK on LIN/RIN and an input resistance of 396 k. With 50 µS pre-emphasis and the limiter disabled, the Line Level would be set to 150 mVPK and the source level would be adjusted down by 13.5 dB to 30 mVPK to compensate for pre-emphasis. With the limiter enabled, the input source can be maintained at 150 mVPK, but the line level should be set at 188 mVPK to give 2 dB headroom. Example 2: An application providing a 1 VPK input to the device on RIN/LIN would set Line Attenuation = 11, resulting in a maximum permissible input level of 636 mVPK on LIN/RIN and an input resistance of 60 k. An external series resistor on LIN and RIN inputs of 58 k would create a resistive voltage divider that would keep the maximum line level on RIN/LIN below 509 mVPK to give a 2 dB headroom. With input signal at 509 mVPK, 75 µs pre- emphasis and the limiter enabled, the Line Level can be set to 636 mVPK. 2. Enable the audio dynamic range control In general the greater the sum of threshold and gain, the greater the perceived audio volume. The following examples demonstrate minimal and aggressive compression schemes. When using the audio dynamic range control, care must be taken to configure the device such that the sum of the threshold and gain is zero, or less, as not to distort or overmodulate. In practice, the sum of the threshold and gain will be less than zero to minimize the possibility for distortion. Example 1 (minimal compression): SETPROPERTY: TX_ACOMP_THRESHOLD = –40 dBFS SETPROPERTY: TX_ACOMP_ATTACK_TIME = 5 ms SETPROPERTY: TX_ACOMP_RELEASE_TIME = 100 ms SETPROPERTY: TX_ACOMP_GAIN = 15 dB Example 2 (aggressive compression): SETPROPERTY: TX_ACOMP_THRESHOLD = –15 dBFS SETPROPERTY: TX_ACOMP_ATTACK_TIME = 0.5 ms SETPROPERTY: TX_ACOMP_RELEASE_TIME = 1000 ms SETPROPERTY: TX_ACOMP_GAIN = 5 dB
Rev. 1.0 235 12. Programming Examples This section contains the programming example for each of the function: FM Transmit, FM Receive, AM/SW/LW Receive, and WB Receive. Before each of the example, an overview of how to program the device is shown as a flowchart. Silicon Labs also provides the actual software (example code) and it can be downloaded from mysilabs.com as AN332SW. 12.1. Programming Example for the FM/RDS Transmitter The following flowchart is an overview of how to program the FM/RDS transmitter. RESET CHIP STATE: POWER DOWN CHIP STATE: POWER UP Power Up With Patch? Check Chip Library ID POWER_UP with FUNC=15 (command 0x01) POWER UP with GPO2OEN bit enabled (command 0x01) Library ID Compatible w/ patch? POWER_UP with Patch and GPO2OEN bits enabled (command 0x01) Send Patch Data (command 0x15, 0x16) Yes No Yes No Check Chip/FW/Comp rev GET_REV (command 0x10) Chip/FW/Comp Rev are correct? Contact Silabs For verification No Yes Contact Silabs For verification
236 Rev. 1.0 Set FM Transmit Frequency (command 0x30) Use GET_INT_STATUS (command 0x14) or hardware interrupts until STC bit is set CHIP STATE: TRANSMITTING Set RCLK settings (property 0x0201, 0x0202) Use Interrupt? Use all default Settings? Yes No No Set INT settings (property 0x0001) Yes Set GPO (command 0x80, 0x81) YesUse GPO? No Call TX_TUNE_STATUS with INTACK bit set (command 0x33) Set Transmit Power (command 0x31) Use GET_INT_STATUS (command 0x14) or hardware interrupts until STC bit is set Call TX_TUNE_STATUS with INTACK bit set (command 0x33)
Rev. 1.0 237 Mono/Stereo? Transmit RDS? (Si4711/13/21 only) Enable Stereo components (property 0x2100) Set Pilot Deviation & Freq (property 0x2102, 0x2107) Disable Stereo components (property 0x2100) Stereo Mono Disable RDS components (property 0x2100) Set RDS Deviation (property 0x2103) Enable RDS components (property 0x2100) Set RDS properties (property 0x2C00-0x2C07) Send RDS PS Group Type0 (command 0x36) Send any other RDS Group Type 1-15? Send RDS Group Type 1-15 (command 0x35) Yes No Yes No Set Audio Deviation (property 0x2101)
238 Rev. 1.0 Preemphasis? Enable Preemphasis (property 0x2106) Disable Preemphasis (property 0x2106 = 2) Yes No Compressor? Enable Compressor Settings (property 0x2200-04) Disable Compressor (property 0x2200) Yes No Limiter? Enable Limiter Settings (property 0x2200, 05) Disable Limiter (property 0x2200) Yes No Set FM Transmit Frequency (command 0x30) Set Transmit Power (command 0x31) CHIP STATE: TRANSMITTING Query TX_TUNE_STATUS (command 0x33) Use GET_INT_STATUS (command 0x14) or hardware interrupts until STC bit is set Call TX_TUNE_STATUS with INTACK bit set (command 0x33) Use GET_INT_STATUS (command 0x14) or hardware interrupts until STC bit is set Call TX_TUNE_STATUS with INTACK bit set (command 0x33)
Rev. 1.0 239 Monitor Audio Signal Quality (ASQ)? Set ASQ settings (property 0x2300 - 0x2304) Query TX_ASQ_STATUS (command 0x34) Optional: Mute or Unmute Audio based on ASQ status (property 0x2105) Want to find an empty channel Using RPS? (Si4712/13/2x only) Send TX_TUNE_MEASURE (command 0x32) Do host processing On returned RPS value To find empty channels CHIP STATE: Received (Idle) Set FM Transmit Freq and/or Power CHIP STATE: TRANSMITTING Yes No Yes No LOOP from start_freq to end_freq until DONE Analog/Digital Audio Input? Set ANALOG input settings (0x2104) Digital Analog Enable digital audio by setting DFS sample rate (property 0x0103) Clock must be available on DCLK/DFS pin Set audio format (property 0x0101)
240 Rev. 1.0 Table 51 provides an example of programming for the FM/RDS Transmitter. The table is broken into three columns. The first column lists the action taking place: command (CMD), argument (ARG), status (STATUS) or response (RESP). For SET_PROPERTY commands, th e property (PROP) and property data (PROPD) are indicated. The second column lists the data byte or bytes in hexadecimal that are being sent or received. An arrow preceding the data indicates data being sent from the device to the system controller. The third column describes the action. Note that in some cases the default properties may be acceptable and no modification is necessary. Refer to Section "5. Commands and Properties" on page 7 for a full description of each command and property. Note: If hardware interrupts are required, the GPO2OEN flag (0x40 ARG1) must be set in the POWER_UP command. Change Chip Function To FM Receive? (Si472x only) Send POWER_DOWN (command 0x11) Yes CHIP STATE: POWER DOWN Send POWER_UP For FM Receive (command 0x01) CHIP STATE: POWER UP (FM Receive) Look at FM Receive Flowchart No TRANSMISSION DONE? Yes Send POWER_DOWN (command 0x11) CHIP STATE: POWER DOWN Repeat any of the instructions above after POWER_UP state To change settings No Go back to the very first POWER DOWN state to POWER UP the chip in FM Transmit Need to change DCLK/DFS Rate? (digital only) Disable digital audio by setting DFS sample rate to 0 (property 0x0103) Enable digital audio by setting DFS sample rate (property 0x0103) Yes No Change DCLK/DFS rate or Disable DCLK/DFS DCLK/DFS has been changed or re-enabled
Table 51. Programming Example for the FM/RDS Transmitter (bypass “Powerup in Digital Mode”). Set to FM Transmit. Enable interrupts. Reply Status. Clear-to-send high. Set to FM Transmit. Enable interrupts. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high.
Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Sets Left and Right channel mute. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Sets the pilot or tone generator frequency. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Table 51. Programming Example for the FM/RDS Transmitter (Continued)
Reply Status. Clear-to-send high. Set antenna tuning capacitor to auto. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. STCINT = 1. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. (Compressor) and Limiter” (bypass “Input Settings in Digital Mode”). Action: Ensure that DCLK and DFS are already supplied.
Reply Status. Clear-to-send high. Mode: I2S, stereo, 16bit, sample on rising edge of DCLK. Reply Status. Clear-to-send high. Action: The rest of the programming is the same as analog. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high.
Enable the limiter and compressor. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high.
Enable overmodulation, high and low thresholds. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. ASQINT = 1. checking status. This example assumes no audio input. Reply Status. Clear-to-send high. Set antenna tuning capacitor to auto. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. STCINT = 1. Reply Status. Clear-to-send high. Set antenna tuning capacitor to auto. Reply Status. Clear-to-send high.
Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. STCINT = 1. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high.
Reply Status. Clear-to-send high. Sets RDSD0 (stereo) and RDSMS (music). Reply Status. Clear-to-send high. Sets program service repeat count to 3. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Sets alternative frequency to 87.7 MHz. Reply Status. Clear-to-send high. Sets FIFO size to 3 blocks (value must be one larger than fifo size). Reply Status. Clear-to-send high.
Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high.
Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high.
Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high.
and TX_TUNE_STATUS commands have completed execution. TX_TUNE_STATUS to clear the STC bit after it has been set. Enable (Stereo) LMR, Pilot and RDS. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high.
Rev. 1.0 253 12.2. Programming Example for the FM/RDS Receiver The following is a flowchart showing the overview of how to program the FM/RDS Receiver. RESET CHIP STATE: POWER DOWN CHIP STATE: POWER UP Power Up With Patch? Check Chip Library ID POWER_UP with FUNC=15 (command 0x01) POWER UP with GPO2OEN bit enabled (command 0x01) Library ID Compatible w/ patch? POWER_UP with Patch and GPO2OEN bits enabled (command 0x01) Send Patch Data (command 0x15, 0x16) Yes No Yes No Check Chip/FW/Comp rev GET_REV (command 0x10) Chip/FW/Comp Rev are correct? Contact Silabs For verification No Yes Contact Silabs For verification
254 Rev. 1.0 Set FM Tune Frequency (command 0x20) CHIP STATE: RECEIVING FM Set RCLK settings (property 0x0201, 0x0202) Use Interrupt? Use all default Settings? Yes No No Set INT settings (property 0x0001) Yes Set GPO (command 0x80, 0x81) YesUse GPO? No Which pin is used For the antenna? (Si4706 only) Set FM_ANTENNA_INPUT (property 0x1107 = 1) Set FM_ANTENNA_INPUT (property 0x1107 = 0) LPI pin for embedded (short) antenna FMI pin for headphone (long) antenna Use GET_INT_STATUS (command 0x14) or hardware interrupts Until STC bit is set Call FM_TUNE_STATUS With INTACK bit set (command 0x22) Digital output mode? (Si4706/41/43/45 only) Enable digital audio by setting DFS sample rate (property 0x0104) Yes No Clock must be available on DCLK/DFS pin Set audio format (property 0x0102)
Rev. 1.0 255 Set Deemphasis (property 0x1100) Set Mono/Stereo Blend settings (property 0x1800 – 0x180B) Set M ax Tune Error (property 0x1108) Set Soft M ute Settings (property 0x1301 – 0x1303) Set FM Tune Frequency (command 0x20) CHIP STATE: RECEI VI NG FM Query FM_TUNE_STATUS (command 0x22) Set Vol ume (property 0x4000) Set M ute/U nm ute (property 0x4001) Not applicable to Si4749 Use GET_INT_STATUS (command 0x14) or hardware interrupts Unt i l STC bi t i s set Cal l FM_TUNE_STATUS W ith IN TA C K bit set (command 0x22)
256 Rev. 1.0 Receive RDS? only) Set FM_RDS_INT_SOURCE (property 0x1500) Set FM_RDS_INT_FIFO_COUNT (property 0x1501) Set FM_RDS_CONFIG & enable RDS (property 0x1502) Yes Read RDS data with FM_RDS_STATUS (command 0x24) Received RDS Interrupt or poll RDSINT from GET_INT_STATUS LOOP until RDS FIFO is empty Process RDS data on the host Disable RDS in FM_RDS_CONFIG (property 0x1502) No
Rev. 1.0 257 Monitor Received Signal Quality (RSQ)? Set RSQ settings (property 0x1200 - 0x1207) Query FM_RSQ_STATUS (command 0x23) Optional: Do som ething based on FM_RSQ_STATUS SCAN FM Band For valid channels? Store valid channels In the Host CHIP STATE: RECEIVING FM Yes No Yes No Set SEEK settings (property 0x1400-1404) SEEK next Valid channel? Set SEEK settings (property 0x1400-1404) Send FM_SEEK_START (command 0x21) Yes CHIP STATE: RECEIVING FM No LOOP until reaches end of FM band or back to the original Channel Send FM_SEEK_START (command 0x21) Use GET_INT_STATUS (command 0x14) or hardware interrupts until STC bit is set Call FM_TUNE_STATUS with INTACK bit set (command 0x22)
258 Rev. 1.0 Change Chip Function to AM/SW/LW/WB Receive (Si4740/41/42/ 43/44/45) ? Send POWER_DOWN (command 0x11) Yes CHIP STATE: POWER DOWN Send POWER_UP For FM Transmit or AM/SW/ LW Receive or WB Receive (command 0x01) CHIP STATE: POWER UP (FM Transmit or AM/SW/LW Receive or WB Receive) Look at FM Transmit Or AM/SW/LW Receive Or WB Receive Flowchart No RECEIVE FM DONE? Yes Send POWER_DOWN (command 0x11) CHIP STATE: POWER DOWN Repeat any of the instructions above after POWER_UP state To change settings No Go back to the very first POWER DOWN state to POWER UP the chip in FM Receive Need to change DCLK/DFS Rate? (digital only) Disable digital audio by setting DFS sample rate to 0 (property 0x0104) Change DCLK/DFS rate or Disable DCLK/DFS Enable digital audio by setting DFS sample rate (property 0x0104) DCLK/DFS has been changed or re-enabled Yes No
data being sent from the device to the system controller. The third column describes the action. and Properties” for a full description of each command and property. Table 52. Programming Example for the FM/RDS Receiver Set to FM Receive. Enable interrupts. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Mode: I2S, stereo, 16bit, sample on rising edge of DCLK. Reply Status. Clear-to-send high. Action: Go to Configuration (bypass “Powerup in analog mode” section). The rest of the programming is the same as analog. Set to FM Receive. Enable interrupts. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high.
Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Table 52. Programming Example for the FM/RDS Receiver (Continued)
Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Enable blend, SNR high, SNR low, RSSI high and RSSI low interrupts. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high.Clear-to-send high. Reply Status. Clear-to-send high.
Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high.
Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Set antenna tuning capacitor to auto. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. STCINT = 1. Reply Status. Clear-to-send high.
Reply Status. Clear-to-send high. No blend, SNR high, low, RSSI high or low interrupts. Soft mute is not engaged, no AFC rail, valid frequency. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. STCINT = 1. Reply Status. Clear-to-send high.
(RDSINT) high. Seek/Tune Complete (STCINT) high. Interrupt source: RDS received. RDS Synchronized. No lost data. Block A: 0x40A7 → PI Code: 0x40A7 (KSLB). Interrupt source: RDS received. RDS Synchronized. No lost data. Block A: 0x40A7 → PI Code: 0x40A7 (KSLB).
Interrupt source: RDS received. RDS Synchronized. No lost data. Block A: 0x40A7 → PI Code: 0x40A7 (KSLB). Interrupt source: RDS received. RDS Synchronized. No lost data. Block A: 0x40A7 → PI Code: 0x40A7 (KSLB).
Interrupt source: RDS received. RDS Synchronized. No lost data. Block A: 0x40A7 → PI Code: 0x40A7 (KSLB). Interrupt source: RDS received. RDS Synchronized. No lost data. Block A: 0x40A7 → PI Code: 0x40A7 (KSLB).
Interrupt source: RDS received. RDS Synchronized. No lost data. Block A: 0x40A7 → PI Code: 0x40A7 (KSLB). Interrupt source: RDS received. RDS Synchronized. No lost data. Block A: 0x40A7 → PI Code: 0x40A7 (KSLB).
Interrupt source: RDS received. RDS Synchronized. No lost data. Block A: 0x40A7 → PI Code: 0x40A7 (KSLB). Interrupt source: RDS received. RDS Synchronized. No lost data. Block A: 0x40A7 → PI Code: 0x40A7 (KSLB).
Interrupt source: RDS received. RDS Synchronized. No lost data. Block A: 0x40A7 → PI Code: 0x40A7 (KSLB). Interrupt source: RDS received. RDS Synchronized. No lost data. Block A: 0x40A7 → PI Code: 0x40A7 (KSLB).
Interrupt source: RDS received. RDS Synchronized. No lost data. Block A: 0x40A7 → PI Code: 0x40A7 (KSLB). Interrupt source: RDS received. RDS Synchronized. No lost data. Block A: 0x40A7 → PI Code: 0x40A7 (KSLB).
Interrupt source: RDS received. RDS Synchronized. No lost data. Block A: 0x40A7 → PI Code: 0x40A7 (KSLB). Interrupt source: RDS received. RDS Synchronized. No lost data. Block A: 0x40A7 → PI Code: 0x40A7 (KSLB).
Interrupt source: RDS received. RDS Synchronized. No lost data. Block A: 0x40A7 → PI Code: 0x40A7 (KSLB). Interrupt source: RDS received. RDS Synchronized. No lost data. Block A: 0x40A7 → PI Code: 0x40A7 (KSLB).
FM_TUNE_STATUS, and FM_RSQ_STATUS commands have completed execution. the STC bit after it has been set. Interrupt source: RDS received. RDS Synchronized. No lost data. Block A: 0x40A7 → PI Code: 0x40A7 (KSLB). Reply Status. Clear-to-send high.
Rev. 1.0 275 12.3. Programming Example for the AM/LW/SW Receiver The following flowchart shows an overview of how to program the AM/LW/SW receiver. RESET CHIP STATE: POWER DOWN CHIP STATE: POWER UP Power Up With Patch? Check Chip Library ID POWER_UP with FUNC=15 (command 0x01) POWER UP with GPO2OEN bit enabled (command 0x01) Library ID Compatible w/ patch? POWER_UP with Patch and GPO2OEN bits enabled (command 0x01) Send Patch Data (command 0x15, 0x16) Yes No Yes No Check Chip/FW/Comp rev GET_REV (command 0x10) Chip/FW/Comp Rev are correct? Contact Silabs For verification No Yes Contact Silabs For verification
276 Rev. 1.0 Set AM Tune Frequency (command 0x40) CHIP STATE: RECEIVING AM / SW / LW Digital output mode? (Si4741/43/45 only) Set RCLK settings (property 0x0201, 0x0202) Set DIGITAL output settings (property 0x0102, 0x0104) Use Interrupt? Use all default Settings? Yes No No Set INT settings (property 0x0001) Yes Set GPO (command 0x80, 0x81) YesUse GPO? No Yes No Use GET_INT_STATUS (command 0x14) or hardware interrupts Until STC bit is set Call AM_TUNE_STATUS With INTACK bit set (command 0x42)
Rev. 1.0 277 Set AM_DEEMPHASI S (property 0x3100) Set AM_CHANNEL_FI LTER (property 0x3102) S et S oft M ute S ettings (property 0x3301- 3303) CHI P STATE: R E C E IV IN G A M / S W / LW Quer y AM_TUNE_STATUS (command 0x42) Set Vol ume (property 0x4000) S et M ute/U nm ute (property 0x4001) Set AM Tune Frequency (command 0x40) Use GET_I NT_STATUS (command 0x14) or hardware interrupts U ntil S TC bit is set Cal l AM_TUNE_STATUS W ith IN TA C K bit set (command 0x42)
278 Rev. 1.0 Monitor Received Signal Quality (RSQ)? Set RSQ settings (property 0x3200 - 0x3204) Query AM_RSQ_STATUS (command 0x43) Optional: Do something based on AM_RSQ_STATUS SCAN AM/SW/LW Band For valid channels? Store valid channels In the Host Yes No Yes No LOOP until reaches end of AM band or back to the original channel SEEK next Valid channel? Set SEEK settings (property 0x3400-3404) SEND AM_SEEK_START (COMMAND 0X41) Yes No Set SEEK settings (property 0x3400-3404) Send AM_SEEK_START (command 0X41) CHIP STATE: RECEIVING AM / SW / LW CHIP STATE: RECEIVING AM / SW / LW Use GET_INT_STATUS (command 0x14) or hardware interrupts until STC bit is set Call AM_TUNE_STATUS With INTACK bit set (command 0x42)
Rev. 1.0 279 Change Chip Function To FM Receive or Weather Band? Send POWER_DOWN (command 0x11) Yes CHIP STATE: POWER DOWN Send POWER_UP For FM Receive or Weather Band (command 0x01) CHIP STATE: POWER UP (FM Receive or Weather Band) Look at FM Receive or Weather Band Flowchart No RECEIVE AM / SW / LW DONE? Yes Send POWER_DOWN (command 0x11) CHIP STATE: POWER DOWN Repeat any of the instructions above after POWER_UP state To change settings No Go back to the very first POWER DOWN state to POWER UP the chip in AM / SW / LW Receive
Table 53 provides an example of programming the AM/LW/SW receiver. The table is broken into three columns. data indicates data being sent from the device to the system controller. The third column describes the action. Section “5. Commands and Properties” for a full description of each command and property. Table 53. Programming Example for the AM/LW/SW Receiver Set to AM/LW/SW Receive. Enable interrupts. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. 2S, stereo, 16bit, sample on rising edge of DCLK. Reply Status. Clear-to-send high. Action: Go to Configuration (bypass “Powerup in analog mode” section). The rest of the programming is the same as analog. Set to AM/LW/SW Receive. Enable interrupts. Reply Status. Clear-to-send high.
Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Table 53. Programming Example for the AM/LW/SW Receiver (Continued)
Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high.
Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high.
Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. STCINT = 1. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. STCINT = 1. Reply Status. Clear-to-send high. Value the antenna tuning capacitor is set to. Reply Status. Clear-to-send high. No SNR high, low, RSSI high, or low interrupts. Reply Status. Clear-to-send high.
Rev. 1.0 285 The device sets the CTS bit (and optional interrupt) to in dicate that it is ready to accept the next command. The CTS bit also indicates that the POWER_UP, GET_REV, POWER_DOWN, GET_PROPERTY, GET_INT_STATUS, AM_TUNE_STATUS, and AM_RSQ_STATUS commands have completed execution. When performing a AM_TUNE_FREQ or AM_SEEK_START CTS will indicate that the device is ready to accept the next command even though the operation is not comple te. GET_INT_STATUS or hardware interrupts should be used to query for the STC bit to be set prior to performing other commands. Use AM_TUNE_STATUS to clear the STC bit after it has been set. 12.4. Programming Example for the WB/SAME Receiver The following flowchart is an overview of how to program the WB (Weather Band) Receiver. RESET CHIP STATE: POWER DOWN CHIP STATE: POWER UP Power Up With Patch? Check Chip Library ID POWER_UP with FUNC=15 (command 0x01) POWER UP with GPO2OEN bit enabled (command 0x01) Library ID Compatible w/ patch? POWER_UP with Patch and GPO2OEN bits enabled (command 0x01) Send Patch Data (command 0x15, 0x16) Yes No Yes No Check Chip/FW/Comp rev GET_REV (command 0x10) Chip/FW/Comp Rev are correct? Contact Silabs For verification No Yes Contact Silabs For verification
286 Rev. 1.0 Set WB Tune Frequency (command 0x50) CHIP STATE: RECEIVING WB Set RCLK settings (property 0x0201, 0x0202) Use Interrupt? Use all default Settings? Yes No No Set INT settings (property 0x0001) Yes Set GPO (command 0x80, 0x81) YesUse GPO? No Use GET_INT_STATUS (command 0x14) or hardware interrupts until STC bit is set Call WB_TUNE_STATUS with INTACK bit set (command 0x52)
Rev. 1.0 287 Set WB Max Tune Error (property 0x5108) Set W B Tune Frequency (command 0x50) CHI P STATE: RECEI VI NG WB Query WB_TUNE_STATUS (command 0x52) Set Vol ume (property 0x4000) S et M ute/U nm ute (property 0x4001) Set WB Val i d SNR Threshol d (property 0x5403) S et W B V alid R S S I Threshol d (property 0x5404) Use GET_I NT_STATUS (command 0x14) or hardw are interrupts until STC bi t i s set Cal l WB_TUNE_STATUS w ith IN TAC K bit set (command 0x52)
288 Rev. 1.0 Monitor Received Signal Quality (RSQ)? Set RSQ settings (property 0x5200 - 0x5204) Query WB_RSQ_STATUS (command 0x53) Optional: Do something based on WB_RSQ_STATUS Yes No Monitor Alert Tone (ASQ)? Set ASQ int source (property 0x5600) Query WB_ASQ_STATUS (command 0x55) Optional: Do something based on WB_ASQ_STATUS Yes No Monitor SAME? Set SAME int source (property 0x5500) Query WB_SAME_STATUS (command 0x54) Optional: Do something based on WB_SAME_STATUS Yes No Comlete Message Received? No Yes
Rev. 1.0 289 Change Chip Function To AM or FM? Send POWER_DOWN (command 0x11) Yes CHIP STATE: POWER DOWN Send POWER_UP For AM or FM Receive (command 0x01) CHIP STATE: POWER UP (AM or FM Receive) Look at AM or FM Receive Flowchart No RECEIVE WB DONE? Yes Send POWER_DOWN (command 0x11) CHIP STATE: POWER DOWN Repeat any of the instructions above after POWER_UP state To change settings No Go back to the very first POWER DOWN state to POWER UP the chip in WB Receive
290 Rev. 1.0 For detailed information on SAME processing, please refer to the following flow chart: Set GPO_IEN for SAME and ALERT Tone Interrupts = 0x06 Start Configure SAME Interrupts for HDR_RDY, EOM_DET, and PRE_DET WB_SAME_INTERRUPT Source = 0x0B Tune to WB Channel WB_TUNE_FREQ Disable Timer Set HDR_COUNT = 0 Check Interrupt Status GET_INT_STATUS SAME_INT or ASQ_INT = 1? TIMER > 6 SEC? Clear SAME buffer, Disable timer, and SET_HDR.COUNT = 0 INT TYPE? Call WB_SAME_STATUS INT_ACK = 1 EOM_DET = 1? PRE_DET = 1? HDR_RDY = 1 at this point Increment HDR_COUNT Get Message and Process WB_SAME_STATUS HDR_COUNT = 3? Reset Timer Yes No Yes Yes Yes No Yes No No No Message Length /8 SAME_INT ASQ_INT
data being sent from the device to the system controller. The third column describes the action. Section “5. Commands and Properties” for a full description of each command and property. Table 54. Programming Example for the WB/SAME Receiver Set to weatherband receive. Enable interrupts. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high.
Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Interrupt when alert tone is present. Reply Status. Clear-to-send high. Interrupt when header is ready. Reply Status. Clear-to-send high. Frequency is set in units of 2500 Hz. Reply Status. Clear-to-send high. Table 54. Programming Example for the WB/SAME Receiver (Continued)
WB_TUNE_STATUS, WB_ASQ_STATUS, and WB_RSQ_STATUS commands have completed execution. Reply Status. Clear-to-send high. STCINT = 1. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. Reply Status. Clear-to-send high. SAMEINT = 1. Begin reading message from byte 0. Reply Status. Clear-to-send high. Data confidence level = high. WB_SAME_STATUS:CLRBUF bit description. Reply Status. Clear-to-send high.
consult “AN332: Si47xx Programming Guide”. Table 55. Die Revision and Firmware Revision Table
Rev. 1.0 295 Each of the following subsections de scribes the differences be tween revisions for groups of properties and/or commands. Each property is listed as PROPERTY_NAME (number) = default (supported revisions). Hexadecimal values are immediately preceded by “0x”; all other numeric values are decimal. AM, FM, and WB errata on -B20 have been addressed in -C40 and/or -D60 devices. The -D60 is the most recent revision and offers advanced features not available in the -C40 and -B20 revisions. FM Properties And Commands The properties and commands in this section are related to FM mode. FM Mode Max Tune Error (0x110x Properties) FM_MODE_MAX_TUNE_ERROR (0x1108) = 30 (-B20), 20 (-C40, -D60) Maximum tune error in kHz is stored in property 0x1108. It has a default se tting of 30 kHz in -B20, and a default setting of 20 kHz in -C40 and -D60. It should be noted t hat 20 kHz has been recommended for best performance even on -B20 devices through AN332. FM RSQ Interrupt Configuration (0x120x Properties) FM_RSQ_MULTIPATH_HIGH_THRESHOLD (0x1205 ) = 127 (-D60) FM_RSQ_MULTIPATH_LOW_THRESHOLD (0x1206 ) = 0 (-D60) Properties 0x1205 and 0x1206 are only available on -D60 parts. FM Soft Mute Configuration (0x130x Properties) FM_SOFT_MUTE_SLOPE (0x1301) = 2 (-C40, -D60) The target soft mute target attenuation - up to a set ma ximum attenuation level - is calculated as the difference between the soft mute threshold and the received SNR multiplied by a property value called the FM_SOFT_MUTE_SLOPE. In -C40 and -D60, the default slope is 2 dB/dB. In in -B20, the slope is not configurable through a property, but is also 2 dB/dB. Stereo Blend Thresholds (0x110x, 0x180x Properties) FM_BLEND_STEREO_THRESHOLD (0x1105) = 49 (-B20, -C40) FM_BLEND_MONO_THRESHOLD (0x1106) = 30 (-B20, -C40) FM_BLEND_RSSI_STEREO_THRESHOLD (0x1800) = 49 (-D60) FM_BLEND_RSSI_MONO_THRESHOLD (0x1801) = 30 (-D60) FM_BLEND_RSSI_ATTACK_RATE (0x1802) = 4000 (-D60) FM_BLEND_RSSI_RELEASE_RATE (0x1803) = 400 (-D60) FM_BLEND_SNR_STEREO_THRESHOLD (0x1804) = 27 (-D60) FM_BLEND_SNR_MONO_THRESHOLD (0x1805) = 14 (-D60) FM_BLEND_SNR_ATTACK_RATE (0x1806) = 4000 (-D60) FM_BLEND_SNR_RELEASE_RATE (0x1807) = 400 (-D60) FM_BLEND_MULTIPATH_STEREO_THRESHOLD (0x1808) = 20 (-D60)
296 Rev. 1.0 FM_BLEND_MULTIPATH_MONO_THRESHOLD (0x1809) = 60 (-D60) FM_BLEND_MULTIPATH_ATTACK_RATE (0x180A) = 4000 (-D60) FM_BLEND_MULTIPATH_RELEASE_RATE (0x180B) = 40 (-D60) In -B20 and -C40, FM stereo blend is only determined by RSSI based on blend thresholds set in 0x1105 and 0x1106. In -D60 devices, a series of advanced blend properties have been added to improve the user experience under dynamic signal conditions. To accommodate for this change, RSSI based threshold properties were relocated respectively to properties 0x1800 and 0x1801. 0x1800 and 0x1801 have the same default values as 0x1105 and 0x1106. Additional advanced blend features include stereo blending based on SNR and multipath thresholds. For each set of thresholds, separate blend attack (into mono) and releas e (into stereo) rates may be set. Each of the factors is independently evaluated, and any may trigger a blend into mono at its given threshold and rate. To remove any of the advanced blend factors from consideration; set the corresponding blend thresholds to min value of 0 for SNR based blend (0x1804/0x1805), and set the corresponding blend thresholds to max value of 100 for multipath based blend (0x1808/0x1809). FM Commands Some parameters and returned values are only applicable to -D60 parts. These are: multipath indicator returned by the FM_TUNE_STATUS command and the MULTIP ATH_DETECT_HIGH and MULTIPATH_DETECT_LOW parameters of the FM_RSQ_STATUS command. In -C40 and -D60 devices, the RDSSYNC bit of the response to an FM_RDS_STATUS command may be incorrectly set. A patch is available only for -D60 devices.
Rev. 1.0 297 AM Properties The properties and commands in this section are related to AM mode. AM Mode Configuration (0x310x Properties) AM_MODE_AVC_MAX_GAIN (0x3103) = 0x1543 (-C40, -D60) AM_MODE_AFC_SW_PULL_IN_RANGE (0x3104) = 8695 (-C40, -D60) AM_MODE_AFC_SW_LOCK_IN_RANGE (0x3105) = 11765 (-C40, -D60) AM_MODE_AVC_MAX_GAIN is available in -C40 and -D60 devices with a default max gain of 16 dB. In -B20, the AVC gain is set at maximum and not available through a property. To make -C40 or -D60 behave as -B20, set AM_MODE_MAX_GAIN to 0x7800. AM shortwave AFC range properties are available in -C40 and -D60 devices (supp orted by Si4734/35 devices only). The default values of these properties provide similar behavior to the behavior of -B20 devices. However, in -B20 devices, these properties are not available through the programming API. AM Soft Mute Configuration (0x330x Properties) AM_SOFT_MUTE_SLOPE (0x3301) = 2 (-B20), 1 (-C40, -D60) AM_SOFT_MUTE_MAX_ATTENUATION (0x3302) = 16 (-B20), 8 (-C40, -D60) AM_SOFT_MUTE_SNR_THRESHOLD (0x3303) = 10 (-B20), 8 (-C40, -D60) Settings for Audio Soft Mute Soft mute is active when SNR falls below the gi ven AM_SOFT_MUTE_SNR_THRESHOLD. When active, the output audio will be decreased at a set rate until the target soft mute attenuation is achi eved. In -B20 devices the threshold is 10 dB, whereas in -C40 and -D60 devices it is 8 dB. The target soft mute target attenuation - up to a set ma ximum attenuation level - is calculated as the difference between the soft mute threshold and the received SNR multiplied by a scalar value called the soft mute slope. The default value of this property is 1 dB/dB in -C40 and -D60. In -B20, the value used is 2 dB/dB. The maximum soft mute attenuation level is 10 dB in -B20. In -C40 and -D60 devices, the maximum level can be set by a property AM_SOFT_MUTE_MAXIMUM_ATTENUATION, which has a default value of 8 dB. The soft mute default changes in -C40 and -D60 have been made to improve weak signal listening experience.
depth configuration reference, consult “AN332: Si47xx Programming Guide”. Hexadecimal values are immediately preceded by “0x”; all other numeric values are decimal. Table 56. Die Revision and Firmware Revision Table
Rev. 1.0 299 To Achieve Similar Performance in SI4704/05/3X-D60 to SI4704/05/3X-C40 The -D60 devices have a more advanced feature set than -C40 devices. This sect ion describes a step-by-step procedure to achieve similar perform ance from -D60 devices to that of -C 40 devices by modifying or disabling some of the advanced features. FM Receiver Mode There is a debug feature that remains active in Si4704/05/3x-D60 firmware which can create periodic noise in audio. Silicon Labs recommends you disable this feature by sending the following bytes (shown here in hexadecimal form): 0x12 0x00 0xFF 0x00 0x00 0x00 In Si4704/05/3x-D60 devices, the FM_BLEND_RSSI_STEREO_THRESHOLD property is no longer at address 0x1105. Use address 0x1800 instead. In Si4704/05/3x-D60 devices, the FM_BLEND_RSSI_MONO_THRESHOLD property is no longer at address 0x1106. Use address 0x1801 instead. To disable the SNR-based stereo blend, set both the FM_BLEND_SNR_STEREO_THRESHOLD property (0x1804) and the FM_BLEND_SNR_MONO_THRESHOLD property (0x1805) to 0. To disable the multipath-based stereo blend, set both the FM_BLEND_MULTIPATH_STEREO_THRESHOLD property (0x1808) and the FM_BLEND_MULTIPATH_MONO_THRESHOLD property (0x1809) to 100 (0x64). AM Receive Mode Si473x-D60 devices are compatible with Si473x-C40 devices in AMRX mode. WB Receive Mode There are no Si473x-D60 devices which support WBRX mode. To Achieve Similar Performance in SI4704/05/3X-D60 to SI4704/05/3X-B20 The -D60 devices have a more advanced feature set than -B20 devices. This section describes a step-by-step procedure to achieve similar performanc e from -D60 devices to that of -B20 devices by modifying or disabling some of the advanced features. FM Receiver Mode There is a debug feature that remains active in Si4704/05/3x-D60 firmware which can create periodic noise in audio. Silicon Labs recommends you disable this feature by sending the following bytes (shown here in hexadecimal form): 0x12 0x00 0xFF 0x00 0x00 0x00 In Si4704/05/3X-D60 devices, the FM_BLEND_RSSI_STEREO_THRESHOLD property is no longer at address 0x1105. Use address 0x1800 instead. In Si4704/05/3X-D60 devices, the FM_BLEND_RSSI_MONO_THRESHOLD property is no longer at address 0x1106. Use address 0x1801 instead. To disable the SNR-based stereo blend, set both the FM_BLEND_SNR_STEREO_THRESHOLD property (0x1804) and the FM_BLEND_SNR_MONO_THRESHOLD property (0x1805) to 0. To disable the multipath-based stereo blend, set both the FM_BLEND_MULTIPATH_STEREO_THRESHOLD property (0x1808) and the FM_BLEND_MULTIPATH_MONO_THRESHOLD property (0x1809) to 100 (0x64).
300 Rev. 1.0 AM Receive Mode Set the AM_MODE_AVC_MAX_GAIN property (0x3103) to 0x7800. Set the AM_SOFT_MUTE_THRESHOLD property (03303) to 10. Set the AM_SOFT_MUTE_SLOPE property (0x3301) to 2 Set the AM_SOFT_MUTE_MAX_ATTENUATION property (0x3302) to 16. WB Receive Mode There are no Si473x-D60 devices which support WBRX mode. To Achieve Similar Performance in Si4704/05/3X-C40 to Si4704/05/3X-B20 This section describes a step-by-step procedure to achieve performance from -C40 devices that is similar to that of -B20 devices. FM Receiver Mode Si473x-C40 devices are compatible with Si473x-B20 devices in FMRX mode. AM Receive Mode Set the AM_MODE_AVC_MAX_GAIN property (0x3103) to 0x7800 (maximum). Set the AM_SOFT_MUTE_THRESHOLD property (0x3303) to 10 (db). Set the AM_SOFT_MUTE_SLOPE property (0x3301) to 2 (dB/dB). Set the AM_SOFT_MUTE_MAX_ATTENUATION property (0x3302) to 16 (dB). WB Receive Mode Si473x-C40 devices are compatible with Si473x-B20 devices in WBRX mode.
Rev. 1.0 301 DOCUMENT CHANGE LIST Revision 0.1 to Revision 0.2 Updated Product Matrix in Table 1. Added Si4706 FM and High-Performance RDS Receiver support. Added Si4707 WB/SAME Receiver support. Added Si4740/41 multipath, blend, and AGC properties. Added Si4749 High-Performance RDS Receiver support. Updated Firmware, Library, and Component Compatibility tables. Added Command Timing Parameters for the WB Receiver. Updated FM Transmitter maximum audio volume recommendations. Revision 0.2 to Revision 0.3 Added notes to AM/SW/LW Receiver Reference Clock section. Removed Si4706/07/4x–related material. Updated product matrix in Table 1. Revision 0.3 to Revision 0.4 Added Si4704/05/30/31/34/35/36/37/38/39-C40 receiver support and additional AM properties. Added Si4784/85-B20 receiver support. Updated product matrix in Table 1. Updated with corrections to couple commands and properties. Revision 0.4 to Revision 0.41 Minor edits. Revision 0.41 to Revision 0.5 Combined information in AN332 Rev. 0.41 and Added information for Si47xx-D50 and Si47xx-D60 parts. Revision 0.5 to Revision 0.6 Added Appendix A and Appendix B. Revision 0.6 to Revision 0.7 Added FM_BLEND_MAX_STEREO_SEPARATION property Revision 0.7 to Revision 0.8 Corrected pin numbers of LIN and RIN for Si4704/05/3x-D60 parts. Added more explanations to property 0x1900 and 0x3103. Added AUXIN Components in Tables 33, 38, and 41. Revision 0.8 to Revision 1.0 Removed all information about AUXIN components. Removed AUXIN components from Tables 30, 35, and 38. Added notes to powerup command section.
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