AN331

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Rev. 0.1 9/07 Copyright © 2007 by Silicon Laboratories AN331 AN331 COMPENSATING THE F EEDBACK L OOP FOR THE Si3400 AND Si3401 1. Introduction The Si3400 and Si3401 reference designs are available for m any output voltages (e.g., 3.3, 5, 9, 12 V) and output capacitor types. In general, Silicon Laboratories strongly re commends using these standa rd designs to minimize risk and ensure robust performance. Refer to the desi gn databases posted on the Si3400/01 documentation page on the Silicon Labs website for more information: „ EVB Data Sheets z Si3400-EVB z Si3401-EVB z Si3400ISO-EVB z Si3401ISO-EVB „ EVB Reference Design Databases (Schematics and Layout) z Si3400-EVB z Si3401-EVB z Si3400ISO-EVB z Si3401ISO-EVB However, some designers may want to consider other cases of output filtering, input filtering, inductors, etc. for a variety of reasons (cost, footprint, availability, etc.). While it would be desirable to use circuit simulation to optimize the feedback loop, it is very difficult to get reliable information about important factors such as capacitor ESR. Also, the stabilizing effect of the input side hot-swap switch and input filter ESR must be taken into account, which is not straightforward for commonly available SPICE implementations. For these reasons, the feedback loop must be experimentally optimized if a known reference design is not used. The application note outlines the general process for co mpensating the feedback loop experimentally. In case a predefined compensation and output filter is not used, it is strongly recommended that this procedure be followed to ensure robust performance. 1.1. Breaking the feedback loop The feedback loop is broken and a transformer is used to inject an ac signal across the break. Using a transformer allows the loop stability to be measured in a closed loop system with what ever load a filtering is present. The loop is broken at the output and at the point sensing the out put voltage. The transformer ac and dc impedance must be small compared to the impedance sensing the output voltage. Figures 1 and 2 show the recommended transformer pl acement for the non-isolated and isolated reference designs.

Vpos is a EMI and ESD plane. Use top layer. Vneg is a thermal plane as wel as ESD and EMI. on backside 1 to 1.2mm pitch 0.3 to 0.33mm diameter. Figure 1. Non-Isolated

Vneg is a thermal plane as well as ESD and EMI. on backside 1 to 1.2mm pitch 0.3 to 0.33mm diameter. Capacitors C10-C17 are for ESD immunity.. Place optional bypass diodes for high power applications (>10W) in parallel. Vpos is a EMI and ESD plane. Use top layer. Figure 2. Isolated

long as it keeps a low ac and dc impedance. over 10 MHz insuring that the transformer itself does not impact the feedback loop. interest and have a provision for high impedance (1 MΩ) probes. practice, a signal level of –20 to –30 dBm (50 Ω reference) has been found to be satisfactory. unity (zero dB) and 10 dB of gain margin when the phase reaches zero degrees. Figure 3. Phase and Gain of VOUT with Respect to VIN

6 Rev. 0.1 non-isolated reference design the R7-C7 zero is at 1.6 kHz and the loop bandwidth is about 4 kHz. C19 introduces a final pole which is required to filter noise that can be coupled to th e ERout node. If used, the C20-R6 zero is placed at about the loop bandwidth (not below) so as to maximize the phase boost prior to the pole from C20-R5// R6. The optimization process for the non-isolated design is as follows: 1. R5 and R6 are fixed to set the desired output voltage (see http://www.silabs.com/public/documents/tpub_doc/ othertpubs/Wireline/High_Voltage/en/Si3400SwitcherCalcs.xls 2. Vary C7 to move the crossover frequency up and down. 3. R7 is increased to reduce the C7-R7 zero to 1/2 to 1/3 of the loop bandwidth. 4. If used, C20 is set so that C20-R6 is equal to the loop bandwidth. 5. If the phase margin and gain margin are too big or too small go back to step 2 and change C7 up (not enough margin) or down (too much margin and not enough bandwidth). For the isolated design, the C21-R11 pole compensates the zero introduced by C9 and R8+R6//R5. Therefore, the zeros of concern for loop stability are C21-R12 and C8-R5. As in the non-isol ated design these zeros (in this case 7.8 kHz and 7.2 kHz) are placed at around the desired loop bandwidth (7 kHz) so as to maximize the phase boost. In this case both zeros are placed near the loop bandwidth because it is desirable to minimize R12 to reduce noise at ERout. The optimization process for the isolated design is as follows: 1. R5 and R6 are fixed to set the desired output voltage (see http://www.silabs.com/public/documents/tpub_doc/ othertpubs/Wireline/High_Voltage/ R8 is set to 10 kΩ, R11 is set to 4.99 kΩ and R7 is set according to the output voltage (1 kΩ at 3.3 V 2.05 kΩ at 5 V and 4.99 kΩ at 9 or 12 V for example). R9 is generally set to approximately 3.01 kΩ. 2. Vary C9 and C21 to move the crossover frequency up and down. Generally, C9 and C11 are kept as a ratio and C9 is < 1/4 of C21. 3. R12 is increased so that R12 x C21 is less than or equal to the loop bandwidth subject to the constraint that R12 <1K to filter any noise at ERout. 4. C8 is increased so that C8 x R5 is approximately equal to the loop bandwidth. 5. If the phase margin and gain margin are too big or too small, go back to step 2 and change C9 and C21 (in the same ratio) up (not enough margin) or down (too much margin and not enough bandwidth). 2. Conclusions To ensure robust performance in cases where a predefined compensation and output filter are not used, the application note outlines the general process required for experimentally compensati ng the Si3400/01 feedback loop. Refer to the Si3400/01 Evaluation Board User’s Guides and reference designs for complete schematics for common output voltages and output filter configurations.

Rev. 0.1 7 NOTES:

8 Rev. 0.1 CONTACT INFORMATION Silicon Laboratories Inc.

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