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Silicon on Insulator (SOI) process tech nology, which enables the integration of a robust surge pr otection function. used in Power over Ethernet powered device applications.
- Traditional PD Surge Protection Considerations
most often used with PD controllers is an external SMAJ58A TVS diode (D1 in Figure 1). Figure 1. Traditional PoE PD Interface and Switching Regulator PoE PD controllers are implemented in processes providing a 100 V breakdown voltage.
2 Rev. 0.2 3. Detailed Description of Si3400 Protection Si3400 and Si3401 protection consists of a stack of te n, high-current 6.2 V Zener diodes. These lower-voltage Zener diodes have a lower temperature and process vari ation than a higher voltage Zener clamp, such as an SMAJ58A. Consequently, the range of initial breakdown fo r the complete stack is mu ch tighter: typically <1 V variation at room temperature (as compared to 6.8 V for the SMAJ58A) and <4 V variation over –40 to +85 °C. Due to the incremental resistance of the Zener diode stack, the voltage at 0.5 A current typically increases to 73 V, and the voltage at 5 A current is less than 79 V for the Si34 00's on-chip protector. As a result, the Si3400's maximum clamping voltage of 79 V is considerably lower than the 90 to 100 V range of a typical SMAJ58A TVS protector. Because the Zener stack is part of the Si3400's internal circuitry, it becomes straightforward to detect a surge condition internal to the IC. To provide additional protection against high current and longer-duration transients, the switcher is shut down, and the hot swap switch is turned on with the current limit disabled when current starts to flow in the Zener diode stack. Disab ling the switcher section during a tr ansient event prevents damage to the switching FET. Turning on the hot swap switch allows steering of some of the surge current to the switching rectifier input filter capacitor, which reduces the current in the Z ener stack and allows for very high current spike tolerance without damage. 4. Surge Test Considerations for the Si3400 and Si3401 There are five basic surge conditions that must be ac counted for when evaluating surge protection as detailed below. The Si3400's performance has been tested in all of these conditions with excellent results. 4.1. Standards-Based Surge Testing IEEE STD™ 802.3-2005 s pecifies a 1000 V surge tolerance with a 300 n sec virtual front and 50 µsec half value (as defined in IEC 60060) with an impedance applied via a 402 Ω resistor to each wire in the wire pair. While the return path is not specified, a worst case interpretation is that the return pair is grounded so that 2.5 A flows in each of the wires to the PD, resulting in a 5 A surge to the PD. The 5 A surge will charge the typical 0.1 µF PD input capa citor to 50 V in 1 µsec. Afte r this time, the Zener diode clamps, and once the hot swap switch is turned on, some of this surge is steered to the switcher input filter capacitor as well. The Si3400's performance has been tested with this worst-ca se interpretation surge co ndition. All devices tested survived the standard 1000 V condition for 10 repetitions with substantial margin. 4.2. ESD An Si3400 isolated EVB (Revision 1.2) was tested for ESD immunity. The test method reference is IEC 61000-4-2. A Schaffner model NSG 435 ESD gun was used to generate the ESD pulses. For this test, the connector shield was tied to the Vneg heat sink/isolated ground plane of the Si3400 ISO EVB, and the ESD pulses were applied to the sh ield with the output of the EVB grounded. The ESD discharge path in this case would be through the 1000 pF high-voltage capacitors connected from the output side ground plane to Vpos and Vneg. An attempt was made to discharge to the RJ -45 pins, but the discharge was always to the shield indicating that surging the shield is an appropriate test method. The ESD gun was used in contact mode and the ESD pulses were applied in both polarities in 500 V increments up to 9 kV. Above 9 kV, contact mode is not supported with the ESD gun; so, air discharge mode was used, again increasing the voltage in 500 V steps up to the maximum av ailable voltage of 16.5 kV in both polarities. After each voltage increment, the board was tested and was not damaged. The 15 kV test was repeated 10 times for each polarity, again with no damage observed after each test.
peak of up to 175 V applied through 400 Ω source shall not result in a safety hazard. fault condition of ringing directly applied, the Si3400 PD will not be damaged. A Si3400 PD evaluation board was tested using this procedure with the test diagram shown in Figure 2. Figure 2. Test Diagram
- Verify board functionality with 48 VDC Supply.
- Unplug 1 m cable from junction block.
- Charge 25 ft cable with HyPot tester at 1000 V.
- Plug 25 ft cable into junction block with HyPot tester connected.
- Unplug 25 ft cable while HyPot te ster is still putting out voltage.
- Plug in 48 V supply through 1 m cable.
- Verify board functionality.
- Repeat steps 2-7 testing twice at 1000 V and twic e at each voltage above 1000 V in 500 V increments.
assuming that the cable maintains its charge prior to being plugged in. This puts the performance of the Si3400 well into the "excellent" CDE category. Figure 3. Auxiliary Supply inductance, the peak current can exceed 10 A. A surge limiting resistor will reduce the overshoot and peak current. this resistor does carry up to the maximum 350 mA of dc PD input current, a 0.5 W resistor is recommended.
The test results are summarized in Table 1. optimal cost and performance compared to solutions requiring an external surge protector. Table 1. Test Results
6 Rev. 0.2 DOCUMENT CHANGE LIST Revision 0.1 to Revision 0.2 Updated Table 1 on page 5. z Added reference to IEC 61000-4-2 specification for ESD test.
Rev. 0.2 7 NOTES:
8 Rev. 0.2 CONTACT INFORMATION Silicon Laboratories Inc.
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Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: PoEinfo@silabs.com Internet: www.silabs.com Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse- quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per- sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.