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Rev. 0.9 6/09 Copyright © 2009 by Silicon Laboratories AN230 AN230 Si4700/01/02/03 P ROGRAMMING G UIDE 1. Introduction 1.1. Scope This document applies to Si4700/01/02/03 firmware re vision 15 and greater and example code version 2 and greater. Refer to www.mysilabs.com for example code. 1.2. Purpose The purpose of this programming guide is to describe the following: Device initialization sequence and busmode selection 2-wire and 3-wire busmodes Step-by-step procedures for setting default configuration channel selection seek up/seek down RDS/RBDS This document references the Si4700/01 and Si4702/03 data sheets. 1.3. Terminology SENB or SEN—serial enable pin, active low, used only for 3-wire operation SDIO—serial data in/data out pin. SCLK—serial clock pin. RSTB or RST —reset pin, active low Device—refers to the Si4700/01/02/03
2 Rev. 0.9
Rev. 0.9 3 TABLE OF C ONTENTS
Figure 1. Initialization Sequence
Rev. 0.9 5 2.1.1. Hardware Initialization The FM tuner device is capable of communicating using eit her a 3-wire or 2-wire interface. The selection of this interface is made during the reset sequence. Figure 1 demonstrates the sequencing of hardware events relative to reset. Figure 2 combines this information with the setting of the ENABLE and DISABLE bits to better describe the possible combinations. The following steps should be used to initialize the device properly. 1. Supply V A and VD. 2. Supply V IO while keeping the RST pin low. Note that power supplies may be sequenced in any order (steps 1 and 2 may be reversed). 3. Configure the proper pins for bus mode selection. See Figure 3, “Powerup, Powerdown, and Reset Flowchart,” on page 7. 4. Set the RST pin high. The device registers may now be read and written. 5. Provide RCLK. If using the internal oscillator option, set the XOSCEN bit. Provide a sufficient delay before setting the ENABLE bit to ensure that the oscillator has stabilized. The delay will vary depending on the external oscillator circuit and the ESR of the crystal, and it should include margin to allow for device tolerances. The recommended minimum delay is no less than 500 ms. A similar delay may be necessary for some external oscillator circuits. Determine the necessary stabilization time for the clock source in the system. To experimentally measure the minimum oscillator stabilization time, adjust the delay time between setting the XOSCEN and ENABLE bits. After powerup, use the Set Property Command described in "5.1.Si4702/03 Commands (Si4702/03 Rev C or Later Device Only)" on page 31 to read property address 0x0700. If the delay exceeds the minimum oscillator stabilization time, the property value will read 0x1980 ±20%. If the property value is above this range, the delay time is too short. The selected delay time should include margin to allow for device tolerances. 6. Si4703-C19 Errata Solution 2: Set RDSD = 0x0000. Note that this is a writable register. 7. Set the ENABLE bit high and the DI SABLE bit low to powerup the device. Unpredictable behavior could result if a non-zero value is present in the RDSD register of the Si4703-C19 when it is enabled. Note that no other device will experience this behavior. There are three solutions available to ensure a zero value in the RDSD register when the Si4703-C19 is enabled and only one solution need be selected. a. Solution 1—Generate a hard reset before enablin g the tuner to clear the RDSD register. This is described in steps 2, 3, and 4 above and in step 1, To power up the device (after power down), of 2.1.2. "Hardware Powerdown” below. This must be done every time the tuner is enabled. b. Solution 2—Write a zero value to the RDSD register be fore enabling the tuner. This is described in step 6 above and must be done every time the tuner is enabled. c. Solution 3—Disable RDS by setting RDS = 0 before disabling the tuner. This is described in step 1, To power down the device, of 2.1.2. "Hardware Powerdown” below and must be done every time the tuner is disabled. When the device is disabled, the RDSD register is automatically set to zero in preparation for the next time the device is enabled. 2.1.2. Hardware Powerdown A powerdown mode is available to reduce power consumption when the part is idle. Setting both the ENABLE bit high and the DISABLE bit high starts t he powerdown sequ ence. This disables analog and digital circuitry while maintaining register configuration and keeping the bus active. Note that the device automatically sets the ENABLE bit low after the internal powerdown sequence completes. Setting the ENABLE bit low directly will cause the device to partially powerdown and should be avoided. See Figure 2. Setting the ENABLE bit high and the DISABLE bit low will bring the device out of powerdown mode and resume normal operation. Refer to Figure 1 for more information. To power down the device: 1. Si4703-C19 Errata Option 3: Set RDS = 0.
- Set the ENABLE bit high and the DISABLE bit high to place the device in powerdown mode. Note that all
register states are maintained so long as VIO is supplied and the RST pin is high.
- Remove V A and VD supplies as needed.
- Si4703-C19 Errata Option 1: Perform a hard reset of t he tuner by following steps 2, 3, and 4 of 2.1.1 Hardware
IO is still supplied in this scenario. If VIO is not supplied, refer to device initialization procedure above.
- Set the ENABLE bit high and the DI SABLE bit low to powerup the device.
bus mode. Method one uses the SEN and SDIO pins while method two uses GPIO1 and GPIO3 (See Figure 3). (02h.0)/DISABLE (02h.6)—Powerup Control" on page 11. Figure 2. Powerup, Powerdown, and Reset State Diagram register is zero before enabling.
Figure 3. Powerup, Powerdown, and Reset Flowchart Note: See data sheet for further details.
static, static after power up, or dynamic after power up (Table 2). Table 1. Register Use
bits, indicating the powerdown mode has been entered. during powerup configuration. Table 2. Status Bit Classification
Figure 8. Powerup Timing Table 3. Powerup Configuration Sequence Write address 07h (required for crystal oscillator operation). Set the XOSCEN bit to power up the crystal. Wait for crystal to power up (required for crystal oscillator operation). Write address 02h (required). Set the DMUTE bit to disable mute. Optionally mute can be disabled later when audio is needed. Set the ENABLE bit high to set the powerup state. Set the DISABLE bit low to set the powerup state. Wait for device powerup (required). Refer to the Powerup Time specification in Table 7 "FM Characteristics" of the data sheet. Read addresses 00h–01h (optional). The bits PN[3:0] = 1 indicate the part family: Si4700/01/02/03. The bits MFGID[11:0] = 242h indicate Silicon Laboratories as the manufacturer. The bits REV[5:0] = 1 indicate silicon revision A. 2 indicates revision B. 3 indicates revision C. DEV = 0000 after powerup = Si4700. DEV = 0001 after powerup = Si4702. DEV = 1000 after powerup = Si4701. DEV = 1001 after powerup = Si4703. The FIRMWARE bits indicate the firmware revision after powerup. be stored in a 16 word array, shadow_reg[]. Write remaining hardware configuration registers (required). Write the general configuration registers (required). Write the regional configuration registers (required). These registers can be programmed in any order.
digital low (GND). If this is desired, set the fields GPIO1-3[1:0] in register 04h to 10b prior to setting the disable bit. Figure 9. Powerdown Timing set, multiple audio output devices can share a single input into an amplifier without the need for a multiplexer. 0x0100 prior to power up and are 0x3C04 after. Table 4. Powerdown Sequence Write address 07h (optional for LOUT and ROUT Hi-Z). Set AHIZEN. All other bits in this register should be maintained at the value last read (i.e., 0x3C04 or 0xBC04). Write address 04h (optional for GPIO1/2/3 low). Write address 02h (required). Clear the DMUTE bit to enable mute. Set the ENABLE bit high and DISABLE bit high to set the powerdown state.
another device in the system, or left unused. as a general purpose output or left unused. RDS is only available on the Si4701 and Si4703. Table 5. GPIO1 States
00 High impedance (default)
01 Reserved
10 Low output (GND level)
11 High output (VIO level)
Table 6. GPIO2 States
01 STC/RDS interrupt
unused. Note that if the XOSCEN bit is set, GPIO3 is used for the crystal oscillator and this field is ignored. designer options and trade offs so the device can be tailored to a specific design. Table 7. GPIO3 States
01 Mono/Stereo Indicator
Table 8. BLNDADJ States
Figure 10. Stereo Separation removed (SMUTER). The available settings for SMUTEA and SMUTER are shown in the Tables 9 and 10 below. Table 9. SMUTEA Table 10. SMUTER
00 Fastest (default)
01 Fast
10 Slow
11 Slowest
adjust the input voltage into an audio amplifier. low may result in false detections. SEEKTH is one of multiple parameters that can be used to validate channels. For more information and example settings, see "Appendix—Seek Adjustability and Settings" on page 35. "Appendix—Seek Adjustability an d Settings" on page 35. Table 11. VOLEXT Settings
While FM transmission is essentially the same around th e world, there are a few differences between countries. This group of registers allows for customization to a given region. This register sets the range of tunable frequencies. T he device supports 3 different ranges as shown in Table 12. high limit of the range is where the seek algorithm stops or wraps back around to the low limit. information. The 50 kHz should only be used in those countries where transmission at 50 kHz spacing is allowed. For all other countr ies, the AFC will automatically correct for statio ns that are transmitting slightly off carrier. Selecting the proper spacing for the country the system will be used in will result in the best overall performance. 75 µs (0), used in the USA; and 50 µs (1) used in Europe, Australia, and Japan. Table 12. BAND Ranges
11 Reserved (Do not use)
Table 13. SPACE Settings
Rev. 0.9 19 3.5. End User Adjustable Control Registers Several register fields could be tied dire ctly to an end user inte rface. Most designs will have an end user interface that gives access to some if not all of these features, but whether these features ar e implemented via the Si470x device or some other hardware in the design is system specific. 3.5.1. DMUTE (02h.14)—Disable Mute Setting this bit high disables the mute feature. The audio output of the device can be muted in two ways; either by setting this bit low or by programming the VOLUME bits to 0. 3.5.2. MONO (02h.13)—Force Mono Many end users find it desirable to force mono on stat ions with excessive stereo noise. While the device tries to avoid this situation with the stereo/mono blend feature, this bit provides th e option to system designer. Setting MONO = 1 disables the stereo/mono blend feature and fo rces mono decoding of the FM baseband information regardless of signal SNR. 3.5.3. VOLUME (05h.3:0)—Volume Volume is self explanatory. It adjusts the signal streng th of the LOUT and ROUT pins. See the description of VOLEXT for the various settings relative to full scale output. 3.6. Seek Control Registers One of the most powerful features of the device is the ability to au tomatically locate cha nnels with valid content. Several registers control how seek behaves, however, th is section is dedicated to those registers that could possibly change upon the execution of any seek operation. 3.6.1. SEEKUP (02h.9)—Seek Direction The device has the ability to seek for st ations in either direction. Setting th is bit to 1 will cause the device to seek from the current channel up to the next available channel. Setting this bit to 0 will cause the device to seek down to the next available channel. 3.6.2. SKMODE (02h.10)—Seek Band Limit Behavior Mode The device has the ability to stop seeking when a band limit (see BAND) is reached or to wrap around to the other end of the band. Setting this bit caus es the former behavior, i.e. if seeking up and 108 MHz is reached, the device will stop seeking and set the SF/BL bit. Clearing this bit will cause the devi ce to instead wrap back to 76 or 87.5 MHz depending on the setting of BAND. This bit qualif ies as one that may be changed at seek time because of the various features the designer may want to provid e to the end user. For example, a feature that scans the entire band for all valid stations is most likely to begin at CHAN = 00 and go to the end of the band. For that feature, SKMODE = 1 is the best choice. However, to provide a feature that seeks up or down from the currently tuned station, SKMODE = 0 is likely the better choice. 3.6.3. SEEK (02h.8)—Seek This bit indicates that the device should begin a seek operation using the currently programmed seek settings (SKMODE, SEEKUP, SEEKTH, SKSNR, SKCNT). The operation can be aborted by clearing this bit, but this may leave the device on an invalid channel. During normal operation, the designer will leave this bit set until the device sets the STC bit. Once the STC bit is set, the designer should then clear the SEEK bit. Status of the seek operation can be obtained by polling the REA DCHAN register which is updated by the device as the SEEK progresses through the band. The following flow chart shows a typical seek algorithm. Normally when SF/BL is set, the curr ent channel is invalid. Ho wever, there are two exceptions. The first occurs when SKMODE = 0 and there is only one valid channel on the entire band. If the seek is started from that one valid channel, it will wrap the entire band and end on th e valid channel it started from. Since the limit of the seek has been reached, the SF/BL bit will be set. The second exception occurs when SKMODE = 1 and there is a valid channel exactly at the band limit. Because the SEEK has hit the band limit, the bit will be se t. To check for a valid station at the band limits, tune to the station just above the lower limit. Set the SKMODE = 0, SEEKUP = 0, and SEEK = 1. If there is a valid station at the limits, it will be detected. Table 14 shows the sequence of commands required for seek and assumes that the Powerup Configuration, detailed in Section 2.1. "Power, Initialization Sequence, and Busmode Selection”, has completed. This table is intended to be used in conjunction with the seek flowchart in Figure 12.
Figure 11. Seek Timing Table 14. Seek Up/Seek Down Sequence Write address 02h (required). Set the SKMODE high to stop seek at the band limits and low to wrap at the band limits. Set the SEEKUP bit high to seek up and low to seek down. Set the SEEK bit high to begin the seek operation. settings. This array is referred to throughout this document and in the example code as si470x_shadow. Wait for GPIO2 = 0 (required for interrupt method). This indicates that a seek/tune operation has completed. Read address 0Ah (required). The STC bit being set indicates tuning has completed. seek criteria (SEEKTH, SKSNR, SKCNT). The ST bit being set indicates stereo operation. The bits RSS[7:0] indicate RSSI level for the current channel. Read address 0Bh (optional). Write address 02h (required). Set the SEEK bit low to end the tuning operation and to set the STC bit low. Example: Write data to 4001h. Read address 0Ah (optional). operation. Do not set the TUNE or SEEK bits until the Si470x clears the STC bit.
Figure 12. Seek Flowchart
Setting the TUNE bit initiates the tuning process causing the device to switch to the frequency indicated by CHAN. cleared before performing another seek or tune. Configuration, detailed in Section 2.1. "Power, Initialization Sequence, and Busmode Selection”, has completed. Table 15. Channel Selection Sequence Write address 03h (required). Set the TUNE bit high to begin a tuning operation. Set CHAN[9:0] bits to select the desired channel. Wait for GPIO2 = 0 (required for interrupt method). This indicates that a seek/tune operation has completed. Read address 0Ah (optional for interrupt method, required for polling method). The STC bit being set indicates tuning has completed. The ST bit being set indicates stereo operation. The bits RSSI[7:0] indicate RSSI level for the current channel. Read address 0Bh (optional). The bits READCHAN[9:0] indicate the current channel. Write address 03h (required). Set the TUNE bit low to end the tuning operation and to set the STC bit low. Example: Write data to 0050h. Read address 0Ah (optional). operation. Do not set the TUNE or SEEK bits until the Si470x clears the STC bit.
code found in rds.c. For more information on RDS, please refer to “AN243: Using RDS/RBDS with the Si4701/03". Figure 15. RDS Timing Table 16. RDS/RBDS Sequence Write address 02h (optional). Verbose mode indicates the number of errors corrected in each block. Write address 04h (required for interrupt method). Set the RDSIEN bit high to enable a low interrupt on GPIO2 when RDS data are ready. Set the RDS enable bit (RDS = 1). Set GPIO2[1:0] = 01 to enable STC and RDSR interrupts on GPIO2. Example: To enable RDS operation with RDS interrupts and seek/tune interrupts enabled, write data D004h. Wait for GPIO2 = 0 (required for interrupt method). This indicates that RDS data are ready. Read address 0Ah (optional for interrupt method, required for polling method). The RDSR bit being set indicates RDS data are ready (Si4701 only). or more errors, the data in RDSA should be discarded. Read address 0Bh (optional). BLERD indicate 6 or more errors, then just the respective block may be discarded. Read addresses 0Ch–0Fh (required). The bits RDSA[15:0], RDSB[15:0], RDSC[15:0], and RDSD[15:0] contain error-corrected RDS group data.
Figure 16. RDS Flowchart
- Programming with Commands (Si4702/03 Rev C or Later Device Only)
complete list of commands is available in 5. "Command and Properties (Si4702/03 Rev C and Later Device Only)”. (Register 4, bit 12) must be disabled for the duration of the command processing by setting RDS = 0. registers 0Ch–0Fh (RDSA–RDSD). when the command processor is enabled, write register 0Fh to 0x00FF and poll until register 0Fh is 0x0000. Responses provide the user information and are echoed after a command and associated arguments are issued. Table 17. Format for Programming with Commands (Si4702/03 Rev C or Later Device Only)
wire bus mode. In this example the GET_PROPERTY command is demonstrated. register are at the end of the 2-wire mode. control word is ADDR+R = 00100001b = 0x21. The device acknowledges the control word by setting ACK = 0. are not valid and must be ignored. This process is repeated until the STATUS byte is set to 0x00. Table 18. Command and Response Procedure—2-Wire Bus Mode REG 02h–0Bh Write 0x-- Write with the original value. REG 0Ah–0Bh Read 0x-- Read starts from Register 0Ah. RESP0–6 Read 0x-- Response data are only valid when STATUS is set to 0x00. STATUS Read 0x08 Reply Status. Response data are not valid. REG 0Ah–0Bh Read 0x-- Read starts from Register 0Ah. RESP0–6 Read 0x-- Response data are only valid when STATUS is set to 0x00. STATUS Read 0x00 Reply Status. Response data are valid.
unused response bytes return random data and must be ignored. be the last register written. and pulses SCLK high and then low one final time. Table 19. Command and Response Procedure—3-Wire Bus Mode RESP6/STATUS Read 0x0008 Reply Status. Data is not ready. RESP6/STATUS Read 0x0000 Reply Status. Data is ready.
Rev. 0.9 29 Next, the controller sends ARG6 and CMD of the command by driving drives the 9-bit control word on SDIO, consisting of the device address (A7:A5 = 101b), the writ e bit (0b), the device address (A4 = 0b), and register address for the COMMAND4 register (A3:A0 = 1111b). The control word is followed by a 16-bit data word, consisting of ARG6 followed by CMD. The system controller then sets SEN = 1 and pulses SCLK high and then low one final time. To read the status and response from the device, the system controller sets SEN= 0. Next, the controller drives the 9-bit control word on SDIO, consisting of the device addr ess (A7:A5 = 101b), the read bit (1b), the device address (A4 = 0b), and register address for t he RESPONSE4 register (A3:A0 = 1111b). The control word is followed by a 16-bit data word, consisting of RESP6 followed by STATUS. The system controller then sets SEN = 1 and pulses SCLK high and then low one final time. In this example, the STATUS byte is 0x08, indicating that the response data are not ready. The device is not ready to accept another command. RESP6 is random until the STATUS byte is 0x00. This process should be repeated until the STATUS byte is set to 0x00. When the STATUS byte is set to 0x00, the system contro ller may read the response bytes from the device in any order. If the reply included RESP0 and RESP1 by tes, the system controller sets SEN = 0, and then the controller drives the 9-bit control word on SDIO, consisting of the devic e address (A7:A5 = 101b), the read bit (1b), the device address (A4 = 0b), and regi ster address for th e RESPONSE1 register (A3:A0 = 1100b). The control word is followed by a 16-bit data word, consisting of RESP0 followed by RESP1. The system controller then sets SEN =1 and pulses SCLK high and then low one final time. SEN Control ARG4 ARG5 SEN SCLK 1 0 10101110b 0x03 0x00 0 1P u l s e SEN Control ARG6 CMD SEN SCLK 1 0 10101111b 0x00 0x08 0 1P u l s e SEN Control RESP7 STATUS SEN SCLK 1 0 10111111b 0x00 0x08 0 1P u l s e SEN Control RESP7 STATUS SEN SCLK 1 0 10111111b 0x00 0x00 0 1P u l s e SEN Control RESP0 RESP1 SEN SCLK 1 0 10111101b 0x-- 0x-- 0 1P u l s e
- Command and Properties (Si4702/03 Rev C and Later Device Only)
Table 20. Si4702/03 Command Summary (Si4702/03 Rev C or Later Device Only) 0x07 SET_PROPERTY Sets the value of a property. 0x08 GET_PROPERTY Retrieves a property's value. 0xFF VERIFY_COMMAND This command can be used to determine that the command processor is enabled.
Rev. 0.9 31 5.1. Si4702/03 Commands (Si4702/03 Rev C or Later Device Only) Command 0x07 SET PROPERTY Sets a property shown in Section 5.2. "Si4702/03 Properties (Si4702/03 Rev C or Later Device Only)”. This command may only be sent when in powerup mode. Response bytes: None Command B i tD 7 D 6 D 5D 4D 3D 2D 1D 0 C M D 000 0 0 1 1 1 ARG0 PROPERTY_VALUE[15:8] ARG1 PROPERTY_VALUE[7:0] ARG2 Always write to 0 ARG3 Always write to 0 ARG4 PROPERTY_INDEX[15:8] ARG5 PROPERTY_INDEX[7:0] ARG6 Always write to 0
32 Rev. 0.9 Command 0x08 GET PROPERTY Gets a property shown in Section 5.2. This command may only be sent when in powerup mode. Response bytes: Two Command Response Command 0xFF VERIFY_COMMAND This command can be used to determine that the command processor is enabled. Send this command and poll to see that the command byte has been cleared. Response bytes: None Command B i tD 7 D 6 D 5D 4D 3D 2D 1D 0 C M D 000 0 1 0 0 0 ARG0 Always write to 0 ARG1 Always write to 0 ARG2 Always write to 0 ARG3 Always write to 0 ARG4 PROPERTY_INDEX[15:8] ARG5 PROPERTY_INDEX[7:0] ARG6 Always write to 0 B i t D 7 D 6 D 5D 4D 3D 2D 1D 0 RESP0 PROPERTY VALUE [15:8] RESP1 PROPERTY VALUE [7:0] B i tD 7 D 6 D 5D 4D 3D 2D 1D 0 C M D 111 1 1 1 1 1 ARG0 Always write to 0 ARG1 Always write to 0 ARG2 Always write to 0 ARG3 Always write to 0 ARG4 Always write to 0 ARG5 Always write to 0 ARG6 Always write to 0
Rev. 0.9 33 5.2. Si4702/03 Properties (Si4702/03 Rev C or Later Device Only) Property 0x0200. FM_DETECTOR_SNR (Default 0) Selects the SNR where the FM detector switches modes. Default of 0 is backward compatible with Si4702/03-B16 FM detector. SNR >12 differential detector 12 > SNR > threshold impulse reject detector threshold > SNR > 0 slew rate detector Property 0x0300 BLEND_MONO_RSSI (Default 31) Sets the RSSI level to enable full mono audio output. At RSSI levels more than BLEND_MONO_RSSI, but less than BLEND_STEREO_RSSI, stereo separa tion will be reduced. If this property is used , it is re commended that the BLENDADJ bits be set to 0. B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 00000000 F D S N R [ 7 : 0 ] Bit Name Function D15:D8 Reserved Always write to 0. D7:D0 FDSNR Sets threshold for FM detector. B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 00000000 B M R [ 7 : 0 ] Bit Name Function D15:D8 Reserved Always write to 0. D7:D0 BMR Sets threshold for full mono audio output.
34 Rev. 0.9 Property 0x0301 BLEND_STEREO_RSSI (Default 50) Sets the RSSI level to enable full stereo audio output. At RSSI levels more th an BLEND_MONO_RSSI, but less than BLEND_STEREO_RSSI, stereo separa tion will be reduced. If this property is used , it is re commended that the BLENDADJ bits be set to 0. Property 0x0700 CALCODE (Default n/a) READ-ONLY Internal calibration result of the powerup sequence. This result may be used to troubleshoot crystal oscillator/RCLK Property 0x0C00 SNRDB (Default n/a) READ-ONLY SNR level (in 2 dB steps) that the seek algorithm is seeing. FM_DETECTOR_SNR uses this value to compare to the threshold. B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 00000000 B S R [ 7 : 0 ] Bit Name Function D15:D8 Reserved Always write to 0. D7:D0 BSR Sets threshold for full stereo audio output. B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name CALCODE[15:0] Bit Name Function D15:D0 CALCODE Internal calibration result of the powerup sequence. B i t D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Name 00000000 S NRDB[7:0] Bit Name Function D15:D8 Reserved Always write to 0. D7:D0 SNRDB SNR level (in 2 dB steps) that the seek algorithm is compared to.
Rev. 0.9 35 APPENDIX—S EEK ADJUSTABILITY AND SETTINGS Introduction An important feature of an FM radio receiver is it s ability to reliably identify valid stations during a seek operation. This feature allows end customers to seek from one valid station to the next up and down the FM band. It also allows manufacturers to create host software to automatic ally populate a list of valid stations in a given area. However, reliably identifying and separating valid stations from noise or p oor-quality stations is challenging in any environment, especially portable devi ces. The Silicon Laboratorie s Si4700/01/02/03 FM Tu ner family provides a highly reliable seek algorithm, and also adds adjustability so that manufact urers and/or end users can customize seek settings to accommodate individual tastes or changing RF environments. Default Seek Qualifiers The most commonly used measurement of valid stations is the total received power at a given channel compared to a threshold. In the Si4700/01/02/03 family, this power measurement is Received Signal Strength Indicator (RSSI), measured as the integrated powe r after the channel filter for a given channel. The RSSI seek threshold (SEEKTH) is simply the power level above which a valid channel is determined. Setting the seek threshold too high may result in missed valid channels; too low may result in false detections. To augment the accuracy of this metr ic, the Si4700/01/02/03 incorporates a second indicator of valid channels called Automatic Frequency Control Rail, or AFC rail. AFC rail is used to dete ct the condition wherein an adjacent channel's power is detected at the tuned frequency, potentially detecting a false positive. If a tuned channel’s RSSI is above the seek threshold, but the AFC has tracked from the center of the channel by a given number of kHz, the channel can reliably be determined to be an invalid station. Using the RSSI threshold in conjunction with AFC rail offers seek performance with a greater than 90% probability of finding only valid stations and a sub-4 second scan time for auto-populating valid stations. Note: Figures given represent a competitive host micro-controller, 200 kHz channel spacing, and 87.5–108 MHz band setting.
indicated by their frequencies. Figure 17. Sample RSSI Spectrum the seek threshold to 22 as shown avoids false detections but could miss these valid stations. users may adjust seek as desired. threshold values and likely results are shown in Table 21.
present on a given channel. This qualifier is optional and adjustable. Table 22 provides some example settings and approximate results. disqualify them as valid stations. Table 21. Sample SKSNR[3:0] Settings Table 22. Sample SKCNT[3:0] Settings
The seek algorithm sequencing is shown in the flowchart in Figure 18. Figure 18. Seek Algorithm Flowchart Note: Both SNR and FM impulse count are independent and can be run as additional qualifiers with or without the other.
Table 23. Summary of Seek Settings
Rev. 0.9 41 DOCUMENT CHANGE LIST Revision 0.42 to Revision 0.43 Added Sections 4. "Programming with Commands (Si4702/03 Rev C or Later Device Only)” and 5. "Command and Properties (Si4702/03 Rev C and Later Device Only)”. Revision 0.43 to Revision 0.44 Updated "4.1.Programming in Command in 2-wire Control Interface Mode" on page 27. Updated command register "Property 0x0200. FM_DETECTOR_SNR (Default 0)" on page 33. Revision 0.44 to Revision 0.5 Added Si4703-C19 Errata description: Updated 2.1.1 Hardware Initialization. Updated 2.1.2 Hardware Powerdown. Updated Figure 2 on page 6. Revision 0.5 to Revision 0.6 Added "Appendix—Seek Ad justability and Settings”. Expanded Sections 3.3.4–3.3.6 Added description of setting GPIO1/2/3 low to Table 4. Clarified Section 3.2.1 and Table 3. Removed NDA. Revision 0.6 to Revision 0.61 Added 0.5 to 0.6 revision list. Revision 0.61 to Revision 0.62 Updated Table 20, “Si4702/03 Command Summary (Si4702/03 Rev C or Later Device Only),” on page 30. Revision 0.62 to Revision 0.7 Updated Table 21, “Sample SKSNR[3:0] Settings,” on page 37 and Table 23, “Summary of Seek Settings,” on page 40. Revision 0.7 to Revision 0.8 Updated BLEND_MONO_RSSI, BLEND_STEREO_RSSI property index in Tables 18, 19, and Section 5.2. Revision 0.8 to Revision 0.9 Updated "2.1.1.Hardware Initialization" on page 5 step 5. Updated Register , “Property 0x0C00 SNRDB (Default n/a) READ-ONLY,” on page 34.
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