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circuit cost and complexity, they sample signals at very high rates and produce a low-noise, high-resolution output. Delta-sigma ADCs also add benefit by shaping noise and digitally filtering the information to enhance performance. reduce the cost and complexity of circuits that must filter the signal at the input of the ADC. weigh-scales. The maximum C8051F35x ADC output word rate is 1 kHz. Figure 1. ADC0 Block Diagram
2 Rev. 0.2 2. Using the C8051F35x Delta-Sigma ADC Using delta-sigma ADCs require an unde rstanding of how to properly configur e the modulator, use of the digital filter/decimator, and the nature of high-precision measurements of small signal voltages. Additionally, the C8051F35x family of devices’ ADC provides functions such as calibration and offset adjustment that should be fully understood when designing with these devices. The followi ng sections describe the signal path from the input signal source, to the ADC input, through the modulator, digital filter, and finally the output result (16- or 24-bit digital output). Calibration of the ADC and ci rcuit board design notes follow. Finally, delta-sigma noise specifications are discussed. 2.1. Signal The C8051F35x ADC is designed for optimal performance with a modulator sample rate of 19.2 kHz. The ADC is designed as an oversampling data converter, so the band width of the input signal should be low (the lower the input signal bandwidth, the better th e noise performance will be). The ADC is designed to measure voltages with high precision. 2.1.1. Getting the Signal to the ADC To aid high-precision measurements of small voltage sign als, the ADC is best configured to input a differential signal to an AIN+ and AIN– input pin pair. The analog mu ltiplexer (AMUX) can select from eight external channels of input, an on-chip temperature sensor, and an internal analog ground. The signal source (e.g, a transducer) can be directly wired to the ADC’s input. If the input is from a pair of wires, t wisted-pairs should be used with shielding to reduce noise where feasible (keep wires as short as po ssible and away from other signals, especially digital signals). The main idea is to design a system in which noise will be present equally on both AIN+ and AIN– in order to reject common-mode noise. (See Figure 6 on page 12.) 2.1.2. Sensor Excitation Some transducers require an excitation current to generate an output voltage. The C8051F35x devices feature two on-chip current mode digital-to-analog converters (IDACs) for this purpose. See the data sheet for more details. 2.1.3. Analog Front-End The input circuit to the ADC pins typically requires filtering and sometimes buffering and gain. Filtering requirements for a delta-sigma ADC are low, and often the on-chip buffer and programmable gain will suffice. 2.1.4. External Buffer and Gain The input signal must be kept within the dynamic range of the ADC (determined by the voltage reference voltage) and within ground and supply voltage. The best measur ement performance is achieved when the input signal’s dynamic range is the same as the dynamic range of t he ADC (i.e., voltage reference voltage). When the signal is much smaller than the dynamic range of the ADC it will require amplification. The on-chip programmable gain or an external amplifiercan can be used for th is purpose. In many applications, a simple op-amp will suffice, but for best performance choose a low-noise instrumentation or chopper stabilized amplifier. Many sensors have high-impedance output stages and require a high-impedance input to avoid introducing offset error. External amplifiers and op-amps serve this purpo se. The C8051F35x devices also have an on-chip input buffer. However, for very high-resolution measurements, the on-chip buffers or external op-amps may not suffice due to drift (i.e., 1/f noise). For the best measurements, consider the use of chopper stabilized amplifiers (best for high-accuracy dc measurements) or a low-noise amplifier. 2.1.5. Analog Input Filter Typically, the only required input circuit needed for a del ta-sigma ADC is an RC low-pass filter. While the ADC shapes and filters noise, there is no noise rejection at the sample rate (19.2 kHz a nd its multiples). The RC time constant should be designed to adequately remove noise at the sample rate frequency bandwidth, but not cause error due to filter settling time as the input signal volt age changes. The ADC samples the signal at a high rate by switching a capacitor. This results in average current flow into the ADC. This switching current can cause several inaccuracies in measurement including gain and offset erro rs and non-linearity if the input filter is not properly designed. Further, if an input buffer is used (e.g., an op-amp) the switched capacito r could result in amplifier instability. The RC circuit solves these problems by prov iding isolation (the resistor) and a c harge reservoir (the capacitor).
such that a high valued resistor is not necessary. Typically, capacitors valued in the 1/10th’s of µF’s are used. Figure 2. Configuring The Delta-Sigma ADC
- Gain4. Configure 3. Zero/Tare
4 Rev. 0.2 2.2.1. Voltage Reference The voltage reference circuit should be treated as carefully as the measured signal, because noise on the voltage reference degrades ADC performance. The C8051F35x can use its on-chip voltage reference (2.4 V typical) or an externally supplied voltage reference (input to the VREF+ and VREF– pins). For optimal performance, we recommend the use of a high-quality, low-noise external re ference. To filter noise, use a 1.0 µF ceramic capacitor connected between VREF+ and VREF–, placed as close to the pins as possible. Note: When using the internal voltage reference, VREF– must be connected to ground externally. This is typically done by con- necting the VREF– pin directly to the analog ground plane. 2.2.2. Programmable Gain The goal is to match the input signal dynamic range to the dynamic range that can be measured by the ADC (based on voltage reference voltage). This can be accomplished by scaling the voltage reference (VREF) voltage and by amplifying the signal. A larger VREF voltage improv es performance, thus it is better to apply gain to the signal rather than reducing VREF. A signal can be amplified using a combination of an external amplifier and/or the The C8051F35x devices feature an on-chip programmable ga in amplifier (PGA) with eight gain settings. The ADC input gain is selected using the ADC0 Control Register (ADC0CN). AD C0CN[2:0] are the AD0GN bits used to select one of the eight gain settings. (See SFR Definition 2.1.) SFR Definition 2.1. ADC0CN: ADC0 Control Register Bits 7–5: Unused: Read = 000b, Write = don’t care. Bit 4: AD0POL: ADC0 Polarity. 0: ADC operates in Unipolar mode (straight binary result). 1: ADC operates in Bipolar mode (2s compliment result). Bit 3: AD0BCE: ADC0 Burnout Current Source Enable. 0: ADC Burnout current sources disabled. 1: ADC Burnout current sources enabled. Bits 2:0 AD0GN: ADC0 Programmable Gain Setting. 000: PGA Gain = 1. 001: PGA Gain = 2. 010: PGA Gain = 4. 011: PGA Gain = 8. 100: PGA Gain = 16. 101: PGA Gain = 32. 110: PGA Gain = 64. 111: PGA Gain = 128. This SFR can only be modified when ADC0 is in IDLE mode. R R R R/W R/W R/W R/W R/W Reset Value - - - AD0POL AD0BCE AD0GN 00010000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xF4
used to zero or tare a measurement as a function of the end-product and is not intended for calibration. supply range (“low” input buffer). is digitally filtered to obtain large output words). Figure 3. Modulator and Digital Filter
6 Rev. 0.2 Once the modulator clock is configured, the modulator sample rate of the ADC is also set to MDCLK/128. Therefore, the typical sample rate is 2.4576 MHz/128 = 19.2 kHz. This w ill be well above th e signal bandwidth measured, as the maximum output word rate for the ADC is 1 kHz. SFR Definition 2.2. ADC0CLK: ADC0 Modulator Clock Divisor Bits 7–0: ADC0CLK: ADC0 Modulator Clock Divisor. This register establishes the Modulator Clock (MDCLK), by dividing down the system clock (SYSCLK). The input signal is sampled by the modulator at a frequency of MDCLK / 128. For opti- mal performance, the divider should be chosen such that the modulator clock is equal to 2.4576 MHz (modulator sampling rate = 19.2 kHz). The system clock is divided according to the equation: MDCLK = SYSCLK / (ADC0CLK + 1) Note: The Modulator Sampling Rate is not the ADC Output Word Rate. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value ADC0CLK 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xF7
Figure 4. Digital Filter Frequency Response (SINC3) still allowing the minimum required output word rate. The decimation ratio is set in the ADC0 Decimation Ratio High and Low registers (ADC0DECH and ADC0DECL).
8 Rev. 0.2 SFR Definition 2.3. ADC0DECH: ADC0 Decimation Ratio Register High Byte SFR Definition 2.4. ADC0DECL: ADC0 Decimation Ratio Register Low Byte Bits 7–3: Unused: Read = 00000b, Write = don’t care. Bits 2–0: DECI[10:8]: ADC0 Deci mation Ratio Register, Bits 10–8. This register contains the high bits of the 11-bit ADC Decimation Ratio. The decimation ratio deter- mines the output word rate of ADC0, based on the Modulator Clock (MDCLK). See the ADC0DECL register description for more information. This SFR can only be modified when ADC0 is in IDLE mode. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value ----- D E C I 1 0 D E C I 9 D E C I 8 0 0 0 0 0 1 1 1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x9B Bits 7–0: DECI[7:0]: ADC0 Decimation Ratio Register, Bits 7–0. This register contains the low byte of the 11-bit ADC Decimation Ratio. The decimation ratio deter- mines the number of modulator input samples used to generate a single output word from the ADC. The ADC0 decimation ratio is defined as: Decimation Ratio = DECI[10:0] + 1 The corresponding sampling period and output word rate of ADC0 is: ADC0 Conversion Period = [(DECI[10:0] + 1) x 128] / MDCLK ADC0 Output Word Rate = MDCLK / [128 x (DECI[10:0] + 1)] The minimum decimation ratio setting is 20. Any register setting below 19 will automatically be interpreted as 19. Important: When using the fast filter, the decimation ratio must be divisible by 8 (DECI[2:0] = 111b). This SFR can only be modified when ADC0 is in IDLE mode. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value DECI7 DECI6 DECI5 DECI4 DECI3 DECI2 DECI1 DECI0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x9A
Rev. 0.2 9 The ADC’s digital filter gives two options for output: FAST and SINC3. The FAST filter uses results from only the current conversion cycle or period, while the SINC3 filter uses three conversion cycles. The fast filter output reacts more quickly to changes on the analog input, while th e SINC3 filter output produces lower-noise results. Additionally, the SINC3 filter is designed to reject 50 and 60 Hz frequencies (see Figure 4 on page 7). When it is necessary to respond quickly to signal changes or when fast channel switching is required (between different measured signals at the AMUX), the FAST filter should be used. In most cases, the SINC3 filter output is used for best noise performance. Using the FAST Filter: Set the ADC0 Interrupt Select bit (AD0ISEL) bit to 1 in the ADC0 Configuration Register (ADC0CF). This will set the ADC0 end-of-conversion interrupt bit to be set upon a ready result in the FAST filter. The output of the FAST filter is placed in the ADC0FH, ADC0FM, and ADC0FL registers. NOTE: When using the FAST filter, the Decimation Ratio must be divisible by 8. (See SFR Definition 2.4.) Using the SINC3 Filter: Clear the ADC0 Interrupt Select bit (AD0ISEL) bit to 0 in the ADC0 Configuration Register (ADC0CF). This will set the ADC0 end-of-conversion interrupt bit to be set upon a ready result in the SINC3 filter. The output of the SINC3 filter is placed in the ADC0H, ADC0M, and ADC0L registers. 2.2.7. Calibration The C8051F35x family of devices has two, built-in calibrati on functions: internal and system calibration. Each of these calibration options can calibrate for both offset and gain errors. Offset calibration should be performed prior to gain calibration. Calibration coefficients are stored in special function registers (constants are 24-bits) and are user accessible. However, the calibration adjustments are made automatica lly by the ADC, and so no further user calibration adjustment is necessary once the ADC calibration function is complete (i.e., the MCU does not have to condition the ADC outputs for calibration). Internal calibrations (offset and gain) require no external signals to the ADC inputs, but do require the voltage reference input. System calibration uses external signals , and is useful for removing errors due to temperature- induced offset/gain drift, reference voltage drift, offset, and gain errors from the analog front-end circuit. System calibration is performed as follows: Offset: This is done first by applying an external “zero” voltage to the AIN+/AIN– pins. Gain: This is done after offset calibration. A full-scale positive voltage is applied to the AIN+/AIN– pins, for the given current programmable gain amplifier setting. Calibrations are initiated by writing to the ADC0 System Mode Bits (A D0SM) in the ADC0CF register (see SFR Definition 2.5). Section 5.2 of the data sheet details comp lete information concerning the calibration of the ADC. It is recommended that a full self or system calibration be performed at system start-up. An MCU-scheduled regular calibration can be periodically performed for best performance of the measurement system.
10 Rev. 0.2 SFR Definition 2.5. ADC0MD: ADC0 Mode Bit 7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC is in low-power shutdown. 1: ADC0 Enabled. ADC is active and ready to perform calibrations or conversions. Note: Disabling the ADC automatically resets the AD0SM bits back to the “Idle” state. Bit 6: Unused: Read = 0b, Write = don’t care. Bits 5–4: RESERVED: Must Write to 00b. Bit 3: Unused: Read = 0b, Write = don’t care. Bits 2–0: AD0SM: ADC0 System Mode Select. These bits define the operating mode for the ADC. They are used to initiate all ADC conversion and calibration cycles. 000: Idle 001: Full Internal Calibration (offset and gain). 010: Single Conversion. 011: Continuous Conversion. 100: Internal Offset Calibration. 101: Internal Gain Calibration. 110: System Offset Calibration. 111: System Gain Calibration. Note: Any system mode change by the user during a conversion or calibration will termi- nate the operation, and corrupt the result. To write to many of the other ADC registers, the AD0SM bits must be set to IDLE mode (000b). R/W R R/W R/W R R/W R/W R/W Reset Value AD0EN - Reserved Reserved - AD0SM 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xF3
Rev. 0.2 11 3. Hardware Design Designing a low-noise, high-precision measurement system requires not on ly proper ADC configuration, but careful circuit board design and interface considerations as well. For an in-depth discussion concerning proper mixed-signal circuit board design, se e application note, “AN203: Printed Circuit Design Notes.” AN203 covers many topics concerning proper PCB design such as power supply, decoupling, ground circuit, component placement, and routing of traces (lay out guidelines). Also included is a ch ecklist that can be used to ensure all relevant items have been considered for the application. Here is a list of notes concerning the use of the C8051F35x on a circuit board: Use ground planes: Typically a minimum of 4-layers should be used. Connect components’ ground pins directly to the plane. Use copper plane fill between traces on the signal layers, and connect the fill to ground using vias (do not leave “floating” copper). Separate analog and digital ground planes can be used; connect them in one place. Design a few locations for connection so that the best connection can be tested, usually near the ADC or near the power supply to the board. See AN203 for details and recommended layer assignments for ground, power, and signal planes. Avoid ground loops: Unless careful isolation has been designed, all circuit boards and systems must share a common, low-impedance ground connection so they have the same ground potential. This is especially true of the sensor if not on the same board as the ADC. Do not connect a sensor’s ground or negative side wire to a different ground plane than the C8051F35x’s. Connect both sensor wires to AIN+/AIN–, and make another common ground connection between the boards (chassis ground) when applicable. Place components carefully in order to control ground currents: All ground currents from each component must return to the power supply. Place digital, noisy signals and their traces away from analog signals and the analog input circuits connected to the ADC. Avoid ground current return flow in the area of the analog signal path (e.g., digital components placed in such a way that return currents must flow by the anti-alias filters at AIN+ and AIN– pins will degrade performance). See AN203. Keep analog traces away from digital traces: Component placement and orientation will help the designer route digital traces away from the analog signals. Analog traces (including the voltage reference) must be kept as short as possible. Sensor input: The delta-sigma will reject noise (though not at the modulator sample frequency). However, care should be taken to use a simple anti-alias filter and a high-quality amplifier (when applicable). Keep wires as short as possible. Input impedance at AIN+ and AIN– should be matched to preserve common-mode rejection. Reject common-mode and ground noise: Make differential measurements and use twisted wire pairs (shielded if possible). EMI and ground noise that appears equally on both differential inputs to the ADC will not appear in the measurment.
- Delta-Sigma Noise Specifications
of a very small signal voltage; therefore, the noise performance is one of the most important specifications. Figure 7. Histogram Analysis of Noise: Effective Noise vs. Noise-Free Resolution
gives the designer a good idea of the expected ADC noise in a measurement for a given gain and output word rate. This noise information can be used to calculate the effective resolution of the ADC. increase the effective resoution by filtering noise (the averaging is a form of digital filtering). more stringent requirement and can be calculated from the given rms noise value in the data sheet. 6.6 – sigma. Multiplying sigma by 6.6 will allow the calculation noise-free bits in an ADC for a given configuration. Table 1. ADC0 SINC3 Filter Input-Referred Typical rms Noise (µV)
Rev. 0.2 15 Table 1 is a copy of the posted specification of the AD C0’s typical noise table from the C8051F35x family data sheet. This table shows the expected, typical rms noise of the ADC at the ou tput of the SINC3 filter for given decimation ratios and gain settings. If measuring a signal that requires a 10 Hz output word rate with unity gain, we set the decimation ratio for 1920 (remember: use the highest decimation ratio setting possible ). This gives an expected VNOISERMS of 2.38 µV (from Table 1). This is the noise number used to predict the expected effective resolution. With a 2.5 V voltage reference, each LSB in a bipolar measurement is as follows: V REF/223 = 2.5 V/223 = 298 nV. Therefore, the standard deviation (rms noise) in terms of codes is as follows: 2.38 µV/298 nV = ~8 LSBs or output codes of noise. In practical terms, if the analog inputs are grounded fo r a noise test (both AIN+/AIN– are connected to analog ground and a bipolar measurement is made), you could ex pect to observe a standard deviation of 8 codes. This equates to an effective resolution of 23 bits – 3 bits = 20-bits effective resolution (it takes 3 bits to represent a variation of eight binary output codes, so we subtract 3 bits from the signed 24-bit output word). If concerned with noise-free resolution, we proceed with the same method but instead use the rms noise voltage (one standard deviation) multiplied by 6.6. Multiplying the rms noise by 6.6 re sults in a noise level in which 99.9% of all codes will be included. This leaves only the bits that will remain constant from sample-to-sample in our noise test. Again, using the 2.38 µV rms noise voltage (from Table 1), 99.9% of all sampled output codes should be contained within 2.38 µV x 6.6 = 15.7 µV. An LSB = 298 nV, and so the total number of noise-varying bits is as follows: 15.7 µV/298 nV = ~53 codes. 53 bits requires 26 or 6-bits of a digital code to represent 53 different output codes, and so 23 bits – 6 bits = 17-bits of noise-free resolution.
16 Rev. 0.2 DOCUMENT CHANGE LIST Revision 0.1 to Revision 0.2 Updated text on page 15.
Rev. 0.2 17 NOTES:
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