AKD4368

AKD4368 AKM | Alldatasheet

Document overview

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• PDF pages: 39

Technical content

• Compatible with 2 types of interface - Direct interface with AKM’s A/D converter evaluation boards - On-board AK4114 as DIR which accepts optical input
• 10pin header for serial control interface GND AK4114 (DIR) Opt In A/D Data 10pin Header AK4368 LIN RIN MIN HPL HPR 1.6 ~ 3.6V LOUT ROUT Regulator 5.0V 3.0V

Figure 1. AKD4368 Block Diagram

• Circuit diagram and PCB layout are attached at the end of this manual.

1) Set up the power supply lines. Each supply line should be distributed from the power supply unit. for the AK4368 and AK4114. About the AK4368’s audio interface format, refer to datasheet of the AK4368. About the AK4114’s audio interface format, refer to Table 2 in this manual. supplied from DSP. It is possible to evaluate at various sampling frequencies using built-in the AK4368’s PLL. Figure 2. PLL Master Mode

The system clock can be supplied by two ways below. (DIR). MCKO is needed for a synchronous singal of BICK and LRCK. M/S should be set to “L” for SW1. Figure 3. PLL Slave Mode supplied from J17 or PORT3. Setup of jumper pins is same as (1)PLL Master Mode.

Figure 4. EXT Slave Mode connector (TORX176). Nothing should be connected to PORT3 (DSP) and J17. JP17(EXT)should be short. CM0 and M/S should be set to “L” for SW1. set to “x1” and JP15 (BCFS) should be set to “64fs”. The AK4114 does not operate under fs = 32kHz. Therefore, this mode corresponds to fs = 32kHz and over. connected to PORT1 (DIR). JP17(EXT) should be short. (MKFS) should be set to “x1” and JP15 (BCFS) should be set to “64fs”.

Table 1. Mode Setting for AK4368 and AK4114 Table 2. Setting for AK4114 audio interface format

1. JP1 (GND) : Analog ground and Digital ground
2. JP14 (MKFS) : MCLK Frequency
3. JP15 (BCFS) : BICK Frequency

Upper-side is “H” and lower-side is “L”. [SW2] (DIR): Power down of AK4114. Keep “H” during normal operation. Keep “L” when the AK4114 is not used. [SW3] (PDN): Power down of AK4368. Keep “H” during normal operation. [LED1] (ERF): Monitor INT0 pin of the AK4114. LED turns on when some error has occurred to AK4114.

(CTRL) with PC by 10 wire flat cable packed with the AKD4368.

10 Wire Flat Cable

Figure 5. Connect of 10 wire flat cable

Figure 8. HPL, HPR Output Circuit 2)-1. Outputs of HPL and HPR pins are applied via J2 and J8. 2)-2. Outputs of HPL and HPR pins are applied via J5.

• AKM assumes no responsibility for the trouble when using the circuit examples.

[AKD4368-A] <KM077800> - 9 - 2. Control Software Manual „ Set-up of evaluation board and control software 1. Set up the AKD4368 according to previous term. 2. Connect IBM-AT compatible PC with AKD4368 by 10-line type flat cable (packed with AKD4368). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”. In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled “AK4368 Evaluation Kit” into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of “akd4368.exe” to set up the control program. 5. Then please evaluate according to the follows. „ Operation flow Keep the following flow. 1. Set up the control program according to explanation above. 2. Click “Port Reset” button. 3. Click “Write default” button „ Explanation of each buttons 1. [Port Reset] : Set up the USB interface board (AKDUSBIF-A) when using the board. 2. [Write default] : Initialize the register of AK4368. 3. [All Write] : Write all registers that is currently displayed. 4. [Function1] : Dialog to write data by keyboard operation. 5. [Function2] : Dialog to write data by keyboard operation. 6. [Function3] : The sequence of register setting can be set and executed. 7. [Function4] : The sequence that is created on [Function3] can be assigned to buttons and executed. 8. [Function5]: The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. 9. [SAVE] : Save the current register setting. 10. [OPEN] : Write the saved values to all register. 11. [Write] : Dialog to write data by mouse operation. „ Indication of data Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the part that is not defined in the datasheet.

[AKD4368-A] <KM077800> - 10 - „ Explanation of each dialog 1. [Write Dialog]: Dialog to write data by mouse operation There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data If you want to write the input data to AK4368, click [OK] button. If not, click [Cancel] button. 2. [Function1 Dialog] : Dialog to write data by keyboard operation Address Box: Input registers address in 2 figures of hexadecimal. Data Box: Input registers data in 2 figures of hexadecimal. If you want to write the input data to AK4368, click [OK] button. If not, click [Cancel] button. 3. [Function2 Dialog] : Dialog to evaluate DATT There are dialogs corresponding to register of 05h and 06h. Address Box: Input registers address in 2 figures of hexadecimal. Start Data Box: Input starts data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to AK4368 by this interval. Step Box: Data changes by this step. Mode Select Box: If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 If you want to write the input data to AK4368, click [OK] button. If not, click [Cancel] button.

[AKD4368-A] <KM077800> - 11 - 4. [SAVE] and [OPEN] 4-1. [SAVE] All of current register setting values displayed on the main window are saved to the file. The extension of file name is “akr”. <Operation flow> (1) Click [SAVE] Button. (2) Set the file name and click [SAVE] Button. The extension of file name is “akr”. 4-2. [OPEN] The register setting values saved by [SAVE] are written to the AK4368. The file type is the same as [SAVE]. <Operation flow> (1) Click [OPEN] Button. (2) Select the file (*.akr) and Click [OPEN] Button.

The sequence of register setting can be set and executed. setting sequence is used. Go to (2) if the other setting sequence is required. (2) Set the control sequence. Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused. (3) Click [START] button. Then this sequence is executed. The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step. Figure 9. Window of [F3]

The sequence file (*.aks) saved by [Function3] can be listed up to 10 files, assigned to buttons and then executed. When [F4] button is clicked, the window as shown in Figure 10 opens. Figure 10. [F4] window

(1) Click [OPEN] button and select the sequence file (*.aks) saved by [Function3]. Figure 11. [F4] window(2) (2) Click [START] button, then the sequence is executed. [OPEN] : The name assign of sequence file(*.ak4) saved by [SAVE] is loaded. (1) This function doesn't support the pause function of sequence function. (2) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder.

buttons and then executed. When [F5] button is clicked, the window as shown in Figure 12 opens. Figure 12. [F5] window (1) Click [OPEN] button and select the register setting file (*.akr). (2) Click [WRITE] button, then the register setting is executed.

Figure 13. [F5] windows(2) [OPEN] : The name assign of register setting file(*.ak5) saved by [SAVE] is loaded. (1) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder. loaded again in order to reflect the change.

[AKD4368-A] <KM077800> - 17 - MEASUREMENT RESULTS [Measurement condition]

• Measurement unit : Audio Precession System Two Cascade
• MCLK : 11.2896MHz
• BICK : 64fs
• fs : 44.1kHz
• Bit : 24bit
• Measurement mode : EXT Slave mode
• Power Supply : VDD = HVDD = 3.3V
• Measurement Filter : 10Hz ∼ 20kHz
• Temperature : Room Parameter DAC Analog Output Characteristics Result (Lch / Rch) Unit DAC -> HPAMP THD+N (-3dBFS Output) -56.5 / -57.0 dB D-Range (-60dB Output, A-weighted) 90.7 / 90.7 dB S/N (A-weighted) 90.8 / 90.8 dB DAC -> LOUT THD+N (0dBFS Output) -75.8 / -75.7 dB D-Range (-60dB Output, A-weighted) 88.7 / 88.4 dB S/N (A-weighted) 88.7 / 88.4 dB

Figure 22. Crosstalk

• These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status.
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• AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.

A A B B C C D D E E E E D D C C B B A A HVDD AVDD LIN RIN MIN 4368_BICK 4368_LRCK 4368_SDATA SCL/CCLK CAD0/CSN DVDD DVDD HPL HPR 4368_MCKO 4368_PDN SDA/CDTI LOUT ROUT 4368_I2C EXT_MCLK SDTO CDTO Title Size Document Number Rev Date: Sheet of AK4368 A AKD4368-A Rev.0 Friday, January 07, 2005 Title Size Document Number Rev Date: Sheet of AK4368 A AKD4368-A Rev.0 Friday, January 07, 2005 Title Size Document Number Rev Date: Sheet of AK4368 A AKD4368-A Rev.0 Friday, January 07, 2005 DGND AGND C12 10u C12 10u TP29 3DCAP3 TP29 3DCAP3 10k 10k TP17 AVSS TP17 AVSS (short) (short) TP22 ROUT TP22 ROUT TP27 3DCAP1 TP27 3DCAP1 (short) (short) TP4 PDN TP4 PDN TP3 DVSS TP3 DVSS TP5 CAD0/CSN TP5 CAD0/CSN C11 0.1u C11 0.1u TP25 VCOC TP25 VCOC TP24 RIN TP24 RIN C14 470n C14 470n 10u 10u C17(open) C17(open) CN2 CN2 TP15 VCOM TP15 VCOM TP11 BICK TP11 BICK 0.1u 0.1u TP16 HVDD TP16 HVDD TP9 SDATA TP9 SDATA CN1 CN1 CN4 CN4 TP14 MCKI TP14 MCKI C15 4.7n C15 4.7n JP1 GND JP1 GND TP28 3DCAP2 TP28 3DCAP2 TP6 SCL/CCLK TP6 SCL/CCLK C10 4.7n C10 4.7n TP26 LIN TP26 LIN NC MCKO DVSS DVDD MCKI I2C BICK LRCK SDA/CDTI SDATA NC SCL/CCLK NC CAD0/CSN PDN NC NC 3DCAP1 3DCAP2 3DCAP3 LOUT ROUT NC VCOM AVDD MUTET HVDD AVSS HVSS HPR NC NC HPL MIN NC RIN VCOC LIN PVSS PVDD NC AK4368 AK4368 TP2 PVDD TP2 PVDD 0.1u 0.1u TP23 MIN TP23 MIN TP18 HVSS TP18 HVSS (short) (short) TP13 DVDD TP13 DVDD C16 10u C16 10u TP21 LOUT TP21 LOUT 0.1u 0.1u 10u 10u C13 47u C13 47u TP7 SDA/CDTI TP7 SDA/CDTI TP8 I2C TP8 I2C TP12 MCKO TP12 MCKO CN3 CN3 TP20 HPL TP20 HPL TP19 HPR TP19 HPR TP10 LRCK TP10 LRCK 47u 47u 2.2u 2.2u 0.1u 0.1u TP1 AVDD TP1 AVDD

A A B B C C D D E E E E D D C C B B A A LIN RIN MIN HPR HPL LOUT ROUT Title Size Document Number Rev Date: Sheet of Input/Output A AKD4368-A Rev.0 Friday, December 24, 2004 Title Size Document Number Rev Date: Sheet of Input/Output A AKD4368-A Rev.0 Friday, December 24, 2004 Title Size Document Number Rev Date: Sheet of Input/Output A AKD4368-A Rev.0 Friday, December 24, 2004 HP BNC HP BNC HPL HPL R33 10k R33 10k R13 R13 R19 6.8 R19 6.8 R14(short) R14(short) C33 22u C33 22u LIN LIN R12 6.8 R12 6.8 JP3 HPL JP3 HPL J16 ROUT J16 ROUT R18(short) R18(short) C22 47u C22 47u R29 220 R29 220 HPR HPR C21 C21 RIN RIN C37 22u C37 22u R11(short) R11(short) R32 220 R32 220 JP5 HPR JP5 HPR MIN MIN R30 10k R30 10k HP HP C23 C23 C27 47u C27 47u J14 LOUT J14 LOUT C26 C26 R21 R21

A A B B C C D D E E E E D D C C B B A A VCC VCC EXT_MCLK X_LRCK DIR_MCLK MCKO EXT_BICK BICK DIR_BICK Title Size Document Number Rev Date: Sheet of CLOCK A AKD4368-A Rev.0 Friday, December 24, 2004 Title Size Document Number Rev Date: Sheet of CLOCK A AKD4368-A Rev.0 Friday, December 24, 2004 Title Size Document Number Rev Date: Sheet of CLOCK A AKD4368-A Rev.0 Friday, December 24, 2004 EXT DIR MCKO 64fs 32fs INV THR DIR ADC D CLK Q Q PR CL U4A 74AC74 U4A 74AC74 R35 R35 U2A 74HC14 U2A 74HC14 JP16 MCLK JP16 MCLK J17 EXT J17 EXT JP13 BICK JP13 BICK D CLK Q Q PR CL U4B 74AC74 U4B 74AC74 JP14 MKFS JP14 MKFS JP17 EXT JP17 EXT CLK RST Q10 Q11 Q12 74HC4040 74HC4040 JP12 PHASE JP12 PHASE JP15 BCFS JP15 BCFS

A A B B C C D D E E E E D D C C B B A A VCC VCC VCC VCC VCC VCC VCC SDTO DIR_SDTI DIR_BICK DIR_LRCK DIR_MCLK CAD0 CM0 CM0 REG REG DAUX REG CAD1 I2C M/S Title Size Document Number Rev Date: Sheet of DIR/DIT A AKD4368-A Rev.0 Friday, December 24, 2004 Title Size Document Number Rev Date: Sheet of DIR/DIT A AKD4368-A Rev.0 Friday, December 24, 2004 Title Size Document Number Rev Date: Sheet of DIR/DIT A AKD4368-A Rev.0 Friday, December 24, 2004 H L DIF0 DIF2 CAD0 CM0 for 74AC74, 74HC4040, 74HC14, 74HCT157, 74LS07, 74HCT04 CAD1 I2C M/S C45 0.1u C45 0.1u +C48 10u +C48 10u U2B 74HC14 U2B 74HC14 C51 0.47u C51 0.47u C43 0.1u C43 0.1u R38 R38 R39 10k R39 10k C44 0.1u C44 0.1u 47u 47u C46 0.1u C46 0.1u U6A 74HCT04 U6A 74HCT04 OUT VCC GND GND PORT1 DIR PORT1 DIR GND IF VCC IN PORT2 DIT PORT2 DIT C57 10u C57 10u C54 C54 C50 0.1u C50 0.1u C40 0.1u C40 0.1u C41 0.1u C41 0.1u LED1 ERF LED1 ERF RP1 47k RP1 47k C55 0.1u C55 0.1u U6B 74HCT04 U6B 74HCT04 R40 R40 C56 0.1u C56 0.1u C49 10u C49 10u C42 0.1u C42 0.1u C47 0.1u C47 0.1u VIN VOUT GND TO92 TO92 C53 0.1u C53 0.1u SW1 MODE SW1 MODE + C38 47u + C38 47u 11.2896MHz 11.2896MHz U6C 74HCT04 U6C 74HCT04 C52 C52 U2C 74HC14 U2C 74HC14 10u 10u R36 470 R36 470 SW2 DIR SW2 DIR C39 0.1u C39 0.1u C59 0.1u C59 0.1u IPS0 NC DIF0 TEST2 DIF1 NC DIF2 IPS1 P/SN XTL0 XTL1 TVDD DVSS TX0 TX1 BOUT COUT UOUT VOUT DVDD DVSS MCKO1 BICK MCKO2 DAUX XTO XTI PDN CM0 CM1 OCKS1 OCKS0 INT0 AVDD R VCOM AVSS RX0 NC RX1 TEST1 RX2 NC RX3 VIN LRCK SDTO INT1 AK4114 AK4114 HSU119 HSU119 C58 10u C58 10u R37 18k R37 18k

A A B B C C D D E E E E D D C C B B A A D3V VCC VCC VCC D3V 4368_PDN CAD0/CSN SCL/CCLK 4368_SDATA 4368_I2C 4368_LRCK 4368_BICK D3V D3V DAUX BICK DIR_SDTI EXT_MCLK EXT_BICK DIR_LRCK X_LRCK 4368_MCKO M/S MCKO CDTO SDA/CDTI CAD1 I2C I2C CAD0 Title Size Document Number Rev Date: Sheet of LOGIC A AKD4368-A Rev.0 Friday, December 24, 2004 Title Size Document Number Rev Date: Sheet of LOGIC A AKD4368-A Rev.0 Friday, December 24, 2004 Title Size Document Number Rev Date: Sheet of LOGIC A AKD4368-A Rev.0 Friday, December 24, 2004 LRCK ADC ADC DIR MCLK VCC SDTI DIR BICK SCL/CCLK CDTO/SDA(ACK) SDA/CDTI CSN L H JP19 SDTI JP19 SDTI RP2 47k RP2 47k U2D 74HC14 U2D 74HC14 R42 R42 JP18 LRCK JP18 LRCK R41 R41 DIR G VCC GND 74ALVC245 74ALVC245 RP3 47k RP3 47k R48 10k R48 10k SW3 PDN SW3 PDN R46 10k R46 10k C61 0.1u C61 0.1u A/B G 74HCT157 74HCT157 R45 470 R45 470 C60 0.1u C60 0.1u U10A 74LS07 U10A 74LS07 R50 10k R50 10k PORT3 ROM PORT3 ROM + C62 47u + C62 47u R51 1.8k R51 1.8k U2E 74HC14 U2E 74HC14 R49 470 R49 470 R43 10k R43 10k VCC GND 74LVC541 74LVC541 C63 0.1u C63 0.1u R44 10k R44 10k HSU119 HSU119 R47 470 R47 470 R52 R52 PORT4 CTRL PORT4 CTRL

A A B B C C D D E E E E D D C C B B A A Title Size Document Number Rev Date: Sheet of PIN A AKD4638-A Rev.0 Friday, December 24, 2004 Title Size Document Number Rev Date: Sheet of PIN A AKD4638-A Rev.0 Friday, December 24, 2004 Title Size Document Number Rev Date: Sheet of PIN A AKD4638-A Rev.0 Friday, December 24, 2004 U6E 74HCT04 U6E 74HCT04 U10C 74LS07 U10C 74LS07 U10F 74LS07 U10F 74LS07 U10D 74LS07 U10D 74LS07 U6D 74HCT04 U6D 74HCT04 U6F 74HCT04 U6F 74HCT04 U10E 74LS07 U10E 74LS07 U2F 74HC14 U2F 74HC14 U10B 74LS07 U10B 74LS07

A A B B C C D D E E E E D D C C B B A A Title Size Document Number Rev Date: Sheet of AK4368 A AK4368-SUB for 41BGA Friday, January 07, 2005 Title Size Document Number Rev Date: Sheet of AK4368 A AK4368-SUB for 41BGA Friday, January 07, 2005 Title Size Document Number Rev Date: Sheet of AK4368 A AK4368-SUB for 41BGA Friday, January 07, 2005 TP7 SDA/CDTI TP7 SDA/CDTI 10u 10u R17 10k R17 10k TP4 PDN TP4 PDN 0.1u 0.1u TP29 3DCAP3 TP29 3DCAP3 CN1 CN1 0.1u 0.1u TP2 PVDD TP2 PVDD TP27 3DCAP1 TP27 3DCAP1 C11 0.1u C11 0.1u NC MCKO DVSS DVDD MCKI I2C BICK LRCK SDA/CDTI SDATA NC SCL/CCLK NC CAD0/CSN PDN NC NC 3DCAP1 3DCAP2 3DCAP3 LOUT ROUT NC VCOM AVDD MUTET HVDD AVSS HVSS HPR NC NC HPL MIN NC RIN VCOC LIN PVSS PVDD NC AK4368 AK4368 TP6 SCL/CCLK TP6 SCL/CCLK C12 10u C12 10u 0.1u 0.1u TP13 DVDD TP13 DVDD CN4 CN4 TP22 ROUT TP22 ROUT (short) (short) TP20 HPL TP20 HPL TP9 SDATA TP9 SDATA TP23 MIN TP23 MIN CN2 CN2 TP8 I2C TP8 I2C TP11 BICK TP11 BICK TP5 CAD0/CSN TP5 CAD0/CSN TP17 AVSS TP17 AVSS TP16 HVDD TP16 HVDD TP25 VCOC TP25 VCOC 10u 10u TP14 MCKI TP14 MCKI C15 4.7n C15 4.7n 0.1u 0.1u C16 10u C16 10u C17(open) C17(open) 2.2u 2.2u TP18 HVSS TP18 HVSS TP15 VCOM TP15 VCOM TP1 AVDD TP1 AVDD TP10 LRCK TP10 LRCK TP12 MCKO TP12 MCKO TP19 HPR TP19 HPR TP28 3DCAP2 TP28 3DCAP2 C14 470n C14 470n C46 C46 TP3 DVSS TP3 DVSS C10 4.7n C10 4.7n CN3 CN3 TP24 RIN TP24 RIN TP26 LIN TP26 LIN TP21 LOUT TP21 LOUT