AK4356 AKM | Alldatasheet
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ASAHI KASEI [AK4356] M0072-E-01 1999/09 - 1 - GENERAL DESCRIPTION The AK4356 is a high performance six channels DAC corresponding to 96kHz sampling mode of DVD. Two channels of them can operate up to 192kHz sampling fully correspond to DVD-Audio standards. The AK4356 introduces the advanced multi-bit architecture for DS modulator. This new architecture achieves the wider dynamic range, while keeping much the same superior distortion characteristics as conventional Single Bit way. In the AK4356, the analog outputs are filtered in the analog domain by switched-capacitor filter (SCF) with high tolerance to clock jitter. The analog outputs are full differential output, so the device is suitable for hi-end applications.
FEATURES
o Sampling Rate up to 192kHz for 2 channels mode, 96kHz for 6 channels mode o 24Bit 8 times Digital Filter with Slow roll-off option Ripple: –0.005dB, Attenuation: 75dB o THD+N: -94dB o DR, S/N: 112dB o High Tolerance to Clock Jitter o Low Distortion Differential Output o Channel Independent Digital De-emphasis for 32, 44.1 & 48kHz sampling o Channel Independent Zero Detect Pin o Channel Independent Digital Attenuator with soft-transition o Soft Mute o 3-wire Serial Interface for Volume Control o I/F format: MSB justified, LSB justified, I2S o TTL Level Digital I/F o Master Clock Normal Speed: 256fs, 384fs, 512fs or 768fs Double Speed: 128fs, 192fs, 256fs or 384fs o Power Supply: 4.75 to 5.25V o 44pin LQFP Package o Ta: -40 to 85°C 192kHz 24Bit Six-Channel DAC for DVD-Audio AK4356
ASAHI KASEI [AK4356] M0072-E-01 1999/09 - 2 - n Block Diagram SCF DAC DATT DZFL1 LOUT1+ LOUT1- SCF DAC DATT DZFR1 ROUT1+ ROUT1- SCF DAC DATT DZFL2 LOUT2+ LOUT2- SCF DAC DATT DZFR2 ROUT2+ ROUT2- SCF DAC DATT DZFL3 LOUT3+ LOUT3- SCF DAC DATT DZFR3 ROUT3+ ROUT3- Audio I/F Control Register AK4356 MCLK LRCK BICK MCK O LRCK BICK XTI XTO Controller CS CCLK CDTI LRCK BICK SDOUT1 SDOUT2 SDOUT3 AC3 SDTI1 SDTI2 SDTI3
ASAHI KASEI [AK4356] M0072-E-01 1999/09 - 3 - n Ordering Guide AK4356VQ -40 ~+85°C 44pin LQFP(0.8mm pitch) AKD4356 Evaluation Board n Pin Layout LOUT1- ROUT 1+ LOUT1+ DZFL2 3 DZFR1 4 DZFL1 C AD0 6 C AD1 7 PDN 8 BICK MCLK 10 DVDD 11 ROUT 1-43 LOUT 2+42 LOUT 2-41 ROUT 2+40 ROUT 2-39 LOUT 3+38 LOUT 3-37 ROUT 3+36 ROUT 3-35 AVSS34 DVSS 12 SDTI1 13 SDTI2 14 SDTI3 15 LRCK 16 SMUTE 17 CCLK 18 CDTI 19 CSN 20 DFS 0 21 CKS 0 22 AVDD VREFH DZFR2 DZFL3 DZFR3 DZFE DIF2 DIF1 DIF0 CKS2 CKS1 AK4356VQ Top View
ASAHI KASEI [AK4356] M0072-E-01 1999/09 - 4 - PIN/FUNCTION No. Pin Name I/O Function
1 LOUT1- O DAC1 Lch Negative Analog Output Pin
2 LOUT1+ O DAC1 Lch Positive Analog Output Pin
3 DZFL2 O DAC2 Lch Zero Input Detect Pin
4 DZFR1 O DAC1 Rch Zero Input Detect Pin
5 DZFL1 O DAC1 Lch Zero Input Detect Pin
6 CAD0 I Chip Address 0 Pin
7 CAD1 I Chip Address 1 Pin
8 PDN I Power-Down & Reset Pin
When “L”, the AK4356 is powered-down and the control registers are reset to default state. If the state of CAD0-1 changes, then the AK4356 must be reset by PDN.
9 BICK I Audio Serial Data Clock Pin
10 MCLK I Master Clock Input Pin
11 DVDD - Digital Power Supply Pin, +4.75~+5.25V
12 DVSS - Digital Ground Pin
13 SDTI1 I DAC1 Audio Serial Data Input Pin
14 SDTI2 I DAC2 Audio Serial Data Input Pin
15 SDTI3 I DAC3 Audio Serial Data Input Pin
16 LRCK I Audio Input Channel Clock Pin
17 SMUTE I Soft Mute Pin (Note)
When this pin goes to “H”, soft mute cycle is initialized. When returning to “L”, the output mute releases.
18 CCLK I Control Data Clock Pin
19 CDTI I Control Data Input Pin
20 CSN I Chip Select Pin
This pin should be held to “H” except for access.
ASAHI KASEI [AK4356] M0072-E-01 1999/09 - 5 - No. Pin Name I/O Function
21 DFS0 I Double Speed Sampling Mode 0 Pin (Note)
“L”: Normal Speed, “H”: Double Speed at DFS1 bit = “0”.
22 CKS0 I Input Clock Select 0 Pin (Note)
23 CKS1 I Input Clock Select 1 Pin (Note)
24 CKS2 I Input Clock Select 2 Pin (Note)
25 DIF0 I Audio Data Interface Format 0 Pin (Note)
26 DIF1 I Audio Data Interface Format 1 Pin (Note)
27 DIF2 I Audio Data Interface Format 2 Pin (Note)
28 DZFE I Zero Input Detect Enable Pin (Note)
29 DZFR3 O DAC3 Rch Zero Input Detect Pin
30 DZFL3 O DAC3 Lch Zero Input Detect Pin
31 DZFR2 O DAC2 Rch Zero Input Detect Pin
32 VREFH I Positive Voltage Reference Input Pin, AVDD
33 AVDD - Analog Power Supply Pin
34 AVSS - Analog Ground Pin, +4.75~+5.25V
35 ROUT3- O DAC3 Rch Negative Analog Output Pin
36 ROUT3+ O DAC3 Rch Positive Analog Output Pin
37 LOUT3- O DAC3 Lch Negative Analog Output Pin
38 LOUT3+ O DAC3 Lch Positive Analog Output Pin
39 ROUT2- O DAC2 Rch Negative Analog Output Pin
40 ROUT2+ O DAC2 Rch Positive Analog Output Pin
41 LOUT2- O DAC2 Lch Negative Analog Output Pin
42 LOUT2+ O DAC2 Lch Positive Analog Output Pin
43 ROUT1- O DAC1 Rch Negative Analog Output Pin
44 ROUT1+ O DAC1 Rch Positive Analog Output Pin
Note:SMUTE, DFS0, CKS0, CKS1, CKS2, DIF0, DIF1, DIF2, DZFE pins are ORed with serial control register.
ASAHI KASEI [AK4356] M0072-E-01 1999/09 - 6 - ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS=0V; Note 1) Parameter Symbol min max Units Power Supplies Analog Digital |AVSS-DVSS| (Note 2) AVDD DVDD DGND -0.3 -0.3 6.0 6.0 0.3 V V V Input Current (any pins except for supplies) IIN - –10 mA Analog Input Voltage VINA -0.3 AVDD+0.3 V Digital Input Voltage VIND -0.3 DVDD+0.3 V Ambient Temperature Ta -40 85 °C Storage Temperature Tstg -65 150 °C Note:1. All voltages with respect to ground. 2. AVSS and DVSS must be connected to the same analog ground plane. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS=0V; Note 1) Parameter Symbol min typ max Units Power Supplies (Note 3) Analog Digital AVDD DVDD 4.75 4.75 5.0 5.0 5.25 5.25 V V Note:1. All voltages with respect to ground. 3. The power up sequence between AVDD and DVDD is not critical. *AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
ASAHI KASEI [AK4356] M0072-E-01 1999/09 - 7 - ANALOG CHARACTERISTICS (Ta=25°C; AVDD, DVDD=5V; AVSS, DVSS=0V; VREFH=AVDD; fs=44.1kHz; BICK=64fs; Signal Frequency =1kHz; 24bit Data; RL‡2kW; Measurement Frequency=20Hz~20kHz at 44.1kHz, 20Hz~40kHz at fs=96kHz, 20Hz~80kHz at fs=192kHz; unless otherwise specified) Parameter min typ max Units Dynamic Characteristics (Note 4) Resolution 24 Bits S/(N+D) fs=44.1kHz fs=96kHz dB dB DR (-60dBFS) fs=44.1kHz, A-weighted fs=96kHz 106 112 105 dB dB S/N (Note 5,6) fs=44.1kHz, A-weighted fs=96kHz 106 112 105 dB dB Interchannel Isolation 90 110 dB DC Accuracy Interchannel Gain Mismatch 0.2 0.5 dB Gain Drift (Note 7) 20 -ppm/°C Output Voltage (AOUT+) - (AOUT-) (Note 8)–2.55 –2.75 –2.95 Vpp Load Resistance (Note 9) 2 kW Load Capacitance 25 pF Power Supply Rejection (Note 10) 50 dB Power Supplies Power Supply Current Normal Operation (PDN = “H”) AVDD DVDD (fs=44.1kHz) (fs=96kHz) (fs=192kHz) Power-Down-Mode (PDN = “L”) AVDD+DVDD (Note 11) 100 mA mA mA mA mA Note: 4. Measured by UPD(ROHDE & SCHWARZ). Refer to the evaluation board manual. 5. 107dB at CCIR-ARM weighted 6. S/N is independent of input bit length. 7. VREFH is constantly +5.0V. 8. Full scale voltage (0dB). Output voltage scales with the voltage of VREFH pin. AOUT(typ.@0dB)=(AOUT+)-(AOUT-)=–2.75Vpp*VREFH/5.0 9. AC load 10. PSR is applied to AVDD, DVDD with 1kHz, 100mVpp. VREFH pin is held a constant voltage. 11. All digital input pins including clock pins (MCLK, BICK and LRCK) are connected to DVSS.
ASAHI KASEI [AK4356] M0072-E-01 1999/09 - 8 - FILTER CHARACTERISTICS (fs=44.1kHz) (Ta=25°C; AVDD, DVDD=4.75 ~5.25V; fs=44.1kHz; DFS1 = DFS0 = “0”; DEM=OFF) Parameter Symbol min typ max Units Digital Filter Passband (Note 12) ±0.01dB -6.0dB PB 0 - 22.05 20.0 kHz kHz Stopband (Note 12) SB 24.1 kHz Passband Ripple PR –0.005 dB Stopband Attenuation SA 75 dB Group Delay (Note 13) GD - 27.2 - 1/fs Digital Filter + SCF Frequency Response: 0~20.0kHz FR - –0.2 -d B Note:12. The passband and stopband frequencies scale with fs. For example, PB=0.4535*fs(@±0.01dB), SB=0.546*fs. 13. The calculating delay time which occurred by digital filtering. This time is from setting the 16/20/24bit data of both channels on the input register to the output of analog signal. FILTER CHARACTERISTICS (fs=96kHz) (Ta=25°C; AVDD, DVDD=4.75 ~5.25V; fs=96kHz; DFS1 = “0”; DFS0 = “1”; DEM=OFF) Parameter Symbol min typ max Units Digital Filter Passband (Note 14) ±0.01dB -6.0dB PB 0 - 48.0 43.5 kHz kHz Stopband (Note 14) SB 52.5 kHz Passband Ripple PR –0.005 dB Stopband Attenuation SA 75 dB Group Delay (Note 13) GD - 27.2 - 1/fs Digital Filter + SCF Frequency Response: 0~40.0kHz FR - –0.3 -d B Note:14. The passband and stopband frequencies scale with fs. For example, PB=0.4535*fs(@±0.01dB), SB=0.546*fs.
ASAHI KASEI [AK4356] M0072-E-01 1999/09 - 9 - FILTER CHARACTERISTICS (fs=192kHz) (Ta=25°C; AVDD, DVDD=4.75 ~5.25V; fs=192kHz; DFS1 = “1”; DFS0 = “0”; DEM=OFF) Parameter Symbol min typ max Units Digital Filter Passband (Note 15) ±0.01dB -6.0dB PB 0 - 96.0 87.0 kHz kHz Stopband (Note 15) SB 105 kHz Passband Ripple PR –0.005 dB Stopband Attenuation SA 75 dB Group Delay (Note 13) GD - 27.2 - 1/fs Digital Filter + SCF Frequency Response: 0~80.0kHz FR - –0.5 -d B Note:15. The passband and stopband frequencies scale with fs. For example, PB=0.4535*fs(@±0.01dB), SB=0.546*fs. DIGITAL CHARACTERISTICS (Ta=25°C; AVDD, DVDD=4.75 ~5.25V) Parameter Symbol min typ max Units High-Level Input Voltage Low-Level Input Voltage VIH VIL 2.2 0.8 V V Hight-Level Output Voltage (Iout= -100mA) Low-Level Output Voltage (Iout= 100mA) VOH VOL DVDD-0.5 0.5 V V Input Leakage Current Iin - - –10 mA
ASAHI KASEI [AK4356] M0072-E-01 1999/09 - 10 - SWITCHING CHARACTERISTICS (Ta=25°C; AVDD, DVDD=4.75 ~5.25V; CL=20pF) Parameter Symbol min typ max Units Master Clock Timing Frequency Duty fCLK Duty 8.192 36.864 MHz LRCK frequency (Note 16) Normal Speed Mode (DFS1-0 = “00”) Double Speed Mode (DFS1-0 = “01”) 4 times Speed Mode (DFS1-0 = “10”) Duty Cycle fsn fsd fsq Duty 128 192 kHz kHz kHz Serial Interface Timing BICK Period Normal Speed Mode Double Speed Mode 4 times Speed Mode BICK Pulse Width Low Pulse Width High BICK “›” to LRCK Edge (Note 17) LRCK Edge to BICK “›” (Note 17) SDTI Hold Time SDTI Setup Time tBCK tBCK tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS 1/128fs 1/64fs 1/64fs ns ns ns ns ns ns ns ns ns Control Interface Timing CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN “H” Time Rise Time of CSN Fall Time of CSN Rise Time of CCLK Fall Time of CCLK tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tR1 tF1 tR2 tF2 200 150 ns ns ns ns ns ns ns ns ns ns ns ns Power-down/Reset Timing PDN Pulse Width (Note 18) tPDW 150 ns Note:16. If sampling speed mode (DFS0-1) changes, please reset by PDN pin or RSTN bit. 17. BICK rising edge must not occur at the same time as LRCK edge. 18. The AK4356 can be reset by PDN pin “L” upon power up. If CKS0-2 or DFS0-1 changes, the AK4356 should be reset by PDN pin or RSTN bit.
ASAHI KASEI [AK4356] M0072-E-01 1999/09 - 11 - n Timing Diagram VIH MCLK VIL tCLK VIH LRCK VIL 1/fs tBCK tBCKL VIH tBCKH BICK VIL Clock Timing tLRB LRCK VIH BICK VIL tSDS VIH SDTI VIL tSDH VIH VIL tBLR Audio Interface Timing
ASAHI KASEI [AK4356] M0072-E-01 1999/09 - 12 - tCSS CSN VIH CCLK VIL VIH CDTI VIL VIH VIL C1 C0 R/W A4 tCCKL tCCKH tCDS tCDH WRITE Command Input Timing CSN VIH CCLK VIL VIH CDTI VIL VIH VIL D3 D2 D1 D0 tCSW tCSH WRITE Data Input Timing tPDW VIL PDN Power-down & Reset Timing
or CKS2-0 changes, the AK4356 should be reset by PDN pin or RSTN bit. Table 1. System Clock (DFS1-0 = “11”: reserved) Table 2. Example of System Clock [MHz]
justified formats by zeroing the unused LSBs.
3011 I 2 S L / H 32fs or ‡48fs Figure 4
Table 3. Audio data format Figure 1. Mode 0 Timing
Figure 4. Mode 3 Timing The AK4356 includes channel independent digital output volumes (ATT) with 256 levels at 0.5dB steps including MUTE. levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. Table 4. De-emphasis filter control with DEM1-0 (DFS1-0 = “00”)
01 O F F
10 O F F
11 O F F
Table 5. De-emphasis filter control with DFS1-0
DZFE bit. In this case, DZF pins of all channels are always “L” (except for the case of RSTN = “0”). without stopping the signal transmission. (1) The output signal is attenuated by -¥ during 1024 LRCK cycles (1024/fs). (2) Analog output corresponding to digital input have the group delay (GD). (3) If the soft mute is cancelled within 1024 LRCK cycles, the attenuation is discontinued and returned to 0dB. “H”. DZF pin immediately goes to “L” if input data are not zero after going DZF “H”. Figure 5. Soft mute and zero detection mode until MCLK and LRCK are input.
All DACs are placed in the power-down mode by bringing PDN pin “L” and each digital filter is also reset at the same time. application. Figure 6 shows the power-down/up sequence. the click noise influences system application. outputs go to analog common voltage (AVDD/2). (1) The analog output corresponding to digital input has the group delay (GD). (2) Analog outputs are floating (Hi -Z) at the power-down mode. (3) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input. (4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = “L”). (5) Please mute the analog output externally if the click noise (3) influences system application. The timing example is shown in this figure. (6) DZF pins of all channels are “L” in the power-down mode (PDN = “L”). Figure 6. Power-down/up sequence example
VCOM voltage and DZF pins of all channels go to “H”. Figure 7 shows the sequence of reset by RSTN bit. (1) The analog output corresponding to digital input has the group delay (GD). (2) Analog outputs go to VCOM voltage. (4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN = “L”). (5) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 4~5/fs after RSTN bit becomes “1”. (6) There is a delay, 2~3/fs from RSTN bit “1” to the internal RSTN “1”. Figure 7. Reset sequence example
8bits). Address and data is clocked in on the rising edge of CCLK. Data is latched after a low-to-high transition of CSN. The clock speed of CCLK is 5MHz(max). The CSN pin should be held to “H” except for access. Figure 7. Control I/F Timing Table 6. Function Table (O: Supported, X: Not supported) Note: Writing to control register is inhibited when PDN = “L” or the MCLK is not fed.
ASAHI KASEI [AK4356] M0072-E-01 1999/09 - 21 - n Mapping of Program Registers Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Control 1 0 SLOW DZFM DZFE DIF2 DIF1 DIF0 RSTN 01H Control 2 0 0 0 CKS2 CKS1 CKS0 SMUTE RSTN 02H Speed & Power Down Control 0 0 DFS1 DFS0 PW3 PW2 PW1 RSTN 03H De-emphasis Control 0 0 DEMC1 DEMC0 DEMB1 DEMB0 DEMA1 DEMA0 04H LOUT1 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 05H ROUT1 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 06H LOUT2 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 07H ROUT2 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 08H LOUT3 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 09H ROUT3 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 0AH Test Mode 0 0 0 TEST4 TEST3 TEST2 TEST1 TEST0 Note: For addresses from 0BH to 1FH, data is not written. When PDN goes to “L”, the registers are initialized to their default values. When RSTN bit goes to “0”, the internal timing is reset, DZF pins of all channels go to “H” but registers are not initialized to their default values. DZFE, DIF2-0, CKS2-0, SMUTE and DFS0 are ORed with pins.
ASAHI KASEI [AK4356] M0072-E-01 1999/09 - 22 - n Register Definitions Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Control 1 0 SLOW DZFM DZFE DIF2 DIF1 DIF0 RSTN D e f a u l t 0 0000001 RSTN: Internal timing reset 0: Reset. DZF pins of all channels go to “H” and registers are not initialized. 1: Normal operation When the states of SLOW, DIF2-0, CKS2-0 or DFS0-1 changes, the AK4356 should be reset by PDN pin or RSTN bit. Some click noise occurs at that timing. DIF2-0: Audio data interface modes (See Table 3.) Initial: “000”, Mode 0 Register bits of DIF2-0 are ORed with the DFS2-0 pins. DZFE: Data Zero Detect Enable 0: Disable 1: Enable Zero detect function can be disabled by DZFE bit. In this case, the DZF pins of all channels are always “L”. Register bit of DZFE is ORed with the DZFE pin. DZFM: Data Zero Detect Mode 0: Channel Separated Mode 1: Channel ANDed Mode If the DZFM bit is set to “1”, the DZF pins of all channels go to “H” only when the input data at all channels are continuously zeros for 8192 LRCK cycles. SLOW: Slow roll-off response enable 0: Disable 1: Enable Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 01H Control 2 0 0 0 CKS2 CKS1 CKS0 SMUTE RSTN D e f a u l t 0 0000001 RSTN: Internal timing reset 0: Reset. DZF pins of all channels go to “H” and registers are not initialized. 1: Normal operation When the states of SLOW, DIF2-0, CKS2-0 or DFS0-1 changes, the AK4356 should be reset by PDN pin or RSTN bit. Some click noise occurs at that timing. SMUTE: Soft Mute Enable 0: Normal operation 1: All DAC outputs soft-muted Register bit of SMUTE is ORed with the SMUTE pin. CKS2-0: Master Clock Frequency Select (See Table 2.) Initial: “000”, Mode 0 Register bits of CKS2-0 are ORed with the CKS2-0 pins.
ASAHI KASEI [AK4356] M0072-E-01 1999/09 - 23 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 02H Speed & Power Down Control 0 0 DFS1 DFS0 PW3 PW2 PW1 RSTN D e f a u l t 0 0001111 RSTN: Internal timing reset 0: Reset. DZF pins of all channels go to “H” and registers are not initialized. 1: Normal operation When the states of SLOW, DIF2-0, CKS2-0 or DFS0-1 changes, the AK4356 should be reset by PDN pin or RSTN bit. Some click noise occurs at that timing. PW3-1: Power-down control (0: Power-down, 1: Power-up) PW1: Power down control of DAC1 PW2: Power down control of DAC2 PW3: Power down control of DAC3 All sections are powered-down by PW1=PW2=PW3=0. DFS1-0: Sampling speed control (See Table 1.) 00: Normal speed 01: Double speed 10: 4 times speed (DAC2 and DAC3 are automatically powered down.) Register bit of DFS0 is ORed with the DFS0 pin. When sampling speed mode is changed between normal and double/4 times speed mode, DFS1-0 bit should be changed after changing MCLK frequency (figure below). Some click noise occurs at this timing. Sampling speed MCLK normal 4 times /double normal When sampling speed mode is changed between double and 4 times speed mode, sampling mode should be changed to normal speed mode after changing MCLK frequency, and then it should be changed to double/4 times speed mode (figure below). Some click noise occurs at those changing timing. Sampling speed MCLK double/ 4 times normal 4 times /double Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 03H De-emphasis Control 0 0 DEMC1 DEMC0 DEMB1 DEMB0 DEMA1 DEMA0 D e f a u l t 0 0010101 DEMA1-0: De-emphasis response control for DAC1 data on SDTI1 (See Table 4,5.) Initial: “01”, OFF DEMB1-0: De-emphasis response control for DAC2 data on SDTI2 (See Table 4,5.) Initial: “01”, OFF DEMC1-0: De-emphasis response control for DAC3 data on SDTI3 (See Table 4,5.) Initial: “01”, OFF
ASAHI KASEI [AK4356] M0072-E-01 1999/09 - 24 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 04H LOUT1 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 05H ROUT1 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 06H LOUT2 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 07H ROUT2 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 08H LOUT3 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 09H ROUT3 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 D e f a u l t 1 1111111 ATT7-0: Attenuation Level 256 levels, 0.5dB step ATT7-0 Attenuation FFH 0dB FEH -0.5dB FDH -1.0dB : : : : 02H -126.5dB 01H -127.0dB 00H MUTE (- ¥) The transition between set values is soft transition of 7425 levels. It takes 7424/fs (168ms@fs=44.1kHz) from FFH(0dB) to 00H(MUTE). If PDN pin goes to “L”, the ATTs are initialized to FFH. The ATTs are FFH when RSTN = “0”. When RSTN return to “1”, the ATTs fade to their current value. Digital attenuator is independent of soft mute function. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0AH Test Mode 0 0 0 TEST4 TEST3 TEST2 TEST1 TEST0 D e f a u l t 0 0000000 TEST4-0: Test mode
Figure 9. Ground Layout Note: AVSS and DVSS must be connected to the same analog ground plane.
- Grounding and Power Supply Decoupling
digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be near to the AK4356 as possible, with the small value ceramic capacitors being the nearest. signals, especially clocks, should be kept away from the VREFH pin in order to avoid unwanted coupling into the AK4356. modulator beyond the audio passband. the example of external op-amp circuit summing the differential outputs.
ASAHI KASEI [AK4356] M0072-E-01 1999/09 - 28 - PACKAGE 0.15 0.17–0.050.37–0.10 10.00 1.70max 11 1 2333 44pin LQFP (Unit: mm) 10.00 12.80–0.30 0.80 12.80–0.30 0~0.2 0°~10° 0.60–0.20 n Package & Lead frame material Package molding compound: Epoxy Lead frame material: Cu Lead frame surface treatment: Solder plate
ASAHI KASEI [AK4356] M0072-E-01 1999/09 - 29 - MARKING AKM AK4356VQ XXXXXXX JAPAN 1) Pin #1 indication 2) Date Code: XXXXXXX(7 digits) 3) Marking Code: AK4356VQ 4) Country of Origin 5) Asahi Kasei Logo IMPORTANT NOTICE
- These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status.
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