ICEBLINK40-LP1K LATTICE | Alldatasheet
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Technical content
iCEblink40-LP1K Evaluation Kit User’s Guide
iCEblink40-LP1K Evaluation Kit User’s Guide Introduction Thank you for choosing the Lattice Semiconductor iCEblink40™-LP1K Evaluation Kit. This guide describes how to begin using the iCEblink40-LP 1K Evaluation Kit, an easy-to-use platform for rapidly prototyping designs using the iCE40™ FPGA.
Features
Ultra low-power iCE40LP1K FPGA USB programming, debugging, virtual I/O functions, and power supply Four user LEDs Four capacitive-touch buttons 3.3 MHz clock source 1Mbit SPI serial configuration PROM Supported by Lattice iCEcube2™ design software 63 LVCMOS/LVTTL (3.3V) digital I/O connections on 0.1” through-hole connections Supports third-party I/O expansion boards and modules, including 3.3V Arduino Shield boards (requires addi- tional sockets, not supplied) Figure 1. iCEblink40 LP1K Evaluation Board and Major Hardware Features Before using the iCEblink40 board, please be sure to do wnload and install iCEcube2 Release 2011.12 or later. software is only available for the Windows operating system. During the installation process, be sure to install the Adept USB Programming Software, as shown in Figure 2.
power-good LED (LD5) adjacent to the USB connector illuminates. See Figure 4 to locate the power-good LED. cates if the USB power supply, the 3.3V supply, and the 1.2V supply are within the specified ranges. p when the FPGA is correctly loaded with a valid bitstream. Figure 4. iCEblink40 Status LEDs Table 1. iCEblink40 Status LED Descriptions ered hub, or a USB-based wall plug. The board is powered but the FPGA is not yet configured. FPGA configuration bitstream. wer supply or with the on-board regulator.
- Control the LEDs from the four capacitive touch buttons on the board itself.
- Control the LEDs and other internal logic using the USB-based I/O expansion interface.
the capacitive touch buttons stops the LE Ds from scrolling and places the board in a different operating mode. Figure 5. Preprogrammed Demonstration Design
- Press a button to toggle the
- Press any button to enter
If no button was pressed during the last five seconds , the board returns to scrolling the LEDs. www.latticesemi.com/iceblink40-LP1K. drives a byte-wide parallel port expander implemented within the FPGA, controlled by software running on the PC. LEDs, light bars, and 32-bit input and outputs.
- Click Start I/O. Remember, the associated I/O Expander design must be part of the compiled FPGA design
before the Virtual I/Os work.
- If the virtual I/O expansion design is functioning correctl y, the green virtual status LED will turn from red to
Figure 8. Starting the Digilent Adept Virtual I/O Expansion Application To disconnect the virtual I/O interface, simply click the Stop I/O button in the graphical interface. with the virtual I/Os active, change the position of virtual switch [7] (the bottom left switch in the graphical interface). e how the physical LEDs on the board change direction. pushbutton is pressed in the graphical interface.
via simple modifications of the board using the 1x3 connections on JP2, as listed in Table 2. Table 2. Selecting Other Oscillator Frequencies Using Jumper JP2
3.33 MHz (default)
33.3 MHz
board, as shown in Figure 1. Table 3. User LED Operation completely turn off an LED, drive it Low. header located in the lower left corner.
Figure 14. Capacitive Touch Timing Examples The switching time difference between an unpressed and one or more pressed buttons is roughly 300 to 500 ns. tive-touch buttons. Pressing all four buttons is the same as pressing no buttons.
Figure 15. iCEblink40 Demo Application Capacitive Touch Button Flowchart
Table 6. Digital I/O Headers and Their Functions J6 1x6 0.1” centers Left edge, bottom 3.3V digital I/O. Compatible with Digilent 1x6 PMod modules. set Left edge, top Production programming of USB controller. OM. Compatible with Digilent 1x6 PMod modules. th Digilent 1x6 Pmod modules. ppropriate female socket listed, or an equivalent. Straight-through or right-angle through-hole sockets are listed. Male headers are also possible solutions when using the interface cable provided with most Pmod modules. Table 7. Pmod Module Headers J6, J12 1x6 header on 0.1” centers. A six-pin Pmod header. ports two six-pin Pmod modules. ight end of the holes as marked. odules also include interface cables to allow easy connection to other header types.
iCEblink40-LP1K Evaluation Kit User’s Guide If all is working correctly, the power-on LED and the configuration done LED will bo th go out momentarily as iCEcube2 programs the on-board SPI Flash PROM. After pr ogramming is complete, both LEDs should light up again and the FPGA will execute the new configuration image. From Command Line The iCEblink40 programming software can also be executed from a console window or DOS box. To open a con - sole window or DOS box, click the Start button and type cmd in the textbox immediately above the Start button. Executable Location After installation, the programmin g software executable is called iceutil.exe and is located in the \\Sbt- Tools\\sbt_backend\\bin\\win32\\opt directory. The iecutil.exe executable can be copied into the same directory as the FPGA bitstream image or can be pointed to on the command line. FPGA Bitstream Configuration File The required bitstream image is part of the iCEcube2 project. Multiple versions of the bitstream are stored in the <projname>_Implmnt\\sbt\\outputs\\bitmap directory. The raw hexadecimal version of the bitstream is called <projname>_bitmap.hex. The alternate format of the same information is an Intel hexadecimal file called <proj- name>_bitmap_int.hex. Raw Hexadecimal Command Example <path>/iceutil -d iCE40 -res -cr -m M25P10A -fh -w <path/projname>_bitmap.hex Intel Hexadecimal Command Example <path>/iceutil -d iCE40 -res -cr -m M25P10A -fi -w <path/projname>_bitmap_int.hex Help <path>/iceutil -help Testing Core Power Jumper JP1 provides the ability to measure core power consumption by the FPGA. Two power measurement meth- ods are supported. Easy Method Using a Multimeter Connect the iCEblink40 board through your high-accuracy multimeter. Use a meter with a minimum of 10,000 counts; 50,000 counts or more is recommended for better accuracy. To take a quick measurement, follow these steps. 1. Disconnect power to the iCEblink40 board by removing the USB cable connection, either at the board or at the computer. 2. Remove the jumper JP1, which isolates the FPGA’s core supply from the 1.2V supply on the board. 3. Connect your multimeter’s alligator or test clips to the stake pins on header JP1. 4. Configure the multimeter to measure current using its highest mA or Amp range. This setting typically has the lowest voltage drop internally within the meter. 5. Re-connect the USB cable that supplies power to the iCEblink40 board and configure the FPGA device if nec - essary. 6. Observe the power reading on the multimeter. At low clock rates, which results in lower power consumption, switch the meter to a lower amperage setting for better accuracy. However, this also may increase the resis- tance across the meter leads. Using too low of a meter setting causes a large voltage drop within the meter, potentially violating the minimum input voltage specification to the FPGA device.
Figure 24. Schematic
33.33 MHz
Mechanically compatible with Basic I/O shield. Optional SPI PMOD support requested by SiliconBlue field sales.
Table 9. Bill of Materials