AD9833BRMZ

AD9833BRMZ SYC | Alldatasheet

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Technical content

Low Power, 12.65 mW, 2.3 V to 5.5 V, Programmable Waveform Generator Data Sheet AD9833

FEATURES

Digitally programmable frequency and phase 12.65 mW power consumption at 3 V 0 MHz to 12.5 MHz output frequency range 28-bit resolution: 0.1 Hz at 25 MHz reference clock Sinusoidal, triangular, and square wave outputs 2.3 V to 5.5 V power supply No external components required 3-wire SPI interface Extended temperature range: −40°C to +105°C Power-down option 10-lead MSOP package Qualified for automotive applications

APPLICATIONS

Frequency stimulus/waveform generation Liquid and gas flow measurement Sensory applications: proximity, motion, and defect detection Line loss/attenuation Test and medical equipment Sweep/clock generators Time domain reflectometry (TDR) applications GENERAL DESCRIPTION The AD9833 is a low power, programmable waveform generator capable of producing sine, triangular, and square wave outputs. Waveform generation is required in various types of sensing, actuation, and time domain reflectometry (TDR) applications. The output frequency and phase are software programmable, allowing easy tuning. No external components are needed. The frequency registers are 28 bits wide: with a 25 MHz clock rate, resolution of 0.1 Hz can be achieved; with a 1 MHz clock rate, the AD9833 can be tuned to 0.004 Hz resolution. The AD9833 is written to via a 3-wire serial interface. This serial interface operates at clock rates up to 40 MHz and is compatible with DSP and microcontroller standards. The device operates with a power supply from 2.3 V to 5.5 V . The AD9833 has a power-down function (SLEEP). This function allows sections of the device that are not being used to be powered down, thus minimizing the current consumption of the part. For example, the DAC can be powered down when a clock output is being generated. The AD9833 is available in a 10-lead MSOP package. FUNCTIONAL BLOCK DIAGRAM SERIAL INTERFACE AND CONTROL LOGIC SCLK SDATAFSYNC CONTROL REGISTER PHASE1 REG PHASE0 REG MUX SIN ROM 10-BIT DACMUX FREQ0 REG FREQ1 REG ON-BOARD REFERENCE AGND DGND VDD AD9833 PHASE ACCUMULATOR (28-BIT) REGULATOR CAP/2.5V 2.5V AVDD/ DVDD MUXDIVIDE BY 2 MSB MUX FULL-SCALE CONTROL COMP VOUT R 200Ω MCLK 02704-001 Figure 1. AD9833BRMZ GENERADOR DE ONDAS PROGRAMABLE www.sycelectronica.com.ar

Rev. E | Page 2 of 24 TABLE OF CONTENTS Numerically Controlled Oscillator Plus Phase Modulator ... 12

REVISION HISTORY

9/12—Rev. D to Rev. E 4/11—Rev. C to Rev. D Deleted AD9833 to ADSP-2101/ADSP-2103 Interface Added System Demonstration Platform Section, AD9833 Changes to Crystal Oscillator vs. External Clock Section Added Figure 32 and Figure 33; Renumbered Figures Added Evaluation Board Schematics Section, Figure 34, Added Evaluation Board Layout Section, Figure 36, 9/10—Rev. B to Rev. C Changed 20 mW to 12.65 mW in Data Sheet Title 6/10—Rev. A to Rev. B 6/03—Rev. 0 to Rev. A www.sycelectronica.com.ar

VDD = 2.3 V to 5.5 V , AGND = DGND = 0 V , TA = TMIN to TMAX, RSET = 6.8 kΩ for VOUT, unless otherwise noted. 1 Operating temperature range is −40°C to +105°C; typical specifications are at 25°C. Figure 2. Test Circuit Used to Test Specifications

Rev. E | Page 5 of 24 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Rating VDD to AGND −0.3 V to +6 V VDD to DGND −0.3 V to +6 V AGND to DGND −0.3 V to +0.3 V CAP/2.5V 2.75 V Digital I/O Voltage to DGND −0.3 V to VDD + 0.3 V Analog I/O Voltage to AGND −0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (B Version) −40°C to +105°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C θJA Thermal Impedance 206°C/W θJC Thermal Impedance 44°C/W Lead Temperature, Soldering (10 sec) 300°C IR Reflow, Peak Temperature 220°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION www.sycelectronica.com.ar

Figure 5. Pin Configuration Table 4. Pin Function Descriptions 1 COMP DAC Bias Pin. This pin is used for decoupling the DAC bias voltage. output frequency accuracy and phase noise are determined by this clock. 6 SDATA Serial Data Input. The 16-bit serial data-word is applied to this input. 7 SCLK Serial Clock Input. Data is clocked into the AD9833 on each falling edge of SCLK. the internal logic is informed that a new word is being loaded into the device. is not required because the device has a 200 Ω resistor on board.

Rev. E | Page 10 of 24 TERMINOLOGY Integral Nonlinearity (INL) INL is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The end- points of the transfer function are zero scale, a point 0.5 LSB below the first code transition (000 … 00 to 000 … 01), and full scale, a point 0.5 LSB above the last code transition (111 … 10 to 111 … 11). The error is expressed in LSBs. Differential Nonlinearity (DNL) DNL is the difference between the measured and ideal 1 LSB change between two adjacent codes in the DAC. A specified DNL of ±1 LSB maximum ensures monotonicity. Output Compliance Output compliance refers to the maximum voltage that can be generated at the output of the DAC to meet the specifications. When voltages greater than that specified for the output compli- ance are generated, the AD9833 may not meet the specifications listed in the data sheet. Spurious-Free Dynamic Range (SFDR) Along with the frequency of interest, harmonics of the funda- mental frequency and images of these frequencies are present at the output of a DDS device. SFDR refers to the largest spur or harmonic present in the band of interest. The wideband SFDR gives the magnitude of the largest spur or harmonic relative to the magnitude of the fundamental frequency in the zero to Nyquist bandwidth. The narrow-band SFDR gives the attenuation of the largest spur or harmonic in a bandwidth of ±200 kHz about the fundamental frequency. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the rms value of the fundamental. For the AD9833, THD is defined as 2log20THD V VVVVV ++++= where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through sixth harmonics. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency. The value for SNR is expressed in decibels. Clock Feedthrough There is feedthrough from the MCLK input to the analog output. Clock feedthrough refers to the magnitude of the MCLK signal relative to the fundamental frequency in the output spectrum of the AD9833. www.sycelectronica.com.ar

by the traditional rate of ω = 2πf. Figure 23. Sine Wave modulator, SIN ROM, and digital-to-analog converter (DAC). Each subcircuit is described in the Circuit Description section.

Rev. E | Page 12 of 24 CIRCUIT DESCRIPTION The AD9833 is a fully integrated direct digital synthesis (DDS) chip. The chip requires one reference clock, one low precision resistor, and decoupling capacitors to provide digitally created sine waves up to 12.5 MHz. In addition to the generation of this RF signal, the chip is fully capable of a broad range of simple and complex modulation schemes. These modulation schemes are fully implemented in the digital domain, allowing accurate and simple realization of complex modulation algorithms using DSP techniques. The internal circuitry of the AD9833 consists of the following main sections: a numerically controlled oscillator (NCO), frequency and phase modulators, SIN ROM, a DAC, and a regulator. NUMERICALLY CONTROLLED OSCILLATOR PLUS PHASE MODULATOR This consists of two frequency select registers, a phase accumulator, two phase offset registers, and a phase offset adder. The main component of the NCO is a 28-bit phase accumulator. Continuous time signals have a phase range of 0 to 2π. Outside this range of numbers, the sinusoid functions repeat themselves in a periodic manner. The digital implementation is no different. The accumulator simply scales the range of phase numbers into a multibit digital word. The phase accumulator in the AD9833 is implemented with 28 bits. Therefore, in the AD9833, 2π = 2 28. Likewise, the ΔPhase term is scaled into this range of numbers: 0 < ΔPhase < 228 − 1 With these substitutions, the previous equation becomes f = ΔPhase × fMCLK∕228 where 0 < ΔPhase < 228 − 1. The input to the phase accumulator can be selected from either the FREQ0 register or the FREQ1 register and is controlled by the FSELECT bit. NCOs inherently generate continuous phase signals, thus avoiding any output discontinuity when switching between frequencies. Following the NCO, a phase offset can be added to perform phase modulation using the 12-bit phase registers. The contents of one of these phase registers are added to the most significant bits of the NCO. The AD9833 has two phase registers; their resolution is 2π/4096. SIN ROM To make the output from the NCO useful, it must be converted from phase information into a sinusoidal value. Because phase information maps directly into amplitude, the SIN ROM uses the digital phase information as an address to a lookup table and converts the phase information into amplitude. Although the NCO contains a 28-bit phase accumulator, the output of the NCO is truncated to 12 bits. Using the full resolution of the phase accumulator is impractical and unnecessary, because this would require a lookup table of 2 28 entries. It is necessary only to have sufficient phase resolution such that the errors due to truncation are smaller than the resolution of the 10-bit DAC. This requires that the SIN ROM have two bits of phase resolution more than the 10-bit DAC. The SIN ROM is enabled using the mode bit (D1) in the control register (see Table 15). DIGITAL-TO-ANALOG CONVERTER (DAC) The AD9833 includes a high impedance, current source 10-bit DAC. The DAC receives the digital words from the SIN ROM and converts them into the corresponding analog voltages. The DAC is configured for single-ended operation. An external load resistor is not required because the device has a 200 Ω resistor on board. The DAC generates an output voltage of typically 0.6 V p-p. REGULATOR VDD provides the power supply required for the analog section and the digital section of the AD9833. This supply can have a value of 2.3 V to 5.5 V . The internal digital section of the AD9833 is operated at 2.5 V . An on-board regulator steps down the voltage applied at VDD to 2.5 V . When the applied voltage at the VDD pin of the AD9833 is less than or equal to 2.7 V , the CAP/2.5V and VDD pins should be tied together, thus bypassing the on-board regulator. www.sycelectronica.com.ar

this operation is given in .

1. After FSYNC goes low, serial

edge of the last word loaded. Application Note on the Analog Devices, Inc., website. an analog output of midscale. after the reset bit is set to 0. Table 6 describes the individual bits of the control register. will be altered, D15 and D14 must be set to 0, as shown in Table 5. Table 5. Control Register Bits Figure 24. Function of Control Bits

Table 6. Description of Bits in the Control Register frequency register to which the word is loaded and should, therefore, be the same for both of the consecutive writes. Table 9. When B28 = 0, the 28-bit frequency register operates as two 14-bit registers, one containing the 14 MSBs and address. The control bit D12 (HLB) informs the AD9833 whether the bits to be altered are the 14 MSBs or 14 LSBs. frequency register. HLB = 0 allows a write to the 14 LSBs of the addressed frequency register. D11 FSELECT The FSELECT bit defines whether the FREQ0 register or the FREQ1 register is used in the phase accumulator. D9 Reserved This bit should be set to 0. D8 Reset Reset = 1 resets internal registers to 0, which corresponds to an analog output of midscale. Reset = 0 disables reset. This function is explained further in Table 13. NCO is no longer accumulating. When SLEEP1 = 0, MCLK is enabled. This function is explained further in Table 14. D6 SLEEP12 SLEEP12 = 1 powers down the on-chip DAC. This is useful when the AD9833 is used to output the MSB of the DAC data. SLEEP12 = 0 implies that the DAC is active. This function is explained further in Table 14. determines whether it is a sinusoidal or a ramp output that is available. D4 Reserved This bit must be set to 0. data is passed directly to the VOUT pin. When DIV2 = 0, the MSB/2 of the DAC data is output at the VOUT pin. D2 Reserved This bit must be set to 0. D0 Reserved This bit must be set to 0.

registers, which are described in Table 7. Table 7. Frequency and Phase Registers avoid unwanted output anomalies. frequency and phase registers of the AD9833. the address of the frequency register. Table 8. Frequency Register Bits Table 9. Writing 0xFFFC000 to the FREQ0 Register are altered, while with fine tuning, only the 14 LSBs are altered. Table 10. Writing 0x3FFF to the 14 LSBs of the FREQ1 Register

14 LSBs = 0x3FFF

Table 11. Writing 0x00FF to the 14 MSBs of the FREQ0 Register

14 MSBs = 0x00FF

When writing to a phase register, Bit D15 and Bit D14 are set to 11. Bit D13 identifies which phase register is being loaded. Table 12. Phase Register Bits

Table 13. Applying the Reset Function

0 No reset applied

1 Internal registers reset

sleep function are outlined in Table 14. Table 14. Applying the Sleep Function can be written to the part when the SLEEP1 control bit is active. active will be seen at the output after a latency period. MSB of the DAC data, a sinusoidal output, or a triangle output. are used to decide which output is available from the AD9833. frequency of this output from the VOUT pin. VOUT pin, set the mode (D1) bit = 1. Table 15. Outputs from the VOUT Pin Figure 25. Triangle Output

Rev. E | Page 17 of 24 APPLICATIONS INFORMATION Because of the various output options available from the part, the AD9833 can be configured to suit a wide variety of applications. One of the areas where the AD9833 is suitable is in modulation applications. The part can be used to perform simple modulation, such as FSK. More complex modulation schemes, such as GMSK and QPSK, can also be implemented using the AD9833. In an FSK application, the two frequency registers of the AD9833 are loaded with different values. One frequency represents the space frequency, while the other represents the mark frequency. Using the FSELECT bit in the control register of the AD9833, the user can modulate the carrier frequency between the two values. The AD9833 has two phase registers, which enables the part to perform PSK. With phase-shift keying, the carrier frequency is phase shifted, the phase being altered by an amount that is related to the bit stream being input to the modulator. The AD9833 is also suitable for signal generator applications. Because the MSB of the DAC data is available at the VOUT pin, the device can be used to generate a square wave. With its low current consumption, the part is suitable for applications in which it can be used as a local oscillator. GROUNDING AND LAYOUT The printed circuit board (PCB) that houses the AD9833 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be separated easily. A minimum etch technique is generally best for ground planes because it gives the best shielding. Digital and analog ground planes should be joined in one place only. If the AD9833 is the only device requiring an AGND-to-DGND connection, then the ground planes should be connected at the AGND and DGND pins of the AD9833. If the AD9833 is in a system where multiple devices require AGND- to-DGND connections, the connection should be made at one point only, a star ground point that should be established as close as possible to the AD9833. Avoid running digital lines under the device as these couple noise onto the die. The analog ground plane should be allowed to run under the AD9833 to avoid noise coupling. The power supply lines to the AD9833 should use as large a track as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but it is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, and signals are placed on the other side. Good decoupling is important. The AD9833 should have supply bypassing of 0.1 μF ceramic capacitors in parallel with 10 μF tantalum capacitors. To achieve the best performance from the decoupling capacitors, they should be placed as close as possible to the device, ideally right up against the device. www.sycelectronica.com.ar

Figure 28. Flowchart for Data Writes

0.50 BSC

1.10 MAX

Figure 39. 10-Lead Mini Small Outline Package [MSOP] 2 W = Qualified for Automotive Applications. 3 The evaluation board for the AD9833 requires the system demonstration platform (SDP) board, which is sold separately. to obtain the specific Automotive Reliability reports for these models. registered trademarks are the prop erty of their respective owners.