80VA

80VA LATTICE | Alldatasheet

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Technical content

3.3V Generic Digital Crosspoint TM Functional Block DiagramFeatures

• IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL CROSSPOINT FAMILY — Advanced Architecture Addresses Programmable PCB Interconnect, Bus Interface Integration and Jumper/Switch Replacement — “Any Input to Any Output” Routing — Fixed HIGH or LOW Output Option for Jumper/DIP Switch Emulation — Space-Saving PQFP and BGA Packaging — Dedicated IEEE 1149.1-Compliant Boundary Scan Test
• HIGH PERFORMANCE E 2CMOS ® TECHNOLOGY — 3.3V Core Power Supply — 3.5ns Input-to-Output/3.5ns Clock-to-Output Delay — 250MHz Maximum Clock Frequency — TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels (Individually Programmable) — Low-Power: 16.5mA Quiescent Icc — 24mA I OL Drive with Programmable Slew Rate Control Option — PCI Compatible Drive Capability — Schmitt Trigger Inputs for Noise Immunity — Electrically Erasable and Reprogrammable — Non-Volatile E 2CMOS Technology
• ispGDXV™ OFFERS THE FOLLOWING ADVANTAGES — 3.3V In-System Programmable Using Boundary Scan Test Access Port (TAP) — Change Interconnects in Seconds
• FLEXIBLE ARCHITECTURE — Combinatorial/Latched/Registered Inputs or Outputs — Individual I/O Tri-state Control with Polarity Control — Dedicated Clock/Clock Enable Input Pins (two) or Programmable Clocks/Clock Enables from I/O Pins (20) — Single Level 4:1 Dynamic Path Selection (Tpd = 3.5ns) — Programmable Wide-MUX Cascade Feature Supports up to 16:1 MUX — Programmable Pull-ups, Bus Hold Latch and Open Drain on I/O Pins — Outputs Tri-state During Power-up (“Live Insertion” Friendly)
• DESIGN SUPPORT THROUGH LATTICE’S ispGDX DEVELOPMENT SOFTWARE — MS Windows or NT / PC-Based or Sun O/S — Easy Text-Based Design Entry — Automatic Signal Routing — Program up to 100 ISP Devices Concurrently — Simulator Netlist Generation for Easy Board-Level Simulation Global Routing Pool (GRP) I/O Cells I/O Pins B Boundary Scan Control I/O Cells ISP Control I/O Pins A I/O Pins C I/O Pins D

Description

The ispGDXVA architecture provides a family of fast, flexible programmable devices to address a variety of system-level digital signal routing and interface require- ments including:

• Multi-Port Multiprocessor Interfaces
• Wide Data and Address Bus Multiplexing (e.g. 16:1 High-Speed Bus MUX)
• Programmable Control Signal Routing (e.g. Interrupts, DMAREQs, etc.)
• Board-Level PCB Signal Routing for Prototyping or Programmable Bus Interfaces The devices feature fast operation, with input-to-output signal delays (Tpd) of 3.5ns and clock-to-output delays of 3.5ns. The architecture of the devices consists of a series of programmable I/O cells interconnected by a Global Rout- ing Pool (GRP). All I/O pin inputs enter the GRP directly or are registered or latched so they can be routed to the required I/O outputs. I/O pin inputs are defined as four sets (A,B,C,D) which have access to the four MUX inputs gdx80va_02 Copyright © 2000 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8037; http://www.latticesemi.com

can be driven directly from selected sets of I/O pins. conditions for the Vcc and I/O pins must still be met. Table 1. ispGDXVA Family Members CLKEN3 respectively in all devices.

test is supported by dedicated registers at each I/O pin. standard Boundary Scan protocol. together with one group per side. and MUX1 can be driven from either MUXsel1 or MUXsel2. Figure 1. ispGDXVA I/O Cell and GRP Detail (80 I/O Device)

40 I/O Cells

80 Input GRP

80 I/O Inputs

programmed as active high or active low.

00 M 0

01 M 1

11 M 2

10 M 3

cells as well as their relationship to direct MUX inputs. extrapolated from the pattern shown in the table. Figure 2. I/O Hemisphere Configuration of

Table 2. Adjacent I/O Cells (Mapping of Figure 3. Adjacent I/O Cells vs. Direct Input Path for need for an off-chip Open-Drain or Open-Collector buffer. resistor value for the pull-up ranges from 50kΩ to 80kΩ . the 2.5V reference voltage when used.

The ispGDXVA Family architecture has been developed to deliver an in-system programmable signal routing solution with high speed and high flexibility. The devices are targeted for three similar but distinct classes of end- system applications: Programmable, Random Signal Interconnect (PRSI) This class includes PCB-level programmable signal rout- ing and may be used to provide arbitrary signal swapping between chips. It opens up the possibilities of program- mable system hardware. It is characterized by the need to provide a large number of 1:1 pin connections which are statically configured, i.e., the pin-to-pin paths do not need to change dynamically in response to control in- puts. Programmable Data Path (PDP) This application area includes system data path trans- ceiver, MUX and latch functions. With today’s 32- and 64-bit microprocessor buses, but standard data path glue components still relegated primarily to eight bits, PCBs are frequently crammed with a dozen or more data path glue chips that use valuable real estate. Many of these applications consist of “on-board” bus and memory inter- faces that do not require the very high drive of standard glue functions but can benefit from higher integration. Therefore, there is a need for a flexible means to inte- grate these on-board data path functions in an analogous way to programmable logic’s solution to control logic integration. Lattice’s CPLDs make an ideal control logic complement to the ispGDXVA in-system programmable data path devices as shown below. Data Path Bus #1 Control Inputs (from µP) Address Inputs (from µP) Control Outputs System Clock(s) Data Path Bus #2 Configuration (Switch) Outputs ISP/JTAG Interface ispLSI/ ispMACH Device ispGDXVA Device Buffers / RegistersDecoders Buffers / RegistersState Machines Figure 4. ispGDXVA Complements Lattice CPLDs

Applications

Programmable Switch Replacement (PSR) Includes solid-state replacement and integration of me- chanical DIP Switch and jumper functions. Through in-system programming, pins of the ispGDXVA devices can be driven to HIGH or LOW logic levels to emulate the traditional device outputs. PSR functions do not require any input pin connections. These applications actually require somewhat different silicon features. PRSI functions require that the device support arbitrary signal routing on-chip between any two pins with no routing restrictions. The routing connections are static (determined at programming time) and each input-to-output path operates independently. As a result, there is little need for dynamic signal controls (OE, clocks, etc.). Because the ispGDXVA device will inter- face with control logic outputs from other components (such as ispLSI or ispMACH) on the board (which fre- quently change late in the design process as control logic is finalized), there must be no restrictions on pin-to-pin signal routing for this type of application. PDP functions, on the other hand, require the ability to dynamically switch signal routing (MUXing) as well as latch and tri-state output signals. As a result, the pro- grammable interconnect is used to define possible signal routes that are then selected dynamically by control signals from an external MPU or control logic. These functions are usually formulated early in the conceptual design of a product. The data path requirements are driven by the microprocessor, bus and memory architec- ture defined for the system. This part of the design is the earliest portion of the system design frozen, and will not usually change late in the design because the result would be total system and PCB redesign. As a result, the ability to accommodate arbitrary any pin-to-any pin re- routing is not a strong requirement as long as the designer has the ability to define his functions with a reasonable degree of freedom initially. As a result, the ispGDXVA architecture has been defined to support PSR and PRSI applications (including bidirec- tional paths) with no restrictions, while PDP applications (using dynamic MUXing) are supported with a minimal number of restrictions as described below. In this way, speed and cost can be optimized and the devices can still support the system designer’s needs. The following diagrams illustrate several ispGDXVA ap- plications.

Absolute Maximum Ratings 1,2 Max. Junction Temp. (T J) with Power Applied ... 150°C 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). 2. Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement. DC Recommended Operating Conditions C SYMBOL Table 2-0006/gdxva C PARAMETER PACKAGE TYPE Dedicated Clock Capacitance 8 UNITSTYPICAL TEST CONDITIONS 7TQFP TQFP I/O Capacitance pf pf V = 3.3V, V = 2.0V V = 3.3V, V = 2.0VCC CC Y I/O Capacitance (TA =25oC, f=1.0 MHz) PARAMETER MINIMUM MAXIMUM UNITS Erase/Reprogram Cycles 10,000 — Cycles Erase/Reprogram Specifications SYMBOL Table 2-0005/gdxva VCC VCCIO PARAMETER Supply Voltage I/O Reference Voltage Commercial TA = 0°C to +70°C MIN. MAX. UNITS 3.00 2.3 3.60 3.60 V Industrial TA = -40°C to +85°C 3.00 3.60 V V

3-state levels are measured 0.5V from steady-state active level. Figure 8. Test Load *C L includes Test Fixture and Probe Capacitance.

1. Typical values are at VCC = 3.3V and TA = 25°C. Table 2-0007/gdxva

Over Recommended Operating Conditions VIH SYMBOL 2.5V/gdxva VOH PARAMETER Input High Voltage Output High Voltage VOH(MIN) ≤ VOUT or VOUT ≤ VOL(MAX) VOH(MIN) ≤ VOUT or VOUT ≤ VOL(MAX) VCCIO=MIN , IOH = -8mA VCCIO=MIN , IOL = 8mA CONDITION MIN. TYP. MAX. UNITS 1.7 1.8 5.25 V VCCIO VIL I/O Reference Voltage Input Low Voltage 2.3 -0.3 2.7 0.7 V V V VCCIO=MIN , IOH = -100µA 2.1 –– V –– 0.6 V VCCIO=MIN , IOL = 100µA –– 0.2 V VOL Output Low Voltage Over Recommended Operating Conditions SYMBOL 1. One output at a time for a maximum of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized, but not 100% tested. 2. Typical values are at V CC = 3.3V and TA = 25°C. 3. ICC / MHz = (0.002 x I/O cell fanout) + 0.022. 4. For a typical application with 50% of I/O pins used as inputs, 50% used as outputs or bi-directionals. 5. This parameter limits the total current sinking of I/O pins surrounding the nearest GND pin. DC Char_gdx80va IPU IBHLS PARAMETER I/O Active Pullup Current Bus Hold Low Sustaining Current IIH IIL Input or I/O High Leakage Current Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX) CONDITION MIN. TYP. 2 MAX. UNITS -10 -200 µA IBHT Bus Hold Trip Points VIL – VIH V µA µA µA 40 –– µA (VCCIO -0.2) ≤ VIN ≤ VCCIO VCCIO ≤ VIN ≤ 5.25V 0V ≤ VIN ≤ VIL (MAX) IOS 1 Output Short Circuit Current –– -250 mAVCC = 3.3V, VOUT = 0.5V, TA = 25°C ICCQ 4 Quiescent Power Supply Current – 12 – mAVIL = 0.5V, VIH = VCC VIN = VIL (MAX) IBHHS Bus Hold High Sustaining Current -40 –– µAVIN = VIH (MIN) IBHLO Bus Hold Low Overdrive Current –– 550 µA0V ≤ VIN ≤ VCCIO ICC Dynamic Power Supply Current per Input Switching One input toggling at 50% duty cycle, outputs open. – See Note 3 – mA/ MHz ICONT 5 Maximum Continuous I/O Pin Sink Current Through Any GND Pin – –– 160 mA IBHHO Bus Hold High Overdrive Current –– -550 µA0V ≤ VIN ≤ VCCIO

5.0 5.0 5.0 8.5 6.0 9.5 6.0 6.0 6.0 6.0 14.0 5.0 0.5 Data Prop. Delay from Any I/O pin to Any I/O Pin (4:1 MUX) Data Prop. Delay from MUXsel Inputs to Any Output (4:1 MUX) Clock Frequency, Max. Toggle Clock Frequency with External Feedback Input Latch or Register Setup Time Before Y x Input Latch or Register Setup Time Before I/O Clock Output Latch or Register Setup Time Before Y x Output Latch or Register Setup Time Before I/O Clock Global Clock Enable Setup Time Before Y x Global Clock Enable Setup Time Before I/O Clock I/O Clock Enable Setup Time Before Y x Input Latch or Reg. Hold Time (Yx) Input Latch or Reg. Hold Time (I/O Clock) Output Latch or Reg. Hold Time (Y Output Latch or Reg. Hold Time (I/O Clock) Global Clock Enable Hold Time (Y Global Clock Enable Hold Time (I/O Clock) I/O Clock Enable Hold Time (Y Output Latch or Reg. Clock (from Yx) to Output Delay Input Latch or Register Clock (from Yx) to Output Delay Output Latch or Register Clock (from I/O pin) to Output Delay Input Latch or Register Clock (from I/O pin) to Output Delay Input to Output Enable Input to Output Disable Test OE Output Enable Test OE Output Disable Clock Pulse Duration, High Clock Pulse Duration, Low Register Reset Delay from RESET Low Reset Pulse Width Output Delay Adder for Output Timings Using Slow Slew Rate Output Skew (tgco1 Across Chip) External Timing Parameters Over Recommended Operating Conditions ns ns MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 143 111 4.0 3.0 4.0 3.0 2.5 1.5 4.5 0.0 1.5 0.0 1.5 0.0 1.5 0.0 3.5 3.5 10.0 A A A A A A B C B C D A tpd2 tsel2 fmax (Tog.) fmax (Ext.) tsu1 tsu2 tsu3 tsu4 tsuce1 tsuce2 tsuce3 th1 th2 th3 th4 thce1 thce2 thce3 tgco12 tgco22 tco12 tco22 ten2 tdis2 ttoeen2 ttoedis2 twh twl trst trw tsl tsk DESCRIPTIONPARAMETER ( )1 tsu3+tgco1 UNITS-5 MIN. MAX. 1. All timings measured with one output switching, fast output slew rate setting, except tsl. 2. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is used as I/O voltage reference. 3.5 3.5 3.5 6.0 4.0 7.0 5.0 5.0 6.0 6.0 8.0 3.5 0.5 250 166.7 3.0 2.5 2.5 2.0 2.5 1.5 3.0 0.0 0.5 0.0 1.0 0.0 1.0 0.0 2.0 2.0 5.0 MIN. MAX. TEST1 COND.

9.0 9.0 9.0 13.5 11.5 15.7 10.5 10.5 10.5 10.5 22.0 9.0 1.0 Data Prop. Delay from Any I/O pin to Any I/O Pin (4:1 MUX) Data Prop. Delay from MUXsel Inputs to Any Output (4:1 MUX) Clock Frequency, Max. Toggle Clock Frequency with External Feedback Input Latch or Register Setup Time Before Y x Input Latch or Register Setup Time Before I/O Clock Output Latch or Register Setup Time Before Y x Output Latch or Register Setup Time Before I/O Clock Global Clock Enable Setup Time Before Y x Global Clock Enable Setup Time Before I/O Clock I/O Clock Enable Setup Time Before Y x Input Latch or Reg. Hold Time (Yx) Input Latch or Reg. Hold Time (I/O Clock) Output Latch or Reg. Hold Time (Y Output Latch or Reg. Hold Time (I/O Clock) Global Clock Enable Hold Time (Y Global Clock Enable Hold Time (I/O Clock) I/O Clock Enable Hold Time (Y Output Latch or Reg. Clock (from Yx) to Output Delay Input Latch or Register Clock (from Yx) to Output Delay Output Latch or Register Clock (from I/O pin) to Output Delay Input Latch or Register Clock (from I/O pin) to Output Delay Input to Output Enable Input to Output Disable Test OE Output Enable Test OE Output Disable Clock Pulse Duration, High Clock Pulse Duration, Low Register Reset Delay from RESET Low Reset Pulse Width Output Delay Adder for Output Timings Using Slow Slew Rate Output Skew (tgco1 Across Chip) External Timing Parameters Over Recommended Operating Conditions ns ns MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 62.5 7.0 6.0 7.0 6.0 4.0 3.0 8.5 0.0 3.0 0.0 3.0 0.0 3.0 0.0 6.0 6.0 18.0 A A A A A A B C B C D A tpd2 tsel2 fmax (Tog.) fmax (Ext.) tsu1 tsu2 tsu3 tsu4 tsuce1 tsuce2 tsuce3 th1 th2 th3 th4 thce1 thce2 thce3 tgco12 tgco22 tco12 tco22 ten2 tdis2 ttoeen2 ttoedis2 twh twl trst trw tsl tsk DESCRIPTIONPARAMETER ( )1 tsu3+tgco1 UNITS-9 MIN. MAX. 1. All timings measured with one output switching, fast output slew rate setting, except tsl. 2. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is used as I/O voltage reference. MIN. MAX. TEST1 COND. 100 5.5 4.5 5.5 4.5 3.5 2.5 6.5 0.0 2.5 0.0 2.5 0.0 2.5 0.0 5.0 5.0 14.0 7.0 7.0 7.0 11.0 9.0 13.0 8.5 8.5 8.5 8.5 18.0 7.0 0.5

External Timing Parameters (Continued) 1.0 0.0 0 4 10 20 30 40 50 60 70 0.2 0.4 0.6 0.8 1.2 1.4 1.6 ∆ GRP Delay (ns) I/O Cell Fanout ispGDX80VA Maximum ∆ GRP Delay vs. I/O Cell Fanout ispGDX80VA timings are specified with a GRP load (fanout) of four I/O cells. The figure below shows the ∆ GRP Delay with increased GRP loads. These deltas apply to any signal path traversing the GRP (MUXA-D, OE, CLK/CLKEN, MUXsel0-1). Global Clock signals which do not use the GRP have no fanout delay adder.

-3 -5 PARAMETER # DESCRIPTION 1 MIN. MAX. MIN. MAX. UNITS Inputs tio 32 Input Buffer Delay — 0.4 — 0.9 ns GRP tgrp 33 GRP Delay — 1.1 — 1.1 ns MUX tmuxd 34 I/O Cell MUX A/B/C/D Data Delay — 1.0 — 1.5 ns tmuxexp 35 I/O Cell MUX A/B/C/D Expander Delay — 1.5 — 2.0 ns tmuxs 36 I/O Cell Data Select — 1.0 — 1.5 ns tmuxsio 37 I/O Cell Data Select (I/O Clock) — 1.5 — 3.0 ns tmuxsg 38 I/O Cell Data Select (Yx Clock) — 1.5 — 2.0 ns tmuxselexp 39 I/O Cell MUX Data Select Expander Delay — 1.5 — 2.0 ns Register tiolat 40 I/O Latch Delay — 1.0 — 1.0 ns tiosu 41 I/O Register Setup Time Before Clock — 0.8 — 2.0 ns tioh 42 I/O Register Hold Time After Clock — 1.7 — 1.5 ns tioco 43 I/O Register Clock to Output Delay — 1.2 — 0.5 ns tior 44 I/O Reset to Output Delay — 1.0 — 1.5 ns tcesu 45 I/O Clock Enable Setup Time Before Clock — 2.3 — 2.0 ns tceh 46 I/O Clock Enable Hold Time After Clock — 0.2 — 0.5 ns Data Path tfdbk 47 I/O Register Feedback Delay — 0.6 — 0.9 ns tiobp 48 I/O Register Bypass Delay — 0.0 — 0.0 ns tioob 49 I/O Register Output Buffer Delay — 0.0 — 0.0 ns tmuxcg 50 I/O Register A/B/C/D Data Input MUX Delay (Yx Clock) — 1.5 — 2.0 ns tmuxcio 51 I/O Register A/B/C/D Data Input MUX Delay (I/O Clock) — 1.5 — 3.0 ns tiodg 52 I/O Register I/O MUX Delay (Yx Clock) — 3.5 — 4.0 ns tiodio 53 I/O Register I/O MUX Delay (I/O Clock) — 3.5 — 5.0 ns Outputs tob 54 Output Buffer Delay — 1.0 — 1.5 ns tobs 55 Output Buffer Delay (Slow Slew Option) — 4.5 — 6.5 ns toeen 56 I/O Cell OE to Output Enable — 3.5 — 4.0 ns toedis 57 I/O Cell OE to Output Disable — 3.5 — 4.0 ns tgoe 58 GRP Output Enable and Disable Delay — 0.0 — 0.0 ns ttoe 59 Test OE Enable and Disable Delay — 2.5 — 2.0 ns Clocks tioclk 60 I/O Clock Delay — 0.3 — 2.0 ns tgclk 61 Global Clock Delay — 1.3 — 2.0 ns tgclkeng 62 Global Clock Enable (Yx Clock) — 1.5 — 2.5 ns tgclkenio 63 Global Clock Enable (I/O Clock) — 1.0 — 3.5 ns tioclkeng 64 I/O Clock Enable (Yx Clock) — 0.5 — 2.5 ns Global Reset tgr 65 Global Reset to I/O Register Latch — 6.0 — 11.0 ns Internal Timing Parameters1 Over Recommended Operating Conditions 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to the Timing Model in this data sheet for further details.

-7 -9 PARAMETER # DESCRIPTION 1 MIN. MAX. MIN. MAX. UNITS Inputs tio 32 Input Buffer Delay — 1.4 — 1.9 ns GRP tgrp 33 GRP Delay — 1.1 — 1.1 ns MUX tmuxd 34 I/O Cell MUX A/B/C/D Data Delay — 2.0 — 2.5 ns tmuxexp 35 I/O Cell MUX A/B/C/D Expander Delay — 2.5 — 3.0 ns tmuxs 36 I/O Cell Data Select — 2.0 — 2.5 ns tmuxsio 37 I/O Cell Data Select (I/O Clock) — 4.5 — 6.0 ns tmuxsg 38 I/O Cell Data Select (Yx Clock) — 2.5 — 3.0 ns tmuxselexp 39 I/O Cell MUX Data Select Expander Delay — 2.5 — 3.0 ns Register tiolat 40 I/O Latch Delay — 1.0 — 1.0 ns tiosu 41 I/O Register Setup Time Before Clock — 3.2 — 4.4 ns tioh 42 I/O Register Hold Time After Clock — 2.3 — 2.6 ns tioco 43 I/O Register Clock to Output Delay — 0.5 — 0.5 ns tior 44 I/O Reset to Output Delay — 1.5 — 1.5 ns tcesu 45 I/O Clock Enable Setup Time Before Clock — 2.5 — 2.0 ns tceh 46 I/O Clock Enable Hold Time After Clock — 1.0 — 2.0 ns Data Path tfdbk 47 I/O Register Feedback Delay — 1.2 — 1.3 ns tiobp 48 I/O Register Bypass Delay — 0.3 — 0.6 ns tioob 49 I/O Register Output Buffer Delay — 0.6 — 0.7 ns tmuxcg 50 I/O Register A/B/C/D Data Input MUX Delay (Yx Clock) — 2.5 — 3.0 ns tmuxcio 51 I/O Register A/B/C/D Data Input MUX Delay (I/O Clock) — 4.5 — 6.0 ns tiodg 52 I/O Register I/O MUX Delay (Yx Clock) — 5.0 — 6.0 ns tiodio 53 I/O Register I/O MUX Delay (I/O Clock) — 7.0 — 9.0 ns Outputs tob 54 Output Buffer Delay — 2.2 — 2.9 ns tobs 55 Output Buffer Delay (Slow Slew Option) — 9.2 — 11.9 ns toeen 56 I/O Cell OE to Output Enable — 6.0 — 7.5 ns toedis 57 I/O Cell OE to Output Disable — 6.0 — 7.5 ns tgoe 58 GRP Output Enable and Disable Delay — 0.0 — 0.0 ns ttoe 59 Test OE Enable and Disable Delay — 2.5 — 3.0 ns Clocks tioclk 60 I/O Clock Delay — 3.2 — 4.4 ns tgclk 61 Global Clock Delay — 2.7 — 3.4 ns tgclkeng 62 Global Clock Enable (Yx Clock) — 3.7 — 5.4 ns tgclkenio 63 Global Clock Enable (I/O Clock) — 5.7 — 8.4 ns tioclkeng 64 I/O Clock Enable (Yx Clock) — 4.2 — 6.4 ns Global Reset tgr 65 Global Reset to I/O Register Latch — 13.7 — 16.4 ns Internal Timing Parameters1 Over Recommended Operating Conditions 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to the Timing Model in this data sheet for further details.

(I/O INPUT) twltwh COMBINATORIAL I/O OUTPUT VALID INPUTDATA (I/O INPUT) tpd tsel VALID INPUTMUXSEL (I/O INPUT) Combinatorial Output COMBINATORIAL I/O OUTPUT OE (I/O INPUT) tentdis I/O Output Enable/Disable Registered Output Reset REGISTERED I/O OUTPUT trst RESET trw I/O Pin RESET TOE Y0,1,2,3 Y0,1,2,3, Enable tgclk #61 tgclkeng #62 tgclkenio #63 MUX0 MUX1 tgrp #33 MUX Expander Input GRP A B C D OE tgoe #58 tmuxexp #35 tmuxselexp #39 tiobp #48 CLK CLKEN MUX Expander Output tioob #49 tmuxd #34 tmuxs #36 tmuxio #37 tmuxg #38 tmuxcg #50 tmuxcio #51 tiod #52, #53 tgr #65 0902/gdxv/va tio #32 tfdbk #47 tioclk #60 tioclkeg #64 tiolat #40 tiosu #41 tioh #42 tioco #43 tior #44 tcesu #45 tceh #46 tob #54 tobs #55 toeen #56 toedis #57 ttoe #59 CLK CLKEN D Q DATA (I/O INPUT) REGISTERED I/O OUTPUT CLK CLKEN VALID INPUT tt h tsuce tceh tco 1/fmax (external fdbk) tgco su ispGDXVA Timing Model

Lattice’s ispGDX Development System Interface The ispGDX Development System supports ispGDX design using a simple language syntax and an easy-to- use Graphical User Interface (GUI) called Design Manager. From creation to In-System Programming, the ispGDX system is an easy-to-use, self-contained design tool delivered on CD-ROM media.

Features

• Easy-to-use Text Entry System
• ispGDX Design Compiler - Design Rule Checker - I/O Connectivity Checker - Automatic Compiler Function
• Industry Standard JEDEC File for Programming
• Min / Max Timing Report
• Interfaces To Popular Timing Simulators
• User Electronic Signature (UES) Support
• Detailed Log and Report Files For Easy Design Debug
• On-Line Help
• Windows ® 3.1x, Windows 95, Windows 98 and Win- dows NT® Compatible Graphical User Interface
• SUN O/S, Command Line Driven version available PC Version With the ispGDX GUI for the PC, command line entry is not required. The tools run under Microsoft Windows 3.1, Windows 95, Windows 98 and Windows NT. When the ispGDX software is invoked, the Design Manager and an accompanying message window are displayed. The Design Manager consists of the Menu Bar, Tool Bar, Status Bar and the work area. The figure below shows these elements of the ispGDX GUI. The Menu Bar displays topics related to functions used in the design process. Access the various drop-down menus and submenus by using the mouse or “hot” keys. The menu items available in the ispGDX system are FILE, EDIT, DEVICE, INVOKE, INTERFACES, VIEW, WIN- DOW and HELP. The Tool Bar is a quick and easy way to perform many of the functions found in the menus with a single click of the mouse. File, Edit, Undo, Redo, Find, Print Download and Compiler are just some of the Icons found in the ispGDX Tool Bar. For instance, the Compiler Icon performs the same function as the Invoke => Compiler menu com- mands, including design analysis and rule checking and the fitting operation. The Status Bar displays action prompts and the line and column numbers reflect the location of the cursor within the message window or the work area. Workstation Version The ispGDX software is also available for use under the ispGDX software is invoked from the command line under the UNIX operating system. A GUI is not supported in this environment. In the UNIX environment, the ispGDX Design File (GDF) must be created using a text editor. Once the GDF has been created, invoke the ispGDX workstation software from the UNIX command line. The following is an ex- ample of how to invoke ispGDX software. Usage: ispGDX [-i input_file] [-of[edif|orcad|viewlogic|verilog|vhdl]] [-p part name] [-r par_file] Where: -i input_file ispGDX design file -of [edif | orcad | viewlogic | Output format verilog | vhdl] -p part_name ispGDX part number -r par_file Read parameters from parameter file

The GDF file is a simple text description of the design function, device and pin parameters. The file has four parts: device selection, set and constant statements, a pin section and a connection section. A sample file looks like this: // 32-Bit Data 3 to 1 Mux DESIGN datamux; PART ispGDX160V-7Q208; PARAM SECURITY ON; PARAM OPENDRAIN ON; // USE OPEN DRAIN // OPTION PARAM PULL HOLD; // USE BUS HOLD // LATCH OPTION SET BUS_A [dataA31..dataA0]; SET BUS_B [dataB31..dataB0]; SET BUS_C [dataC31..dataC0]; SET BUS_D [dataD31..dataD0]; INPUT BUS_A {A31..A0}; INPUT BUS_B {B31..B0}; INPUT BUS_C {C31..C0}; OUTPUT BUS_D {D31..D0}; INPUT [oe] {B37}; INPUT [clk] {B36}; INPUT [sel1] {B38}; INPUT [sel0] {B39}; BEGIN BUS_D.m0 = BUS_A; BUS_D.m1 = BUS_B; BUS_D.m2 = BUS_C; BUS_D.m3 = VCC; // Default all // outputs to VCC BUS_D.s1 = sel1; BUS_D.s0 = sel0; BUS_D.oe = oe; BUS_D.clk = clk; END This example shows a simple, but complete, 32-bit 3:1 MUX design. Once completed, the compiler takes over. Powerful Syntax Lattice’s ispGDX Design System uses simple, but power- ful, syntax to easily define a design. The !(bang) operator controls pin polarity and can be used in both the pin and connection sections of the design definition. Dot exten- sions define data inputs, select controls for the 4:1 multiplexor, and control inputs of sequential elements and tri-state buffers. Dot extensions are .M# (MUX Input), .S# (MUX Select), and control functions, such as .CLK, .EN, .OE and .A (shown in adjacent table). Pin Attributes are assigned in the pin section of the GDF as well. SLOWSLEW selects the slow slew rate for an output buffer. The Pull parameter can be used to select the internal pull-up or bus hold latch. OPEN drain can be used to select open drain operation. The COMB attribute distinguishes the structure for bidirectional pins. If COMB is used, the input register, or latch, of an output buffer will be applied to bidirectional pins. Please consult the ispGDX Development System Manual for full details. Type Dot Ext. Description MUX Input MUX Selection Control MUX Output .M0 MUXA Data input to 4:1 MUX .M1 MUXB Data input to 4:1 MUX MUX0 Selection input to 4:1 MUX MUX1 Selection input to 4:1 MUX .M2 MUXC Data Input to 4:1 MUX .M3 .S0 .S1 MUXD Data input to 4:1 MUX .CLK Clock for a register .CE Clock enable for register clock .A Adjacent MUX output of an I/O cell .EN Latch enable for a latch signal .OE Output enable for 3-state output or bidirectional signal ispGDXV Dot Ext ispGDX GDF File Dot Extensions ispGDX Development System (Continued)

The ispGDX Design System Compiler After the GDF file is created, the compiler checks the syntax and provides helpful hints and the location of any syntax errors. The compiler performs design rule checks, such as, clock and enable designations, the use of input/ output/BIDI usage, and the proper use of attributes. I/O connectivity is also checked to ensure polarity, MUX selection controls, and connections are properly made. Compilation is completed automatically and report and programming files are saved. Reports Generated When the ispGDX system compiles a design and gener- ates the specified netlists, the following output files are created: Report Files: .log Compiler History .rpt Compiler Report .mfr Maximum Frequency Timing Report .tsu Set-up and Hold Timing Report .tco Clock to Out Timing Report .tpt Timing Report Simulation File: .sim Post-Route Simulation With LAC Format Netlists: .edo EDIF Output .vlo Verilog Output .ifo OrCAD Output .vho VHDL non-VITAL with Maximum Delays Output .vhn VHDL non-VITAL with Maximum Delays Output .vto VHDL VITAL Output Download: .jed JEDEC Device Programming File Third-Party Timing Simulation The ispGDX Design System will generate simulation netlists as specified by a user. The simulation netlist formats available are: EDIF, Verilog (OVI compliant), VHDL (VITAL compliant), Viewlogic, and OrCAD. For In-System Programming, Lattice’s ispGDX devices may be programmed, alone or in a chain with up to 100 other Lattice ISP devices, using Lattice’s ISP Daisy Chain Download software. This powerful Windows-based tool can be launched from the Tool Bar or by Invoking the Download option from the drop down menu within the ispGDX Design System. ISP Daisy Chain Download version 7.1 or above supports the ispGDX Family de- vices. ispGDX Development System (Continued)

Figure 9. ispJTAG Device Programming Interface state machine controls the programming. specified by the Instruction Table.

Scan Test Access Port (TAP) interface. test capability with only a single BSDL file. Table 3. I/O Shift Register Order Figure 10. Boundary Scan Register Circuit for I/O Pins Table 4. ispGDX80VA Device ID Codes

Figure 13. Boundary Scan Waveforms and Timing Specifications

I/O Input/Output Pins – These are the general purpose bidirectional data pins. When used as outputs, each may be independently latched, registered or tristated. They can also each assume one other control function (OE, CLK/CLKEN, and MUXsel as described in the text). RESET / I/O D10 This pin can be configured by the user through software to act as a RESET pin or as an I/O (I/O D10) The default is RESET. If programmed to act as RESET, this pin is an active LOW Input Pin and resets all I/O Register outputs when LOW. Y1/CLKEN1/TOE, Input Pins – These can be either Global Clocks or Clock Enables. In addition, Y1 is multiplexed with Y0/CLKEN0 TOE. Each pin can drive any or all I/O cell registers. The Test Output Enable (TOE) pin tristates all I/O pins when LOW EPEN Input Pin – JTAG TAP Controller Enable Pin. When high, JTAG operation is enabled. When low, JTAG TAP controller is driven to reset. TDI Input Pin – Serial data input during ISP programming or Boundary Scan mode. TCK Input Pin – Serial data clock during ISP programming or Boundary Scan mode. TMS Input Pin – Control input during ISP programming or Boundary Scan mode. TDO Output Pin – Serial data output during ISP programming or Boundary Scan mode. GND Ground (GND) VCC Vcc – Supply voltage (3.3V). VCCIO Input – This pin is used if optional 2.5V output is to be used. Every I/O can independently select either 3.3V or the optional voltage as its output level. If the optional output voltage is not required, this pin must be connected to the VCC supply. Programmable pull-up resistors and bus-hold latches only draw current from this supply. Signal Descriptions Signal Name Description

Signal Locations: ispGDX80VA Signal 100-Pin TQFP RESET /I/O D10 90 Y0/CLKEN0 38 Y1/CLKEN1/TOE 87 EPEN 35 TDI 39 TCK 36 TMS 86 TDO 85 GND 6, 18, 29, 45, 56, 68, 79, 95 VCC 12, 37, 62, 88 VCCIO 89 I/O A0 CLK 1 I/O A1 OE 2 I/O A2 MUXsel1 3 I/O A3 MUXsel2 4 I/O A4 CLK 5 GND I/O A5 OE 7 I/O A6 MUXsel1 8 I/O A7 MUXsel2 9 I/O A8 CLK 10 I/O A9 OE 11 VCC I/O A10 MUXsel1 13 I/O A11 MUXsel2 14 I/O A12 CLK 15 I/O A13 OE 16 I/O A14 MUXsel1 17 GND I/O A15 MUXsel2 19 I/O A16 CLK 20 I/O A17 OE 21 I/O A18 MUXsel1 22 I/O A19 MUXsel2 23 I/O B0 CLK 24 I/O B1 OE 25 I/O B2 MUXsel1 26 I/O B3 MUXsel2 27 I/O B4 CLK 28 GND I/O B5 OE 30 I/O B6 MUXsel1 31 I/O B7 MUXsel2 32 I/O B8 CLK 33 I/O B9 OE 34 VCC I/O B10 MUXsel1 40 I/O B11 MUXsel2 41 I/O B12 CLK 42 I/O B13 OE 43 I/O B14 MUXsel1 44 GND I/O B15 MUXsel2 46 I/O B16 CLK 47 I/O B17 OE 48 I/O B18 MUXsel1 49 I/O B19 MUXsel2 50 I/O C0 CLK 51 I/O C1 OE 52 I/O Locations: ispGDX80VA I/O Control 100 Signal Signal TQFP I/O Control 100 Signal Signal TQFP I/O Control 100 Signal Signal TQFP *I/O D10 is multiplexed with RESET. The functionality is programmable and selected through software. Note: VCC and GND Pads Shown for Reference I/O C2 MUXsel1 53 I/O C3 MUXsel2 54 I/O C4 CLK 55 GND I/O C5 OE 57 I/O C6 MUXsel1 58 I/O C7 MUXsel2 59 I/O C8 CLK 60 I/O C9 OE 61 VCC I/O C10 MUXsel1 63 I/O C11 MUXsel2 64 I/O C12 CLK 65 I/O C13 OE 66 I/O C14 MUXsel1 67 GND I/O C15 MUXsel2 69 I/O C16 CLK 70 I/O C17 OE 71 I/O C18 MUXsel1 72 I/O C19 MUXsel2 73 I/O D0 CLK 74 I/O D1 OE 75 I/O D2 MUXsel1 76 I/O D3 MUXsel2 77 I/O D4 CLK 78 GND I/O D5 OE 80 I/O D6 MUXsel1 81 I/O D7 MUXsel2 82 I/O D8 CLK 83 I/O D9 OE 84 VCC VCCIO I/O D10* MUXsel1 90 I/O D11 MUXsel2 91 I/O D12 CLK 92 I/O D13 OE 93 I/O D14 MUXsel1 94 GND I/O D15 MUXsel2 96 I/O D16 CLK 97 I/O D17 OE 98 I/O D18 MUXsel1 99 I/O D19 MUXsel2 100

Pin Configuration: ispGDX80VA ispGDX80VA 100-Pin TQFP Pinout Diagram I/O A0 I/O A1 I/O A2 I/O A3 I/O A4 GND I/O A5 I/O A6 I/O A7 I/O A8 I/O A9 VCC I/O A10 I/O A11 I/O A12 I/O A13 I/O A14 GND I/O A15 I/O A16 I/O A17 I/O A18 I/O A19 I/O B0 I/O B1 I/O C19 I/O C18 I/O C17 I/O C16 I/O C15 GND I/O C14 I/O C13 I/O C12 I/O C11 I/O C10 VCC I/O C9 I/O C8 I/O C7 I/O C6 I/O C5 GND I/O C4 I/O C3 I/O C2 I/O C1 I/O C0 100 ispGDX80VA Top View DataControl CLK OE MUXsel1 MUXsel2 CLK OE MUXsel1 MUXsel2 CLK OE MUXsel1 MUXsel2 CLK OE MUXsel1 MUXsel2 CLK OE MUXsel1 MUXsel2 CLK OE MUXsel2 MUXsel1 I/O D1 I/O D0 OE CLK OE CLK MUXsel2 MUXsel1 OE CLK MUXsel2 MUXsel1 OE CLK MUXsel2 MUXsel1 OE CLK MUXsel2 MUXsel1 OE CLK Data Control MUXsel2 MUXsel1 OE CLK MUXsel2 MUXsel1 OE CLK MUXsel2 MUXsel1 OE CLK MUXsel2 MUXsel1 OE CLK MUXsel2 MUXsel1 Data Control I/O D19 I/O D18 I/O D17 I/O D16 I/O D15 GND I/O D14 I/O D13 I/O D12 I/O D11 RESET/I/O D10 VCC VCCIO TMS Y1/CLKEN1/TOE I/O D9 I/O D8 I/O D7 I/O D6 I/O D5 GND I/O D4 I/O D3 I/O D2 I/O B2 I/O B3 I/O B4 GND I/O B5 I/O B6 I/O B7 I/O B8 I/O B9 I/O B10 TDI I/O B11 I/O B12 I/O B13 I/O B14 GND I/O B15 I/O B16 I/O B17 I/O B18 EPEN TCK VCC Y0/CLKEN0 Data MUXsel1 MUXsel2 CLK OE MUXsel1 MUXsel2 CLK OE MUXsel1 MUXsel2 CLK OE MUXsel1 MUXsel2 CLK OE MUXsel1 MUXsel2 Control I/O B19 TDO

Ordering Information

Blank = Commercial I = Industrial ispGDX 80VA X XXXX X Speed 3 = 3.5ns Tpd 5 = 5.0ns Tpd 7 = 7.0ns Tpd 9 = 9.0ns Tpd Package T100 = 100-Pin TQFP Device Family 0212/gdx80va Table 2-0041A/gdx80va 100-Pin TQFP5 ispGDX80VA-5T100ispGDXVA 100-Pin TQFP3.5 ispGDX80VA-3T100 100-Pin TQFP7 ispGDX80VA-7T100 FAMILY ORDERING NUMBER PACKAGEtpd (ns) COMMERCIAL Table 2-0041/gdx80va 100-Pin TQFP9 ispGDX80VA-9T100I 100-Pin TQFP7 ispGDX80VA-7T100I 100-Pin TQFP5 ispGDX80VA-5T100I ispGDXVA FAMILY ORDERING NUMBER PACKAGEtpd (ns) INDUSTRIAL Note: The ispGDX80VA devices are dual-marked with both Commercial and Industrial grades. The Commercial speed grade is faster, e.g. ispGDX80VA-3T100-5I.