74LS74 SYC | Alldatasheet

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Technical content

/C0068/C0117/C0097/C0108 /C0068/C0045/C0084/C0121/C0112/C0101 /C0080/C0111/C0115/C0105/C0116/C0105/C0118/C0101 /C0069/C0100/C0103/C0101/C0045/C0084/C0114/C0105/C0103/C0103/C0101/C0114/C0101/C0100 /C0070/C0108/C0105/C0112/C0045/C0070/C0108/C0111/C0112 The SN74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary Q and Q outputs. Information at input D is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or the LOW level, the D input signal has no effect. MODE SELECT – TRUTH TABLE OPERATING MODE INPUTS OUTPUTS OPERATING MODE SD SD D Q Q Set Reset (Clear) *Undetermined Load “1” (Set) Load “0” (Reset) L H L H H H L L H H X X X h l H L H H L L H H L H * Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable if SD and CD go HIGH simultaneously. If the levels at the set and clear are near VIL maximum then we cannot guarantee to meet the minimum level for VOH . H, h = HIGH Voltage Level L, I = LOW Voltage Level X = Don’t Care l, h (q) = Lower case letters indicate the state of the referenced input i, h (q) = (or output) one set-up time prior to the HIGH to LOW clock transition. GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 4.75 5.0 5.25 V TA Operating Ambient Temperature Range 0 25 70 °C IOH Output Current – High –0.4 mA IOL Output Current – Low 8.0 mA LOW POWER SCHOTTKY Device Package Shipping

ORDERING INFORMATION

SN74LS74AN 14 Pin DIP 2000 Units/Box SN74LS74AD 14 Pin SOIC D SUFFIX CASE 751A 2500/Tape & Reel PLASTIC N SUFFIX CASE 646 74LS74 www.sycelectronica.com.ar

LOGIC DIAGRAM (Each Flip-Flop) LOGIC SYMBOL SET (SD) 4 (10) CLEAR (CD) 1 (13) CLOCK 3 (11) D 2 (12) Q 5 (9) Q 6 (8) VCC = PIN 14 GND = PIN 7 5DQ CP QCD 9DQ CP QCD SD SD www.sycelectronica.com.ar

B A DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.715 0.770 18.16 18.80 B 0.240 0.260 6.10 6.60 C 0.145 0.185 3.69 4.69 D 0.015 0.021 0.38 0.53 F 0.040 0.070 1.02 1.78 G 0.100 BSC 2.54 BSC H 0.052 0.095 1.32 2.41 J 0.008 0.015 0.20 0.38 K 0.115 0.135 2.92 3.43 L N 0.015 0.039 0.38 1.01 /C0095/C0095 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. F HG D K C SEATING PLANE N –T– 14 PL M0.13 (0.005) L M J 0.290 0.310 7.37 7.87 N SUFFIX PLASTIC PACKAGE CASE 646–06 ISSUE M www.sycelectronica.com.ar

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. –A– –B– G P 7 PL 14 8 M0.25 (0.010) B M SBM0.25 (0.010) A ST –T– FR X 45 SEATING PLANE D 14 PL K C JM /C0095 DIM MIN MAX MIN MAX INCHESMILLIMETERS A 8.55 8.75 0.337 0.344 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7 P 5.80 6.20 0.228 0.244 R 0.25 0.50 0.010 0.019 /C0095/C0095/C0095/C0095 D SUFFIX PLASTIC SOIC PACKAGE CASE 751A–03 ISSUE F www.sycelectronica.com.ar