74LS273 SYC | Alldatasheet

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CONNECTION DIAGRAM DIP (TOP VIEW) Clock (Active HIGH Going Edge) Input Data Inputs Master Reset (Active LOW) Input Register Outputs CP D0 – D7 MR Q0 – Q7 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 /C0109A HIGH/1.6 mA LOW. HIGH LOW (Note a)LOADING PIN NAMES TRUTH TABLE MR CP D x Q x L X X L H H H H L L H = HIGH Logic Level L = LOW Logic Level X = Immaterial LOGIC DIAGRAM CP MR D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q 73 84 5 9 VCC = PIN 20 GND = PIN 10 = PIN NUMBERS 17 18 16 19 www.sycelectronica.com.ar

The SN74LS273 is an 8-Bit Parallel Register with a common Clock and common Master Reset. When the MR input is LOW, the Q outputs are LOW, independent of the other inputs. Information meeting the setup and hold time requirements of the D inputs is transferred to the Q outputs on the LOW-to-HIGH transition of the clock input. DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs VIL Input LOW Voltage 0.8 V Guaranteed Input LOW Voltage for All Inputs VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA VOH Output HIGH Voltage 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table VO Output LOW Voltage 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, VIN =V ILor VIHVOL O utput LOW Voltage 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table I Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V IIH Input HIGH C urrent 0.1 mA VCC = MAX, VIN = 7.0 V IIL Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX ICC Power Supply Current 27 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter Min Typ Max Unit Test Conditions fMAX Maximum Input Clock Frequency 30 40 MHz Figure 1 tPHL Propagation Delay, MR to Q Output 18 27 ns Figure 2 tPLH tPHL Propagation Delay, Clock to Output 17 ns Figure 1 AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter Min Typ Max Unit Test Conditions tw Pulse Width, Clock or Clear 20 ns Figure 1 ts Data Setup Time 20 ns Figure 1 th Hold Time 5.0 ns Figure 1 trec Recovery Time 25 ns Figure 2 www.sycelectronica.com.ar

CASE 738–03 ISSUE E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. M L J 20 PL MBM0.25 (0.010) T DIM MIN MAX MIN MAX MILLIMETERSINCHES A 25.66 27.171.010 1.070 B 6.10 6.600.240 0.260 C 3.81 4.570.150 0.180 D 0.39 0.550.015 0.022 G 2.54 BSC0.100 BSC J 0.21 0.380.008 0.015 K 2.80 3.550.110 0.140 L 7.62 BSC0.300 BSC M 0 15 0 15 N 0.51 1.010.020 0.040 /C0095/C0095/C0095/C0095 E 1.27 1.770.050 0.070 –A– SEATING PLANE K N FG D 20 PL –T– MAM0.25 (0.010) T E B C F 1.27 BSC0.050 BSC www.sycelectronica.com.ar