74LS221

74LS221 SYC | Alldatasheet

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Technical content

Features

I A dual, highly stable one-shot I Compensated for VCC and temperature variations I Pin-out identical to DM74LS123 (Note 1) I Output pulse width range from 30 ns to 70 seconds I Hysteresis provided at (B) input for added noise immunity I Direct reset terminates output pulse I Triggerable from CLEAR input I DTL, TTL compatible I Input clamp diodes Note 1: The pin-out is identical to DM74LS123 but, functionally it is not; refer to Operating Rules #10 in this datasheet. Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table H = HIGH Logic Level L = LOW Logic Level X = Can Be Either LOW or HIGH ↑ = Positive Going Transition ↓ = Negative Going Transition /c12 = A Positive Pulse /c13 = A Negative Pulse Note 2: This mode of triggering requires first the B input be set from a LOW-to-HIGH level while the CLEAR input is maintained at logic LOW level. Then with the B input at logic HIGH level, the CLEAR input whose positive transition from LOW-to-HIGH will trigger an output pulse. Order Number Package Number Package Description DM74LS221M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS221SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74LS221N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Inputs Outputs CLEAR A B Q Q LX X L H XH X L H XX L L H HL ↑ /c12/c13 H ↓ H /c12/c13 ↑ (Note 2) L H /c12/c13 www.sycelectronica.com.ar

The basic output pulse width is determined by selection of an external resistor (RX) and capacitor (CX). Once trig- gered, the basic pulse width is independent of further input transitions and is a function of the timing components, or it may be reduced or terminated by use of the active low CLEAR input. Stable output pulse width ranging from 30 ns to 70 seconds is readily obtainable. Operating Rules 1. An external resistor (RX) and an external capacitor (CX) are required for proper operation. The value of CX may vary from 0 to approximately 1000 µF. For small time constants high-grade mica, glass, polypropylene, polycarbonate, or polystyrene material capacitor may be used. For large time constants use tantalum or spe- cial aluminum capacitors. If timing capacitor has leak- ages approaching 100 nA or if stray capacitance from either terminal to ground is greater than 50 pF the tim- ing equations may not represent the pulse width the device generates. 2. When an electrolytic capacitor is used for C X a switch- ing diode is often required for standard TTL one-shots to prevent high inverse leakage current. This switching diode is not needed for the DM74LS221 one-shot and should not be used. Furthermore, if a polarized timing capacitor is used on the DM74LS221, the positive side of the capacitor should be connected to the “C EXT ” pin (Figure 1). 3. For CX >> 1000 pF, the output pulse width (tW ) is defined as follows: tW = KRX CX where [RX is in kΩ ] [CX is in pF] [tW is in ns] K ≈ Ln2 = 0.70 4. The multiplicative factor K is plotted as a function of CX for design considerations: (See Figure 4). 5. For CX < 1000 pF see Figure 3 for tW vs. CX family curves with RX as a parameter. 6. To obtain variable pulse widths by remote trimming, the following circuit is recommended: (See Figure 2). 7. Output pulse width versus VCC and temperatures: Fig- ure 5 depicts the relationship between pulse width vari- ation versus VCC . Figure 6 depicts pulse width variation versus temperatures. 8. Duty cycle is defined as tW /T × 100 in percentage, if it goes above 50% the output pulse width will become shorter. If the duty cycle varies between LOW and HIGH values, this causes output pulse width to vary, or jitter (a function of the REXT only). To reduce jitter, REXT should be as large as possible, for example, with R EXT = 100k jitter is not appreciable until the duty cycle approaches 90%. 9. Under any operating condition CX and RX must be kept as close to the one-shot device pins as possible to min- imize stray capacitance, to reduce noise pick-up, and to reduce I-R and Ldi/dt voltage developed along their connecting paths. If the lead length from C X to pins (6) and (7) or pins (14) and (15) is greater than 3 cm, for example, the output pulse width might be quite different from values predicted from the appropriate equations. A non-inductive and low capacitive path is necessary to ensure complete discharge of C X in each cycle of its operation so that the output pulse width will be accu- rate. 10. Although the DM74LS221's pin-out is identical to the DM74LS123 it should be remembered that they are not functionally identical. The DM74LS123 is a retrigger- able device such that the output is dependent upon the input transitions when its output “Q ” is at the “High” state. Furthermore, it is recommended for the DM74LS123 to externally ground the C EXT pin for improved system performance. However, this pin on the DM74LS221 is not an internal connection to the device ground. Hence, if substitution of an DM74LS221 onto an DM74LS123 design layout where the C EXT pin is wired to the ground, the device will not function. 11. VCC and ground wiring should conform to good high- frequency standards and practices so that switching transients on the VCC and ground return leads do not cause interaction between one-shots. A 0.01 µF to 0.10 µF bypass capacitor (disk ceramic or monolithic type) from VCC to ground is necessary on each device. Fur- thermore, the bypass capacitor should be located as close to the VCC -pin as space permits. www.sycelectronica.com.ar

Absolute Maximum Ratings(Note 3) Note 3: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Recommended Operating Conditions Note 4: TA = 25°C and VCC = 5V. Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range 0°C to +70°C Storage Temperature Range −65°C to +150°C Symbol Parameter Min Nom Max Units V CC Supply Voltage 4.75 5 5.25 V VT+ Positive-Going Input Threshold Voltage 12Vat the A Input (VCC = Min) VT− Negative-Going Input Threshold Voltage 0.8 1 Vat the A Input (VCC = Min) VT+ Positive-Going Input Threshold Voltage 12Vat the B Input (VCC = Min) VT− Negative-Going Input Threshold Voltage 0.8 0.9 Vat the B Input (VCC = Min) IOH HIGH Level Output Current −0.4 mA IOL LOW Level Output Current 8 mA tW Pulse Width Data 40 ns(Note 4) Clear 40 tREL Clear Release Time (Note 4) 15 ns Rate of Rise or Fall of 1Schmitt Input (B) (Note 4) Rate of Rise or Fall of 1Logic Input (A) (Note 4) R EXT External Timing Resistor (Note 4) 1.4 100 k Ω C EXT External Timing Capacitance (Note 4) 0 1000 µF DC Duty Cycle R T = 2 kΩ 50 %(Note 4) R T = REXT (Max) 60 TA Free Air Operating Temperature 0 70 °C www.sycelectronica.com.ar

Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted) Note 5: All typicals are at VCC = 5V, TA = 25°C. Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second. Switching Characteristics at VCC = 5V and TA = 25°C Symbol Parameter Conditions Min Typ Max Units (Note 5) VI Input Clamp Voltage V CC = Min, II = −18 mA −1.5 V VOH HIGH Level V CC = Min, IOH = Max 2.7 3.4 V Output Voltage V IL = Max, VIH = Min VOL LOW Level V CC = Min, IOL = Max 0.35 0.5 Output Voltage V IL = Max, VIH = Min V VCC = Min, IOL = 4 mA 0.4 II Input Current @ Max Input Voltage VCC = Max, VI = 7V 0.1 mA IIH HIGH Level Input Current V CC = Max, VI = 2.7V 20 µA IIL LOW Level V CC = Max A1, A2 −0.4 Input Current V I = 0.4V B −0.8 mA Clear −0.8 IOS Short Circuit V CC = Max −20 −100 mA Output Current (Note 6) ICC Supply Current V CC = Max Quiescent 4.7 11 mA Triggered 19 27 Symbol Parameter From (Input) Conditions Min Max Units To (Output) tPLH Propagation Delay Time A1, A2 C EXT = 80 pF 70 ns LOW-to-HIGH Level Output to Q R EXT = 2 kΩ tPLH Propagation Delay Time B C L = 15 pF 55 ns LOW-to-HIGH Level Output to Q R L = 2 kΩ tPHL Propagation Delay Time A1, A2 80 ns HIGH-to-LOW Level Output to Q tPHL Propagation Delay Time B 65 ns HIGH-to-LOW Level Output to Q tPLH Propagation Delay Time Clear to 65 ns LOW-to-HIGH Level Output Q tPHL Propagation Delay Time Clear 55 ns HIGH-to-LOW Level Output to Q tW(out) Output Pulse A1, A2 C EXT = 0 Width Using Zero to Q, Q R EXT = 2 kΩ 20 70 ns Timing Capacitance R L = 2 kΩ C L = 15 pF tW(out) Output Pulse A1, A2 C EXT = 100 pF Width Using External to Q, Q R EXT = 10 kΩ 600 750 ns Timing Resistor R L = 2 kΩ C L = 15 pF C EXT = 1 µF R EXT = 10 kΩ 67 . 5 m s R L = 2 kΩ C L = 15 pF C EXT = 80 pF R EXT = 2 kΩ 70 150 ns R L = 2 kΩ C L = 15 pF www.sycelectronica.com.ar

Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A www.sycelectronica.com.ar

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D www.sycelectronica.com.ar

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E www.sycelectronica.com.ar