Logic IC

74HC-HCT595

SYC Electronica

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

Manufacturer: SYC Electronica

Document: 28 Pages / 180Kb

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PDF pages: 28

Technical content

Product speciﬁcation Supersedes data of 1998 Jun 04

2003 Jun 25

74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

2003 Jun 25 2

Philips Semiconductors Product speciﬁcation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595

FEATURES

8-bit serial input
8-bit serial or parallel output
Storage register with 3-state outputs
Shift register with direct clear
100 MHz (typical) shift out frequency
ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V.

APPLICATIONS

Serial-to-parallel data conversion
Remote control holding register.

DESCRIPTION

The 74HC/HCT595 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT595 is an 8-stage serial shift register with a storage register and 3-state outputs. The shift register and storage register have separate clocks. Data is shifted on the positive-going transitions of the SH_CP input. The data in each register is transferred to the storage register on a positive-going transition of the ST_CP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. The shift register has a serial input (DS) and a serial standard output (Q7’) for cascading. It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. QUICK REFERENCE DATA GND = 0 V; T amb =2 5°C; tr =tf= 6 ns. Notes 1. C PD is used to determine the dynamic power dissipation (PD inµW). PD =C PD × VCC 2 × fi× N+ Σ(CL × VCC 2 × fo) where: fi= input frequency in MHz; fo = output frequency in MHz; C L = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ(C L × VCC 2 × fo) = sum of the outputs. 2. For 74HC595 the condition is VI= GND to VCC . For 74HCT595 the condition is VI= GND to VCC − 1.5 V. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT 74HC 74HCT tPHL /tPLH propagation delay C L = 50 pF; VCC = 4.5 V SH_CP to Q7’ 19 25 ns SH_CP to Qn 20 24 ns MR to Q7’ 100 52 ns fmax maximum clock frequency SH_CP and ST_CP 100 57 MHz C I input capacitance 3.5 3.5 pF C PD power dissipation capacitance per package notes 1 and 2 115 130 pF www.sycelectronica.com.ar

2003 Jun 25 3

Philips Semiconductors Product speciﬁcation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 FUNCTION TABLE See note 1. Note 1. H = HIGH voltage level; L = LOW voltage level; ↑ = LOW-to-HIGH transition; ↓ = HIGH-to-LOW transition; Z = high-impedance OFF-state; n.c. = no change; X = don’t care.

ORDERING INFORMATION

SH_CP ST_CP OE MR DS Q7’ Qn X X L L X L n.c. a LOW level on MR only affects the shift registers X ↑ L L X L L empty shift register loaded into storage register X X H L X L Z shift register clear; parallel outputs in high-impedance OFF-state ↑ X L H H Q6’ n.c. logic high level shifted into shift register stage 0; contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q6’) appears on the serial output (Q7’) X ↑ L H X n.c. Qn’ contents of shift register stages (internal Qn’) are transferred to the storage register and parallel output stages ↑↑ L H X Q6’ Qn’ contents of shift register shifted through; previous contents of the shift register is transferred to the storage register and the parallel output stages TYPE NUMBER PACKAGE TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE 74HC595N −40 to +125°C 16 DIP16 plastic SOT38-4 74HCT595N −40 to +125°C 16 DIP16 plastic SOT38-4 74HC595D −40 to +125°C 16 SO16 plastic SOT109-1 74HCT595D −40 to +125°C 16 SO16 plastic SOT109-1 74HC595DB −40 to +125°C 16 SSOP16 plastic SOT338-1 74HCT595DB −40 to +125°C 16 SSOP16 plastic SOT338-1 74HC595PW −40 to +125°C 16 TSSOP16 plastic SOT403-1 74HCT595PW −40 to +125°C 16 TSSOP16 plastic SOT403-1 74HC595BQ −40 to +125°C 16 DHVQFN16 plastic SOT763-1 74HCT595BQ −40 to +125°C 16 DHVQFN16 plastic SOT763-1 www.sycelectronica.com.ar

2003 Jun 25 4

Philips Semiconductors Product speciﬁcation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 PINNING PIN SYMBOL DESCRIPTION

1 Q1 parallel data output

2 Q2 parallel data output

3 Q3 parallel data output

4 Q4 parallel data output

5 Q5 parallel data output

6 Q6 parallel data output

7 Q7 parallel data output

8 GND ground (0 V)

9 Q7’ serial data output

MR master reset (active LOW)

11 SH_CP shift register clock input

12 ST_CP storage register clock input

OE output enable (active LOW)

14 DS serial data input

15 Q0 parallel data output

CC positive supply voltage handbook, halfpage Q7' DS GND ST_CP SH_CP VCC OE 595 MLA001 MR Fig.1 Pin configuration DIP16, SO16 and (T)SSOP16. handbook, halfpage 11 6 GND (1) Q1 VCC 61 1 GNDTop view MBL893 Q7' MR SH_CP ST_CP OE DS Fig.2 Pin configuration DHVQFN16. (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. www.sycelectronica.com.ar

2003 Jun 25 5

Philips Semiconductors Product speciﬁcation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 handbook, halfpage OEMR 1310 11 12 MLA002 Q7' DS ST_CPSH_CP Fig.3 Logic symbol. handbook, halfpage MSA698 1D 2D C1/ C212

13 EN3

Q7' DS ST_CP SH_CP Fig.4 IEC logic symbol. handbook, full pagewidth ST_CP DS SH_CP MR Q7' 8-STAGE SHIFT REGISTER 8-BIT STORAGE REGISTER OE 3-STATE OUTPUTS Q0 15

13 MLA003

Fig.5 Functional diagram. www.sycelectronica.com.ar

2003 Jun 25 6

Philips Semiconductors Product speciﬁcation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 handbook, full pagewidth STAGE 0 STAGES 1 to 6 STAGE 7 FF0 D CP Q R LATCH D CP Q FF7 D CP Q R LATCH D CP Q MLA010 DQ Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q7' DS ST_CP SH_CP OE MR Fig.6 Logic diagram. www.sycelectronica.com.ar

2003 Jun 25 7

2003 Jun 25 8

Philips Semiconductors Product speciﬁcation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 RECOMMENDED OPERATING CONDITIONS LIMITED VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). Note 1. For DIP16 packages: above 70°C derate linearly with 12 mW/K. For SO16 packages: above 70°C derate linearly with 8 mW/K. For SSOP16 packages: above 60°C derate linearly with 5.5 mW/K. For TSSOP16 packages: above 60°C derate linearly with 5.5 mW/K. For DHVQFN16 packages: above 60°C derate linearly with 4.5 mW/K. SYMBOL PARAMETER CONDITIONS 74HC 74HCT UNIT VI input voltage 0 − VCC 0 − VCC V VO output voltage 0 − VCC 0 − VCC V Tamb ambient temperature −40 − +125 −40 − +125 °C tr,tf input rise and fall time VCC = 2.0 V −− 1000 −−− ns VCC = 4.5 V − 6.0 500 − 6.0 500 ns SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC supply voltage −0.5 +7.0 V IIK input diode current V I< −0.5 V to VI>V CC + 0.5 V −± 20 mA IOK output diode current V O < −0.5 V to VO >V CC + 0.5 V −± 20 mA IO output source or sink current VO = −0.5 V to VCC + 0.5 V Q7’ standard output −± 25 mA Qn bus driver outputs −± 35 mA ICC , IGND VCC or GND current −± 70 mA Tstg storage temperature −65 +150 °C Ptot power dissipation T amb = −40 to +125°C; note 1 − 500 mW www.sycelectronica.com.ar

2003 Jun 25 9

Philips Semiconductors Product speciﬁcation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 DC CHARACTERISTICS Type 74HC At recommended operating conditions; voltages are referenced to GND (ground=0V ) . SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT OTHER V CC (V) Tamb = −40 to +85°C ; note 1 VIH HIGH-level input voltage 2.0 1.5 1.2 − V 4.5 3.15 2.4 − V 6.0 4.2 3.2 − V VIL LOW-level input voltage 2.0 − 0.8 0.5 V 4.5 − 2.1 1.35 V 6.0 − 2.8 1.8 V VOH HIGH-level output voltage VI=V IH or VIL all outputs IO = −20 µA 2.0 1.9 2.0 − V 4.5 4.4 4.5 − V 6.0 5.9 6.0 − V Q7’ standard output IO = −4.0 mA 4.5 3.84 4.32 − V IO = −5.2 mA 6.0 5.34 5.81 − V Qn bus driver outputs IO = −6.0 mA 4.5 3.84 4.32 − V IO = −7.8 mA 6.0 5.34 5.81 − V VOL LOW-level output voltage VI=V IH or VIL all outputs IO =2 0µA 2.0 − 0 0.1 V 4.5 − 0 0.1 V 6.0 − 0 0.1 V Q7’ standard output IO = 4.0 mA 4.5 − 0.15 0.33 V IO = 5.2 mA 6.0 − 0.16 0.33 V Qn bus driver outputs IO = 6.0 mA 4.5 − 0.16 0.33 V IO = 7.8 mA 6.0 − 0.16 0.33 V ILI input leakage current VI=V CC or GND 6.0 −−± 1.0 µA IOZ 3-state output OFF-state current VI=V IH or VIL; VO =V CC or GND 6.0 −−± 5.0 µA ICC quiescent supply current VI=V CC or GND; IO =0 6.0 −− 80 µA www.sycelectronica.com.ar

2003 Jun 25 10

Philips Semiconductors Product speciﬁcation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 Note 1. All typical values are measured at Tamb =2 5°C. Tamb = −40 to +125°C VIH HIGH-level input voltage 2.0 1.5 −− V 4.5 3.15 −− V 6.0 4.2 −− V VIL LOW-level input voltage 2.0 −− 0.5 V 4.5 −− 1.35 V 6.0 −− 1.8 V VOH HIGH-level output voltage VI=V IH or VIL all outputs IO = −20 µA 2.0 1.9 −− V 4.5 4.4 −− V 6.0 5.9 −− V Q7’ standard output Qn bus driver outputs VOL LOW-level output voltage VI=V IH or VIL all outputs IO =2 0µA 4.5 −− 0.1 V Q7’ standard output IO = 4.0 mA 4.5 −− 0.4 V Qn bus driver outputs IO = 6.0 mA 4.5 −− 0.4 V ILI input leakage current VI=V CC or GND 5.5 −−± 1.0 µA IOZ 3-state output OFF-state current VI=V IH or VIL; VO =V CC or GND 5.5 −−± 10.0 µA ICC quiescent supply current VI=V CC or GND; IO =0 5.5 −− 160 µA SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT OTHER V CC (V) www.sycelectronica.com.ar

2003 Jun 25 11

Philips Semiconductors Product speciﬁcation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 Type 74HCT At recommended operating conditions; voltages are referenced to GND (ground = 0 V); tr =tf= 6 ns; CL =5 0p F . SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT OTHER V CC (V) Tamb = −40 to +85°C; note 1 VIH HIGH-level input voltage 4.5 to 5.5 2.0 1.6 − V VIL LOW-level input voltage 4.5 to 5.5− 1.2 0.8 V VOH HIGH-level output voltage VI=V IH or VIL all outputs IO = −20 µA 4.5 4.4 4.5 − V Q7’ standard output IO = −4.0 mA 4.5 3.84 4.32 − V Qn bus driver outputs IO = −6.0 mA 4.5 3.7 4.32 − V VOL LOW-level output voltage VI=V IH or VIL all outputs IO =2 0µA 4.5 − 0 0.33 V Q7’ standard output IO = 4.0 mA 4.5 − 0.15 0.33 V Qn bus driver outputs IO = 6.0 mA 4.5 − 0.16 0.33 V ILI input leakage current VI=V CC or GND 5.5 −−± 1.0 µA IOZ 3-state output OFF-state current VI=V IH or VIL; VO =V CC or GND 5.5 −−± 5.0 µA ICC quiescent supply current VI=V CC or GND; IO =0 5.5 −− 80 µA ΔICC additional supply current per input VI=V CC − 2.1 V; IO = 0; note 2 4.5 to 5.5− 100 450 µA www.sycelectronica.com.ar

2003 Jun 25 12

Philips Semiconductors Product speciﬁcation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 Notes 1. All typical values are measured at Tamb =2 5°C. 2. The value of additional quiescent supply current (ΔICC ) for a unit load of 1 is given here. To determineΔICC per input, multiply this value by the unit load coefficient per input pin: a. pin DS: 0.25 b. pins MR, SH_CP, ST_CP and OE: 1.50. Tamb = −40 to +125°C VIH HIGH-level input voltage VIL LOW-level input voltage 4.5 to 5.5−− 0.8 V VOH HIGH-level output voltage VI=V IH or VIL all outputs IO = −20 µA 4.5 4.4 −− V Q7’ standard output Qn bus driver outputs VOL LOW-level output voltage VI=V IH or VIL all outputs IO =2 0µA 4.5 −− 0.1 V Q7’ standard output IO = 4.0 mA 4.5 −− 0.4 V Qn bus driver outputs IO = 6.0 mA 4.5 −− 0.4 V ILI input leakage current VI=V CC or GND 5.5 −−± 1.0 µA IOZ 3-state output OFF-state current VI=V IH or VIL; VO =V CC or GND 5.5 −−± 10.0 µA ICC quiescent supply current VI=V CC or GND; IO =0 5.5 −− 160 µA ΔICC additional supply current per input VI=V CC − 2.1 V; IO = 0; note 2 4.5 to 5.5−− 490 µA SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT OTHER V CC (V) www.sycelectronica.com.ar

2003 Jun 25 13

Philips Semiconductors Product speciﬁcation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 AC CHARACTERISTICS Family 74HC GND = 0 V; tr =tf= 6 ns; CL =5 0p F . SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT WAVEFORMS V CC (V) Tamb =2 5°C tPHL /tPLH propagation delay SH_CP to Q7’ see Fig.7 2.0 − 52 160 ns 4.5 − 19 32 ns 6.0 − 15 27 ns propagation delay ST_CP to Qn see Fig.8 2.0 − 55 175 ns 4.5 − 20 35 ns 6.0 − 16 30 ns tPHL propagation delay MR to Q7’ see Fig.10 2.0 − 47 175 ns 4.5 − 17 35 ns 6.0 − 14 30 ns tPZH /tPZL 3-state output enable time OE to Qn see Fig.11 2.0 − 47 150 ns 4.5 − 17 30 ns 6.0 − 14 26 ns tPHZ /tPLZ 3-state output disable time OE to Qn see Fig.11 2.0 − 41 150 ns 4.5 − 15 30 ns 6.0 − 12 26 ns tW shift clock pulse width HIGH or LOW see Fig.7 2.0 75 17 − ns 4.5 15 6 − ns 6.0 13 5 − ns storage clock pulse width HIGH or LOW see Fig.8 2.0 75 11 − ns 4.5 15 4 − ns 6.0 13 3 − ns master reset pulse width LOW see Fig.10 2.0 75 17 − ns 4.5 15 6.0 − ns 6.0 13 5.0 − ns tsu set-up time DS to SH_CP see Fig.9 2.0 50 11 − ns 4.5 10 4.0 − ns 6.0 9.0 3.0 − ns set-up time SH_CP to ST_CP see Fig.8 2.0 75 22 − ns 4.5 15 8 − ns 6.0 13 7 − ns th hold time DS to SH_CP see Fig.9 2.0 +3 −6 − ns 4.5 +3 −2 − ns 6.0 +3 −2 − ns www.sycelectronica.com.ar

2003 Jun 25 14

Philips Semiconductors Product speciﬁcation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 trem removal timeMR to SH_CP see Fig.10 2.0 +50 −19 − ns 4.5 +10 −7 − ns 6.0 +9 −6 − ns fmax maximum clock pulse frequency SH_CP or ST_CP see Figs 7 and 8 2.0 9 30 − MHz 4.5 30 91 − MHz 6.0 35 108 − MHz T amb = −40 to +85°C tPHL /tPLH propagation delay SH_CP to Q7’ see Fig.7 2.0 −− 200 ns 4.5 −− 40 ns 6.0 −− 34 ns propagation delay ST_CP to An see Fig.8 2.0 −− 220 ns 4.5 −− 44 ns 6.0 −− 37 ns tPHL propagation delay MR to Q7’ see Fig.10 2.0 −− 220 ns 4.5 −− 44 ns 6.0 −− 37 ns tPZH /tPZL 3-state output enable time OE to Qn see Fig.11 2.0 −− 190 ns 4.5 −− 38 ns 6.0 −− 33 ns tPHZ /tPLZ 3-state output disable time OE to Qn see Fig.11 2.0 −− 190 ns 4.5 −− 38 ns 6.0 −− 33 ns tW shift clock pulse width HIGH or LOW see Fig.7 2.0 95 −− ns 4.5 19 −− ns 6.0 16 −− ns storage clock pulse width HIGH or LOW see Fig.8 2.0 95 −− ns 4.5 19 −− ns 6.0 16 −− ns master reset pulse width LOW see Fig.10 2.0 95 −− ns 4.5 19 −− ns 6.0 16 −− ns tsu set-up time DS to SH_CP see Fig.9 2.0 65 −− ns 4.5 13 −− ns 6.0 11 −− ns set-up time SH_CP to ST_CP see Fig.8 2.0 95 −− ns 4.5 19 −− ns 6.0 16 −− ns SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT WAVEFORMS V CC (V) www.sycelectronica.com.ar

2003 Jun 25 15

Philips Semiconductors Product speciﬁcation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 th hold time DS to SH_CP see Fig.9 2.0 3 −− ns 4.5 3 −− ns 6.0 3 −− ns trem removal timeMR to SH_CP see Fig.10 2.0 65 −− ns 4.5 13 −− ns 6.0 11 −− ns fmax maximum clock pulse frequency SH_CP or ST_CP see Figs 7 and 8 2.0 4.8 −− MHz 4.5 24 −− MHz 6.0 28 −− MHz T amb = −40 to +125°C tPHL /tPLH propagation delay SH_CP to Q7’ see Fig.7 2.0 −− 240 ns 4.5 −− 48 ns 6.0 −− 41 ns propagation delay ST_CP to Qn see Fig.8 2.0 −− 265 ns 4.5 −− 53 ns 6.0 −− 45 ns tPHL propagation delay MR to Q7’ see Fig.10 2.0 −− 265 ns 4.5 −− 53 ns 6.0 −− 45 ns tPZH /tPZL 3-state output enable time OE to Qn see Fig.11 2.0 −− 225 ns 4.5 −− 45 ns 6.0 −− 38 ns tPHZ /tPLZ 3-state output disable time OE to Qn see Fig.11 2.0 −− 225 ns 4.5 −− 45 ns 6.0 −− 38 ns tW shift clock pulse width HIGH or LOW see Fig.7 2.0 110 −− ns 4.5 22 −− ns 6.0 19 −− ns storage clock pulse width HIGH or LOW see Fig.8 2.0 110 −− ns 4.5 22 −− ns 6.0 19 −− ns master reset pulse width LOW see Fig.10 2.0 110 −− ns 4.5 22 −− ns 6.0 19 −− ns SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT WAVEFORMS V CC (V) www.sycelectronica.com.ar

2003 Jun 25 16

Philips Semiconductors Product speciﬁcation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 tsu set-up time DS to SH_CP see Fig.9 2.0 75 −− ns 4.5 15 −− ns 6.0 13 −− ns set-up time SH_CP to ST_CP see Fig.8 2.0 110 −− ns 4.5 22 −− ns 6.0 19 −− ns th hold time DS to SH_CP see Fig.9 2.0 3 −− ns 4.5 3 −− ns 6.0 3 −− ns trem removal timeMR to SH_CP see Fig.10 2.0 75 −− ns 4.5 15 −− ns 6.0 13 −− ns fmax maximum clock pulse frequency SH_CP or ST_CP see Figs 7 and 8 2.0 4 −− MHz 4.5 20 −− MHz 6.0 24 −− MHz SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT WAVEFORMS V CC (V) www.sycelectronica.com.ar

2003 Jun 25 17

Philips Semiconductors Product speciﬁcation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 Family 74HCT GND = 0 V; tr =tf= 6 ns; CL =5 0p F . SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT WAVEFORMS V CC (V) Tamb =2 5°C tPHL /tPLH propagation delay SH_CP to Q7’ see Fig.7 4.5 − 25 42 ns propagation delay ST_CP to Qn see Fig.8 4.5 − 24 40 ns tPHL propagation delay MR to Q7’ see Fig.10 4.5 − 23 40 ns tPZH /tPZL 3-state output enable time OE to Qn see Fig.11 4.5 − 21 35 ns tPHZ /tPLZ 3-state output disable time OE to Qn see Fig.11 4.5 − 18 30 ns tW shift clock pulse width HIGH or LOW see Fig.7 4.5 16 6 − ns storage clock pulse width HIGH or LOW see Fig.8 4.5 16 5 − ns master reset pulse width LOW see Fig.10 4.5 20 8 − ns tsu set-up time DS to SH_CP see Fig.9 4.5 16 5 − ns set-up time SH_CP to ST_CP see Fig.8 4.5 16 8 − ns th hold time DS to SH_CP see Fig.9 4.5 +3 −2 − ns trem removal time MR to SH_CP see Fig.10 4.5 +10 −7 − ns fmax maximum clock pulse frequency SH_CP or ST_CP see Figs 7 and 8 4.5 30 52 − MHz T amb = −40 to +85°C tPHL /tPLH propagation delay SH_CP to Q7’ see Fig.7 4.5 −− 53 ns propagation delay ST_CP to Qn see Fig.8 4.5 −− 50 ns tPHL propagation delay MR to Q7’ see Fig.10 4.5 −− 50 ns tPZH /tPZL 3-state output enable time OE to Qn see Fig.11 4.5 −− 44 ns tPHZ /tPLZ 3-state output disable time OE to Qn see Fig.11 4.5 −− 38 ns www.sycelectronica.com.ar

2003 Jun 25 18

Philips Semiconductors Product speciﬁcation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 tW shift clock pulse width HIGH or LOW see Fig.7 4.5 20 −− ns storage clock pulse width HIGH or LOW see Fig.8 4.5 20 −− ns master reset pulse width LOW see Fig.10 4.5 25 −− ns tsu set-up time DS to SH_CP see Fig.9 4.5 20 −− ns set-up time SH_CP to ST_CP see Fig.8 4.5 20 −− ns th hold time DS to SH_CP see Fig.9 4.5 3 −− ns trem removal time MR to SH_CP see Fig.10 4.5 13 −− ns fmax maximum clock pulse frequency SH_CP or ST_CP see Figs 7 and 8 4.5 24 −− MHz T amb = −40 to +125°C tPHL /tPLH propagation delay SH_CP to Q7’ see Fig.7 4.5 −− 63 ns propagation delay ST_CP to Qn see Fig.8 4.5 −− 60 ns tPHL propagation delay MR to Q7’ see Fig.10 4.5 −− 60 ns tPZH /tPZL 3-state output enable time OE to Qn see Fig.11 4.5 −− 53 ns tPHZ /tPLZ 3-state output disable time OE to Qn see Fig.11 4.5 −− 45 ns tW shift clock pulse width HIGH or LOW see Fig.7 4.5 24 −− ns storage clock pulse width HIGH or LOW see Fig.8 4.5 24 −− ns master reset pulse width LOW see Fig.10 4.5 30 −− ns tsu set-up time DS to SH_CP see Fig.9 4.5 24 −− ns set-up time SH_CP to ST_CP see Fig.8 4.5 24 −− ns th hold time DS to SH_CP see Fig.9 4.5 3 −− ns trem removal time MR to SH_CP see Fig.10 4.5 15 −− ns fmax maximum clock pulse frequency SH_CP or ST_CP see Figs 7 and 8 4.5 20 −− MHz SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT WAVEFORMS V CC (V) www.sycelectronica.com.ar

2003 Jun 25 19

Philips Semiconductors Product speciﬁcation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 AC WAVEFORMS handbook, full pagewidth MSA699 tPLH tPHL tW 1/fmax VM VMSH_CP input Q7' output tTHLtTLH 90% 10% Fig.7 Waveforms showing the clock (SH_CP) to output (Q7’) propagation delays, the shift clock pulse width and maximum shift clock frequency. 74HC595: VM = 50%; VI= GND to VCC . 74HCT595: VM = 1.3 V; VI= GND to 3 V. handbook, full pagewidth MSA700 tPLH tPHL tW 1/fmax VM VM VM ST_CP input tsu SH_CP input Qn output Fig.8 Waveforms showing the storage clock (ST_CP) to output (Qn) propagation delays, the storage clock pulse width and the shift clock to storage clock set-up time. 74HC595: VM = 50%; VI= GND to VCC . 74HCT595: VM = 1.3 V; VI= GND to 3 V. www.sycelectronica.com.ar

2003 Jun 25 20

Philips Semiconductors Product speciﬁcation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 handbook, full pagewidth MLB196 th tsu th tsu Q7' output SH_CP input DS input VM VM VM Fig.9 Waveforms showing the data set-up and hold times for the DS input. 74HC595: VM = 50%; VI= GND to VCC . 74HCT595: VM = 1.3 V; VI= GND to 3 V. The shaded areas indicate when the input is permitted to change for predictable output performance. handbook, full pagewidth MLB197 tPHL tW VM VM VM SH_CP input trem MR input Q7' output Fig.10 Waveforms showing the Master Reset (MR) pulse width, the master reset to output (Q7’) propagation delay and the master reset to shift clock (SH_CP) removal time. 74HC595: VM = 50%; VI= GND to VCC . 74HCT595: VM = 1.3 V; VI= GND to 3 V. www.sycelectronica.com.ar

2003 Jun 25 21

Philips Semiconductors Product speciﬁcation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 handbook, full pagewidth MSA697 tPLZ tPHZ outputs disabled outputs enabled 90% 10% outputs enabled OE input VM tPZL tPZH VM VM Qn output LOW-to-OFF OFF-to-LOW Qn output HIGH-to-OFF OFF-to-HIGH tr tf 90% 10% Fig.11 Waveforms showing the 3-state enable and disable times for inputOE. 74HC595: VM = 50%; VI= GND to VCC . 74HCT595: VM = 1.3 V; VI= GND to 3 V. handbook, full pagewidth MGK563 D.U.T VCC VCC VI VO R T RL = 1 kΩ C L 50 pF PULSE GENERATOR Fig.12 Test circuit for 3-state outputs. Definitions for test circuit: R L = Load resistor. C L = Load capacitance including jig and probe capacitance. R T = Termination resistance should be equal to the output impedance Zo of the pulse generator. TEST SWITCH tPLH /tPHL open tPLZ /tPZL VCC tPHZ /tPZH GND www.sycelectronica.com.ar

2003 Jun 25 22

Philips Semiconductors Product speciﬁcation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 PACKAGE OUTLINES REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA SOT38-4 95-01-14 03-02-13 M H c (e )1 M E A L seating plane w M e D A 2 Z E pin 1 index b 0 5 10 mm scale Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. UNIT A max. 12 b1 (1) (1) (1) b2 cD E e M ZHL mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) A min. A max. b max.wM Ee1 1.73 1.30 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 3.60 7.80 10.0 inches 0.068 0.051 0.021 0.015 0.014 0.009 1.25 0.85 0.049 0.033 0.77 0.73 0.26 0.24 0.14 0.31 0.39 DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 www.sycelectronica.com.ar

2003 Jun 25 23

Philips Semiconductors Product speciﬁcation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 X w M q AA 1 A 2 bp D H E Lp Q detail X E Z e c L v M A (A )3 A y pin 1 index UNIT A max. A 1 A 2 A 3 bp cD (1) E (1) (1)eH E LL p QZ ywv q REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 o o 0.25 0.1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 SOT109-1 99-12-27 03-02-19 076E07 MS-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.05 1.05 0.0410.244 0.228 0.028 0.020 0.028 0.0120.01 0.25 0.01 0.0040.039 0.016 0 2.5 5 mm scale SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 www.sycelectronica.com.ar

2003 Jun 25 24

Philips Semiconductors Product speciﬁcation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 UNIT A 1 A 2 A 3 bp cD (1) E (1) eH E LL p QZ ywv q REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 1.257.9 7.6 1.03 0.63 0.9 0.7 1.00 0.55 o o0.130.2 0.1 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. SOT338-1 99-12-27 03-02-19 (1) w M bp D H E E Z e c v M A X A y 1 8 16 9 q AA 1 A 2 Lp Q detail X L (A )3 MO-150 pin 1 index 0 2.5 5 mm scale SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 A max. www.sycelectronica.com.ar

2003 Jun 25 25

Philips Semiconductors Product speciﬁcation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 UNIT A 1 A 2 A 3 bp cD (1) E (2) (1)eH E LL p QZ ywv q REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 o o0.13 0.10.21 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 SOT403-1 MO-153 99-12-27 03-02-18 w M bp D Z e 0.25 16 9 q AA 1 A 2 Lp Q detail X L (A )3 H E E c v M A XA y 0 2.5 5 mm scale TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 A max. 1.1 pin 1 index www.sycelectronica.com.ar

2003 Jun 25 26

Philips Semiconductors Product speciﬁcation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 terminal 1 index area 0.51 A 1 EhbUNIT ye 0.2 c REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 3.6 3.4 D h 2.15 1.85 2.6 2.4 1.15 0.85 2.50.30 0.18 0.05 0.00 0.05 0.1 DIMENSIONS (mm are the original dimensions) 0.5 0.3 L 0.1 v 0.05 w 0 2.5 5 mm scale SOT763-1 DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm A (1) max. A c detail X yy1 Ce L Eh D h e b 15 10 X D E C B A terminal 1 index area AC C Bv M w M E (1) Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. D (1) 02-10-17 03-01-27 www.sycelectronica.com.ar

2003 Jun 25 27

Philips Semiconductors Product speciﬁcation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 DATA SHEET STATUS Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. LEVEL DATA SHEET STATUS (1) PRODUCT STATUS (2)(3) DEFINITION I Objective data Development This data sheet contains data from the objective speciﬁcation for product development. Philips Semiconductors reserves the right to change the speciﬁcation in any manner without notice. II Preliminary data Qualiﬁcation This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN). DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. www.sycelectronica.com.ar

© Koninklijke Philips Electronics N.V. 2003 SCA75 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.sycelectronica.com.ar . Fax: +54 011 4371-5300 For sales ofﬁces addresses send e-mail to:info@sycelectronica.com.ar . Printed in The Netherlands 613508/04/pp28 Date of release:2003 Jun 25 Document order number: 9397 750 11263 www.sycelectronica.com.ar

Product Information

74HC-HCT595 specifications and overview.

Summary

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

Description

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

Source title 74HC-HCT595 Datasheet(PDF) - SYC Electronica

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