74HC-HCT4020 SYC | Alldatasheet

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Product specification File under Integrated Circuits, IC06 September 1993 74HC/HCT4020 14-stage binary ripple counter

Philips Semiconductors Product specification 14-stage binary ripple counter 74HC/HCT4020

FEATURES

  • Output capability: standard
  • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT4020 are high-speed Si-gate CMOS devices and are pin compatible with the “4020” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4020 are 14-stage binary ripple counters with a clock input ( CP), an overriding asynchronous master reset input (MR) and twelve fully buffered parallel outputs (Q 0, Q3 to Q13). The counter is advanced on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. QUICK REFERENCE DATA GND = 0 V; Tamb =2 5°C; tr =tf= 6 ns Notes 1. C PD is used to determine the dynamic power dissipation (PD inµW): PD =C PD × VCC 2 × fi+ ∑ (CL × VCC 2 ×fo) where: fi= input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC 2 × fo) = sum of outputs C L = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI= GND to VCC For HCT the condition is VI= GND to VCC − 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT HC HCT tPHL/ tPLH propagation delay C L = 15 pF; VCC =5 V CP to Q0 11 15 ns Q n to Qn+1 66n s MR to Qn 17 19 ns fmax maximum clock frequency 101 52 MHz C I input capacitance 3.5 3.5 pF C PD power dissipation capacitance per package notes 1 and 2 19 20 pF www.sycelectronica.com.ar

Philips Semiconductors Product specification 14-stage binary ripple counter 74HC/HCT4020 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 9, 7, 5, 4, 6, 13, 12, 14, 15, 1, 2, 3 Q0, Q3 to Q13 parallel outputs

8 GND ground (0 V)

CP clock input (HIGH-to-LOW, edge-triggered)

11 MR master reset input (active HIGH)

CC positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. fpage MGA829 RCTR14 9 CT=0 CT www.sycelectronica.com.ar

Philips Semiconductors Product specification 14-stage binary ripple counter 74HC/HCT4020 Fig.4 Functional diagram. Fig.5 Logic diagram. FUNCTION TABLE Notes 1. H = HIGH voltage level L = LOW voltage level X = don’t care ↑ = LOW-to-HIGH clock transition ↓ = HIGH-to-LOW clock transition INPUTS OUTPUTS CP MR Q 0, Q3 to Q13 X L L H no change count L Fig.6 Timing diagram. www.sycelectronica.com.ar

Philips Semiconductors Product specification 14-stage binary ripple counter 74HC/HCT4020 DC CHARACTERISTICS FOR 74HC For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr =tf= 6 ns; CL = 50 pF SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HC VCC (V) WAVEFORMS +25 −40 to+85 −40 to+125 tPHL / tPLH propagation delay CP to Q0 140 175 210 ns 2.0 4.5 6.0 Fig.7 t PHL / tPLH propagation delay Q n to Qn+1 110 ns 2.0 4.5 6.0 Fig.7 t PHL propagation delay MR to Qn 170 215 225 ns 2.0 4.5 6.0 Fig.8 t THL / tTLH output transition time 19 110 ns 2.0 4.5 6.0 Fig.7 t W clock pulse width HIGH or LOW 100 120 ns 2.0 4.5 6.0 Fig.7 t W master reset pulse width HIGH 100 120 ns 2.0 4.5 6.0 Fig.8 t rem removal time MR to CP ns 2.0 4.5 6.0 Fig.8 f max maximum clock pulse frequency 6.0 109 4.8 4.0 MHz 2.0 4.5 6.0 Fig.7 www.sycelectronica.com.ar

Philips Semiconductors Product specification 14-stage binary ripple counter 74HC/HCT4020 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (ΔICC ) for a unit load of 1 is given in the family specifications. To determineΔICC per input, multiply this value by the unit load coefficient shown in the table below. AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr =tf= 6 ns; CL = 50 pF INPUT UNIT LOAD COEFFICIENT CP MR 0.85 1.10 SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HCT VCC (V) WAVEFORMS +25 −40 to+85 −40 to+125 tPHL / tPLH propagation delay CP to Q0 18 36 45 54 ns 4.5 Fig.7 tPHL / tPLH propagation delay Q n to Qn+1 8 15 19 22 ns 4.5 Fig.7 tPHL propagation delay MR to Qn 22 45 56 68 ns 4.5 Fig.8 tTHL / tTLH output transition time 7 15 19 22 ns 4.5 Fig.7 tW clock pulse width HIGH or LOW 20 7 25 30 ns 4.5 Fig.7 tW master reset pulse width HIGH 20 8 25 30 ns 4.5 Fig.8 trem removal time MR to CP 10 2 13 15 ns 4.5 Fig.8 fmax maximum clock pulse frequency 25 47 20 17 MHz 4.5 Fig.7 www.sycelectronica.com.ar

Philips Semiconductors Product specification 14-stage binary ripple counter 74HC/HCT4020 AC WAVEFORMS PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. Fig.7 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency. (1) HC : VM = 50%; VI= GND to VCC . HCT: VM = 1.3 V; VI= GND to 3 V. Fig.8 Waveforms showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to clock (CP) removal time. (1) HC : VM = 50%; VI= GND to VCC . HCT: VM = 1.3 V; VI= GND to 3 V. www.sycelectronica.com.ar