74HC-HCT374 SYC | Alldatasheet

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Product specification File under Integrated Circuits, IC06 December 1990 74HC/HCT374 Octal D-type flip-flop; positive edge-trigger; 3-state

Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state 74HC/HCT374

FEATURES

  • 3-state non-inverting outputs for bus oriented

applications

  • 8-bit positive, edge-triggered register
  • Common 3-state output enable input
  • Independent register and 3-state buffer operation
  • Output capability: bus driver
  • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT374 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT374 are octal D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock (CP) and an output enable ( OE) input are common to all flip-flops. The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the 8 flip-flops are available at the outputs. WhenOE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The “374” is functionally identical to the “534”, but has non-inverting outputs. QUICK REFERENCE DATA GND = 0 V; Tamb =2 5°C; tr =tf= 6 ns Notes 1. C PD is used to determine the dynamic power dissipation (PD inµW): PD =C PD × VCC 2 × fi+∑ (CL × VCC 2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC 2 × fo) = sum of outputs C L = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI= GND to VCC For HCT the condition is VI= GND to VCC − 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT HC HCT tPHL / tPLH propagation delay CP to Qn C L = 15 pF; VCC = 5 V 15 13 ns fmax maximum clock frequency 77 48 MHz C I input capacitance 3.5 3.5 pF C PD power dissipation capacitance per flip-flop notes 1 and 2 17 17 pF www.sycelectronica.com.ar

Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state 74HC/HCT374 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION

1 OE 3-state output enable input (active LOW)

2, 5, 6, 9, 12, 15, 16, 19 Q 0 to Q7 3-state flip-flop outputs 3, 4, 7, 8, 13, 14, 17, 18 D 0 to D7 data inputs

10 GND ground (0 V)

11 CP clock input (LOW-to-HIGH, edge-triggered)

CC positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. www.sycelectronica.com.ar

Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state 74HC/HCT374 Fig.4 Functional diagram. FUNCTION TABLE Notes 1. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition Z = high impedance OFF-state ↑ = LOW-to-HIGH CP transition OPERATING MODES INPUTS INTERNAL FLIP-FLOPS OUTPUTS OE CP D n Q 0 to Q7 load and read register L L l h L H L H load register and disable outputs H H l h L H Z Z Fig.5 Logic diagram. www.sycelectronica.com.ar

Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state 74HC/HCT374 DC CHARACTERISTICS FOR 74HC For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr =tf= 6 ns; CL =5 0p F SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HC VCC (V) WAVEFORMS +25 −40 to+85 −40 to+125 tPHL / tPLH propagation delay CP to Qn 165 205 250 ns 2.0 4.5 6.0 Fig.6 t PZH / tPZL 3-state output enable time OE to Qn 150 190 225 ns 2.0 4.5 6.0 Fig.7 t PHZ / tPLZ 3-state output disable time OE to Qn 150 190 225 ns 2.0 4.5 6.0 Fig.7 t THL / tTLH output transition time 14 ns 2.0 4.5 6.0 Fig.6 t W clock pulse width HIGH or LOW 100 120 ns 2.0 4.5 6.0 Fig.6 t su set-up time D n to CP ns 2.0 4.5 6.0 Fig.8 t h hold time D n to CP ns 2.0 4.5 6.0 Fig.8 f max maximum clock pulse frequency 6.0 4.8 4.0 MHz 2.0 4.5 6.0 Fig.6 www.sycelectronica.com.ar

Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state 74HC/HCT374 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver ICC category: MSI Note to HCT types The value of additional quiescent supply current (ΔICC ) for a unit load of 1 is given in the family specifications. To determineΔICC per input, multiply this value by the unit load coefficient shown in the table below. AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr =tf= 6 ns; CL =5 0p F INPUT UNIT LOAD COEFFICIENT OE CP D n 1.25 0.90 0.35 SYMBOL PARAMETER T amb (°C) UNIT TEST CONDITIONS 74HCT VCC (V) WAVEFORMS +25 −40 to+85 −40 to+125 tPHL / tPLH propagation delay CP to Qn 16 32 40 48 ns 4.5 Fig.6 tPZH / tPZL 3-state output enable time OE to Qn 16 30 38 45 ns 4.5 Fig.7 tPHZ / tPLZ 3-state output disable time OE to Qn 18 28 35 42 ns 4.5 Fig.7 tTHL / tTLH output transition time 5 12 15 18 ns 4.5 Fig.6 tW clock pulse width HIGH or LOW 19 11 24 29 ns 4.5 Fig.6 tsu set-up time D n to CP 12 7 15 18 ns 4.5 Fig.8 th hold time D n to CP 5 −3 5 5 ns 4.5 Fig.8 fmax maximum clock pulse frequency 26 44 21 17 MHz 4.5 Fig.6 www.sycelectronica.com.ar

Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state 74HC/HCT374 AC WAVEFORMS Fig.6 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, output transition times and the maximum clock pulse frequency. (1) HC : VM = 50%; VI= GND to VCC . HCT : VM = 1.3 V; VI= GND to 3 V. Fig.7 Waveforms showing the 3-state enable and disable times. (1) HC : VM = 50%; VI= GND to VCC . HCT : VM = 1.3 V; VI= GND to 3 V. Fig.8 Waveforms showing the data set-up and hold times for Dn input. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : V M = 50%; VI= GND to VCC . HCT : VM = 1.3 V; VI= GND to 3 V. www.sycelectronica.com.ar

Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state 74HC/HCT374 PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. www.sycelectronica.com.ar