74HC-HCT299 | DigiCamel IC Datasheet

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74HC-HCT299 SYC | Alldatasheet

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Technical content

General description The 74HC299; 74HCT299 are high-speed Si-gate CMOS devices which are pin-compatible with Low-power Schottky TTL (LSTTL) devices. They are speciﬁed in compliance with JEDEC standard no. 7A. The 74HC299; 74HCT299 contain eight edge-triggered D-type ﬂip-ﬂops and the interstage logic necessary to perform synchronous shift-right, shift-left, parallel load and hold operations. An operation is determined by the mode select inputs S0 and S1, as shown in Table3. Pins I/O0 to I/O7 are ﬂip-ﬂop 3-state buffer outputs which allow them to operate as data inputs in parallel load mode. The serial outputs Q0 and Q7 are used for expansion in serial shifting of longer words. A LOW signal on the asynchronous master reset input MR overrides the Sn and clock CP inputs and resets the ﬂip-ﬂops. All other state changes are initiated by the rising edge of the clock pulse. Inputs can change when the clock is in either state, provided that the recommended set-up and hold times are observed. A HIGH signal on the 3-state output enable inputs OE1 orOE2 disables the 3-state buffers and the I/On outputs are set to the high-impedance OFF-state. In this condition, the shift, hold, load and reset operations still occur when preparing for a parallel load operation. The 3-state buffers are also disabled by HIGH signals on both S0 and S1. 2. Features n Multiplexed inputs/outputs provide improved bit density n Four operating modes: u Shift left u Shift right u Hold (store) u Load data n Operates with output enable or at high-impedance OFF-state (Z) n 3-state outputs drive bus lines directly n Cascadable for n-bit word lengths n ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V n Speciﬁed from−40 °C to +85°C and from−40 °C to +125°C 74HC299; 74HCT299 8-bit universal shift register; 3-state Rev. 03 — 28 July 2008 Product data sheet

11 DSR

74HC_HCT299_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 28 July 2008 3 of 24 NXP Semiconductors 74HC299; 74HCT299 8-bit universal shift register; 3-state Fig 2. Logic symbol Fig 3. IEC logic symbol 001aai458 MR OE2 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 CP DSR DSL R SRG8 3EN5 119 C4/1 /2 M 0 312 81, 4D 3, 4D 6, 5 18 2, 4D 7 Z6 17Z7 7, 5 001aai459 3, 4D 3, 4D www.sycelectronica.com.ar

74HC_HCT299_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 28 July 2008 4 of 24 NXP Semiconductors 74HC299; 74HCT299 8-bit universal shift register; 3-state Fig 4. Logic diagram 001aai461 D Q CP RD FF0 D Q CP RD FF1 D Q CP RD FF2 D Q CP RD FF3 D Q CP RD FF4 D Q CP RD FF5 D Q CP RD FF6 D Q CP RD FF7 DSR I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CP OE1 OE2 MR DSL www.sycelectronica.com.ar

5.1 Pinning

5.2 Pin description

Table 2. Pin description

74HC_HCT299_3 © NXP B.V. 2008. All rights reserved. [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. Table 2. Pin description …continued Table 3. Function table[1] HL H ↑ shift right; DSR→ Q0, Q0 → Q1, etc. HHL ↑ shift left; DSL→ Q7, Q7→ Q6, etc. In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Recommended operating conditions

Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

74HC_HCT299_3 © NXP B.V. 2008. All rights reserved. [1] C PD is used to determine the dynamic power dissipation (PD inµW). At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

74HC_HCT299_3 © NXP B.V. 2008. All rights reserved. [1] tpd is the same as tPHL and tPLH . [2] tpd is the same as tPHL . [3] tt is the same as tTHL and tTLH . [4] ten is the same as tPZH and tPZL . [5] tdis is the same as tPHZ and tPLZ . GND (ground = 0 V); for test circuit, seeFigure11.

74HC_HCT299_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 28 July 2008 14 of 24 NXP Semiconductors 74HC299; 74HCT299 8-bit universal shift register; 3-state [6] C PD is used to determine the dynamic power dissipation (PD inµW). PD = CPD × VCC 2 × fi× N + Σ(CL × VCC 2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; Σ(CL × VCC 2 × fo) = sum of outputs; C L = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching. 11. Waveforms The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given inTable8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Clock pulse to outputs I/On, Q0, Q7 propagation delays, the clock pulse width, the I/On, DSR and DSL to clock pulse set-up and hold times, the output transition times and the maximum clock frequency 001aai462 th tsu th tPHL tTHL tTLH tW tPLH tsu 1/fmax VM VM VM CP input VI GND VI GND VOH VOL I/On, DSR, DSL inputs I/On, Q0, Q7 outputs www.sycelectronica.com.ar

74HC_HCT299_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 28 July 2008 15 of 24 NXP Semiconductors 74HC299; 74HCT299 8-bit universal shift register; 3-state Measurement points are given inTable8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. The master reset pulse width (LOW), the master reset to outputs I/On, Q0, Q7 propagation delays and the master reset to clock pulse removal time 001aai463 I/On, Q0, Q7 outputs VM tPHL VM MR input VM GND GND VI tW trec CP input VOL VI VOH Measurement points are given inTable8. Fig 9. Set-up and hold times from the mode control inputs S0, S1 to the clock pulse 001aai464 I/On, DSR, DSL, Sn inputs CP input tsu th VM VI GND GND VI VM tsu th www.sycelectronica.com.ar

74HC_HCT299_3 © NXP B.V. 2008. All rights reserved. Measurement points are given inTable8. VOL and VOH are typical voltage output levels that occur with the output load. Table 8. Measurement points Test data is given inTable9. T = Termination resistance should be equal to output impedance Zo of the pulse generator. C L = Load capacitance including jig and probe capacitance.

74HC_HCT299_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 28 July 2008 18 of 24 NXP Semiconductors 74HC299; 74HCT299 8-bit universal shift register; 3-state 12. Package outline Fig 12. Package outline SOT163-1 (SO20) UNIT A max. A 1 A 2 A 3 bp cD (1) E (1) (1)eH E LL p Q Zywv q REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm inches 2.65 0.3 0.1 2.45 2.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 o o 0.25 0.1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 SOT163-1 w M bp detail X Z e D y 0.25 075E04 MS-013 pin 1 index 0.1 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.51 0.49 0.30 0.29 0.05 1.4 0.0550.419 0.394 0.043 0.039 0.035 0.0160.01 0.25 0.01 0.0040.043 0.0160.01 0 5 10 mm scale X q AA 1 A 2 H E Lp Q E c L v M A (A )3 A SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 99-12-27 03-02-19 www.sycelectronica.com.ar

74HC_HCT299_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 28 July 2008 19 of 24 NXP Semiconductors 74HC299; 74HCT299 8-bit universal shift register; 3-state Fig 13. Package outline SOT339-1 (SSOP20) UNIT A 1 A 2 A 3 bp cD (1) E (1) eH E LL p Q (1)Zywv q REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.21 0.05 1.80 1.65 0.38 0.25 0.20 0.09 7.4 7.0 5.4 5.2 0.65 7.9 7.6 0.9 0.7 0.9 0.5 o o0.131.25 0.2 0.1 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. 1.03 0.63 SOT339-1 MO-150 99-12-27 03-02-19 X w M q A A 1 A 2 bp D H E Lp Q detail X E Z e c L v M A (A )3 A 11 0 20 11 y 0.25 pin 1 index 0 2.5 5 mm scale SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1 A max. www.sycelectronica.com.ar

74HC_HCT299_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 28 July 2008 20 of 24 NXP Semiconductors 74HC299; 74HCT299 8-bit universal shift register; 3-state Fig 14. Package outline SOT146-1 (DIP20) UNIT A max. 1 2 b1 cD E e M HL REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm inches DIMENSIONS (inch dimensions are derived from the original mm dimensions) SOT146-1 99-12-27 03-02-13 A min. A max. b Z max.wM Ee1 1.73 1.30 0.53 0.38 0.36 0.23 26.92 26.54 6.40 6.22 3.60 7.80 10.0 8.3 24.2 0.51 3.2 0.068 0.051 0.021 0.015 0.014 0.009 1.060 1.045 0.25 0.24 0.14 0.31 0.39 SC-603MS-001 M H c (e )1 M E A L seating plane w M e D A 2 Z b E pin 1 index 0 5 10 mm scale Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. (1)(1) (1) DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1 www.sycelectronica.com.ar

74HC_HCT299_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 28 July 2008 21 of 24 NXP Semiconductors 74HC299; 74HCT299 8-bit universal shift register; 3-state Fig 15. Package outline SOT360-1 (TSSOP20) UNIT A 1 A 2 A 3 bp cD (1) E (2) (1)eH E LL p QZ ywv q REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.5 0.2 o o0.13 0.10.21 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 SOT360-1 MO-153 99-12-27 03-02-19 w M bp D Z e 0.25 11 0 20 11 pin 1 index q AA 1 A 2 Lp Q detail X L (A )3 H E E c v M A XA y 0 2.5 5 mm scale TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 A max. 1.1 www.sycelectronica.com.ar

The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
Section3: Ordering information added
Section12: Package outline drawings added
Section 9 “Static characteristics”: Family data added
Section 11 “Waveforms”: Test circuit added 74HC_HCT299_CNV_2 19970828 Product speciﬁcation - - www.sycelectronica.com.ar

74HC_HCT299_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 28 July 2008 23 of 24 NXP Semiconductors 74HC299; 74HCT299 8-bit universal shift register; 3-state 14. Legal information

14.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Deﬁnitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

14.2 Deﬁnitions

Draft —The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modiﬁcations or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet —A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the full data sheet shall prevail.

14.3 Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes —NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation speciﬁcations and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use —NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications —Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the speciﬁed use without further testing or modiﬁcation. Limiting values —Stress above one or more limiting values (as deﬁned in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale —NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/proﬁle/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conﬂict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license —Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

14.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 15. Contact information For more information, please visit:http://www.sycelectronica.com.ar For sales ofﬁce addresses, please send an email to:info @sycelectronica.com.ar Document status[1][2] Product status[3] Deﬁnition Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development. Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation. Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors 74HC299; 74HCT299 8-bit universal shift register; 3-state 16. Contents www.sycelectronica.com.ar

Product Information

74HC-HCT299 specifications and overview.

Summary

8-bit universal shift register; 3-state July 2008

Description

8-bit universal shift register; 3-state July 2008

Source title 74HC-HCT299 Datasheet(PDF) - SYC Electronica

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