74HC-HCT20 SYC | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 6

Technical content

Product specification File under Integrated Circuits, IC06 December 1990 74HC/HCT20 Dual 4-input NAND gate For a complete data sheet, please also download:

  • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
  • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
  • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

Philips Semiconductors Product specification Dual 4-input NAND gate 74HC/HCT20

FEATURES

  • Output capability: standard
  • ICC category: SSI GENERAL DESCRIPTION The 74HC/HCT20 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT20 provide the 4-input NAND function. QUICK REFERENCE DATA GND = 0 V; Tamb =2 5°C; tr =tf=6n s Notes 1. C PD is used to determine the dynamic power dissipation (PD inµW): PD =C PD × VCC 2 × fi+ ∑ (CL × VCC 2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz C L = output load capacitance in pF VCC = supply voltage in V ∑ (CL × VCC 2 × fo) = sum of outputs 2. For HC the condition is VI= GND to VCC For HCT the condition is VI= GND to VCC − 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT HC HCT tPHL / tPLH propagation delay nA, nB, nC, nD to nY CL = 15 pF; VCC = 5 V 8 13 ns C I input capacitance 3.5 3.5 pF C PD power dissipation capacitance per package notes 1 and 2 22 17 pF

Philips Semiconductors Product specification Dual 4-input NAND gate 74HC/HCT20 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 9 1A, 2A data inputs 2, 10 1B, 2B data inputs 3, 11 n.c. not connected 4, 12 1C, 2C data inputs 5, 13 1D, 2D data inputs 6, 8 1Y, 2Y data outputs

7 GND ground (0 V)

CC positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

Philips Semiconductors Product specification Dual 4-input NAND gate 74HC/HCT20 Fig.4 Functional diagram. Fig.5 HC logic diagram (one gate). Fig.6 HCT logic diagram (one gate). FUNCTION TABLE Notes 1. H = HIGH voltage level L = LOW voltage level X = don’t care INPUTS OUTPUT nA nB nC nD nY L X X X H X L X X H X X L X H X X X L H H H H H L

Philips Semiconductors Product specification Dual 4-input NAND gate 74HC/HCT20 DC CHARACTERISTICS FOR 74HC For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: SSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr =tf= 6 ns; CL =5 0p F SYMBOL PARAMETER Tamb (°C) TEST CONDITIONS 74HC UNIT V CC (V) WAVEFORMS+25 −40 to +85 −40 to +125 tPHL / tPLH propagation delay nA, nB, nC, nD to nY 115 135 ns 2.0 4.5 6.0 Fig.7 t THL / tTLH output transition time 19 110 ns 2.0 4.5 6.0 Fig.7

Philips Semiconductors Product specification Dual 4-input NAND gate 74HC/HCT20 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: SSI Note to HCT types The value of additional quiescent supply current (ΔICC ) for a unit load of 1 is given in the family specifications. To determineΔICC per input, multiply this value by the unit load coefficient shown in the table below. AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr =tf= 6 ns; CL =5 0p F AC WAVEFORMS PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. INPUT UNIT LOAD COEFFICIENT nA, nB, nC, nD 0.3 SYMBOL PARAMETER Tamb (°C) TEST CONDITIONS 74HCT UNIT V CC (V) WAVEFORMS+25 −40 to +85 −40 to +125 tPHL / tPLH propagation delay nA, nB, nC, nD to nY 16 28 35 42 ns 4.5 Fig.7 tTHL / tTLH output transition time 7 15 19 22 ns 4.5 Fig.7 Fig.7 Waveforms showing the enable input (nA, nB, nC, nD) to output (nY) propagation delays and the output transition times. (1) HC : VM = 50%; VI= GND to VCC . HCT: VM = 1.3 V; VI= GND to 3 V.