74HC-HCT193 | DigiCamel IC Datasheet

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74HC-HCT193 SYC | Alldatasheet

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Technical content

General description The 74HC193 and 74HCT193 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are speciﬁed in compliance with JEDEC standard no. 7A. The 74HC193 and 74HCT193 are 4-bit synchronous binary up/down counters. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD is held HIGH, the device will count up. If the CPD clock is pulsed while CPU is held HIGH, the device will count down. Only one clock input can be held HIGH at any time, or erroneous operation will result. The device can be cleared at any time by the asynchronous master reset input (MR); it may also be loaded in parallel by activating the asynchronous parallel load input ( PL). The 74HC193 and 74HCT193 each contain four master-slave JK ﬂip-ﬂops with the necessary steering logic to provide the asynchronous reset, load, and synchronous count up and count down functions. Each ﬂip-ﬂop contains JK feedback from slave to master, such that a LOW-to-HIGH transition on the CPD input will decrease the count by one, while a similar transition on the CPU input will advance the count by one. One clock should be held HIGH while counting with the other, otherwise the circuit will either count by twos or not at all, depending on the state of the ﬁrst ﬂip-ﬂop, which cannot toggle as long as either clock input is LOW. Applications requiring reversible operation must make the reversing decision while the activating clock is HIGH to avoid erroneous counts. The terminal count up ( TCU) and terminal count down (TCD) outputs are normally HIGH. When the circuit has reached the maximum count state of 15, the next HIGH-to-LOW transition of CPU will cause TCU to go LOW. TCU will stay LOW until CPU goes HIGH again, duplicating the count up clock. Likewise, theTCD output will go LOW when the circuit is in the zero state and the CPD goes LOW. The terminal count outputs can be used as the clock input signals to the next higher order circuit in a multistage counter, since they duplicate the clock waveforms. Multistage counters will not be fully synchronous, since there is a slight delay time difference added for each stage that is added. The counter may be preset by the asynchronous parallel load capability of the circuit. Information present on the parallel data inputs (D0 to D3) is loaded into the counter and appears on the outputs (Q0 to Q3) regardless of the conditions of the clock inputs when the parallel load ( PL) input is LOW. A HIGH level on the master reset (MR) input will disable the parallel load gates, override both clock inputs and set all outputs (Q0 to 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter Rev. 03 — 23 May 2007 Product data sheet

74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 3 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter Fig 3. IEC logic symbol CTR4 2CT = 0 1CT = 15 001aag410 4 G1 11 C3 14 R

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5.1 Pinning

5.2 Pin description

[1] LOW-to-HIGH, edge triggered. Table 2. Pin description

74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 7 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter (1) Clear overrides load, data and count inputs. (2) When counting up, the count down clock input (CPD) must be HIGH, when counting down the count up clock input (CPU) must be HIGH. Sequence Clear (reset outputs to zero); load (preset) to binary thirteen; count up to fourteen, ﬁfteen, terminal count up, zero, one and two; count down to one, zero, terminal count down, ﬁfteen, fourteen and thirteen. Fig 8. Typical clear, load and count sequence 001aag411 COUNT UP COUNT DOWN 01 3 CLEAR PRESET 1 0 15 14 1314 15 0 1 2 MR (1) PL CPU (2) CPD (2) TCU TCD

74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For DIP16 packages: above 70°C the value of Ptotderates linearly at 12 mW/K. For SO16 packages: above 70°C the value of Ptotderates linearly at 8 mW/K. For SSOP16 and TSSOP16 packages: above 60°C the value of Ptotderates linearly at 5.5 mW/K.

Recommended operating conditions

Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Table 5. Recommended operating conditions

74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Table 5. Recommended operating conditions …continued Table 6. Static characteristics type 74HC193 At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

1.5 V; VCC =5V ;

Table 9. Dynamic characteristics type 74HCT193 …continued

74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 18 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter 11. Waveforms Measurement points are given inTable10. tPLH and tPHL are the same as tpd. Logic levels VOL and VOH are typical output voltage drops that occur with the output load. Fig 9. The clock (CPU, CPD) to output (Qn) propagation delays, the clock pulse width, and the maximum clock pulse frequency 001aag413 CPU, CPD input VI GND VOH VOL Qn output tPHL tPLH tW VM VM 1/fmax Measurement points are given inTable10. tPLH and tPHL are the same as tpd. Logic levels VOL and VOH are typical output voltage drops that occur with the output load. Fig 10. The clock (CPU, CPD) to terminal count output (TCU, TCD) propagation delays 001aag414 CPU, CPD input TCU, TCD output tPHL VI GND VOH VOL tPLH VM VM

74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 19 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter Measurement points are given inTable10. tPLH and tPHL are the same as tpd. Logic levels VOL and VOH are typical output voltage drops that occur with the output load. Fig 11. The parallel load input (PL) and data (Dn) to Qn output propagation delays andPL removal time to clock input (CPU, CPD) 001aag415 Dn input VI GND VI GND VI GND VOH VOL Qn output CPU, CPD input PL input V M VM VM VM tW trec tPLH tPHL Measurement points are given inTable10. tPLH and tPHL are the same as tpd. Logic levels VOL and VOH are typical output voltage drops that occur with the output load. Fig 12. The master reset input (MR) pulse width, MR to Qn propagation delays, MR to CPU, CPD removal time and output transition times 001aag416 MR input Qn output VOH VOL VI GND VI GND CPU, CPD input VM VM VM 10 % 90 % trec tPHL tTHL tW tTLH

74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 20 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given inTable10. Logic levels VOL and VOH are typical output voltage drops that occur with the output load. Fig 13. The data input (Dn) to parallel load input (PL) set-up and hold times 001aag417 Dn input Qn output VOL VOH GND VI GND VI PL input VM tsu th VM tsu th Measurement points are given inTable10. tPLH and tPHL are the same as tpd. Logic levels VOL and VOH are typical output voltage drops that occur with the output load. Fig 14. The data input (Dn), parallel load input (PL) and the master reset input (MR) to the terminal count outputs (TCU, TCD) propagation delays 001aag418 PL, MR, Dn input TCU, TCD output tPLH tPHL VM VM VOL VOH GND VI Measurement points are given inTable10. Fig 15. The CPU to CPD or CPD to CPU hold times 001aag419 CPD or CPU input CPU or CPD input VI GND VI GND VM VM th

74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 22 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter 12. Application information Fig 17. Application for cascaded up/down counter with parallel load 001aag420 data input IC1 IC2 data output up clock down clock carry borrow asynchronous parallel load reset D0 D1 D2 D3 Q0 Q1 Q2 Q3 TCU TCD MR CPU CPD PL D0 D1 D2 D3 Q0 Q1 Q2 Q3 TCU TCD MR CPU CPD PL

74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 23 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter 13. Package outline Fig 18. Package outline SOT109-1 (SO16) X w M q AA 1 A 2 bp D H E Lp Q detail X E Z e c L v M A (A )3 A y pin 1 index UNIT A max. A 1 A 2 A 3 bp cD (1) E (1) (1)eH E LL p QZ ywv q REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 o o 0.25 0.1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 SOT109-1 99-12-27 03-02-19 076E07 MS-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.05 1.05 0.0410.244 0.228 0.028 0.020 0.028 0.0120.01 0.25 0.01 0.0040.039 0.016 0 2.5 5 mm scale SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 24 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter Fig 19. Package outline SOT338-1 (SSOP16) UNIT A 1 A 2 A 3 bp cD (1) E (1) eH E LL p QZ ywv q REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 1.257.9 7.6 1.03 0.63 0.9 0.7 1.00 0.55 o o0.130.2 0.1 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. SOT338-1 99-12-27 03-02-19 (1) w M bp D H E E Z e c v M A X A y 1 8 16 9 q AA 1 A 2 Lp Q detail X L (A )3 MO-150 pin 1 index 0 2.5 5 mm scale SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 A max.

74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 25 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter Fig 20. Package outline SOT38-4 (DIP16) REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA SOT38-4 95-01-14 03-02-13 M H c (e )1 M E A L seating plane w M e D A 2 Z E pin 1 index b 0 5 10 mm scale Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. UNIT A max. 12 b1 (1) (1) (1) b2 cD E e M ZHL mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) A min. A max. b max.wM Ee1 1.73 1.30 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 3.60 7.80 10.0 inches 0.068 0.051 0.021 0.015 0.014 0.009 1.25 0.85 0.049 0.033 0.77 0.73 0.26 0.24 0.14 0.31 0.39 DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4

74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 26 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter Fig 21. Package outline SOT403-1 (TSSOP16) UNIT A 1 A 2 A 3 bp cD (1) E (2) (1)eH E LL p QZ ywv q REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 o o0.13 0.10.21 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 SOT403-1 MO-153 99-12-27 03-02-18 w M bp D Z e 0.25 16 9 q AA 1 A 2 Lp Q detail X L (A )3 H E E c v M A XA y 0 2.5 5 mm scale TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 A max. 1.1 pin 1 index

The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
Family speciﬁcation included 74HC_HCT193_CNV_2 19970828 Product speciﬁcation - -

74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 28 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter 15. Legal information 16. Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Deﬁnitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

16.1 Deﬁnitions

Draft —The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modiﬁcations or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet —A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the full data sheet shall prevail.

16.2 Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes —NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation speciﬁcations and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use —NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications —Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the speciﬁed use without further testing or modiﬁcation. Limiting values —Stress above one or more limiting values (as deﬁned in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale —NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/proﬁle/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conﬂict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license —Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

16.3 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For sales ofﬁce addresses, send an email to: info@sycelectronica.com.ar Document status[1][2] Product status[3] Deﬁnition Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development. Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation. Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter 18. Contents

Product Information

74HC-HCT193 specifications and overview.

Summary

Presettable synchronous 4-bit binary up/down counter May 2007

Description

Presettable synchronous 4-bit binary up/down counter May 2007

Source title 74HC-HCT193 Datasheet(PDF) - SYC Electronica

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