74HC-HCT00 SYC | Alldatasheet
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Technical content
standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL). The 74HC00; 74HCT00 provides a quad 2-input NAND function. Table 1. Ordering information
74HC_HCT00_4 © NXP B.V. 2010. All rights reserved.
5.1 Pinning
5.2 Pin description
Table 2. Pin description
74HC_HCT00_4 © NXP B.V. 2010. All rights reserved. [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For DIP14 package: P tot derates linearly with 12 mW/K above 70 °C. For SO14 package: Ptot derates linearly with 8 mW/K above 70 °C. For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 °C. For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 °C.
- Recommended operating conditions
Table 3. Function table [1] Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Table 5. Recommended operating conditions
74HC_HCT00_4 © NXP B.V. 2010. All rights reserved. Table 5. Recommended operating conditions …continued Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
74HC_HCT00_4 © NXP B.V. 2010. All rights reserved. Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Table 7. Dynamic characteristics GND = 0 V; CL = 50 pF; for load circuit see Figure 7.
74HC_HCT00_4 © NXP B.V. 2010. All rights reserved. [1] t pd is the same as tPHL and tPLH. [2] t t is the same as tTHL and tTLH. ∑ (CL × VCC2 × fo) = sum of outputs. GND = 0 V; CL = 50 pF; for load circuit see Figure 7. Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Table 8. Measurement points
74HC_HCT00_4 © NXP B.V. 2010. All rights reserved. Test data is given in Table 9. RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. Table 9. Test data
74HC_HCT00_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 11 January 2010 8 of 15 NXP Semiconductors 74HC00; 74HCT00 Quad 2-input NAND gate 12. Package outline Fig 8. Package outline SOT27-1 (DIP14) UNIT A max. 1 2 (1) (1)b1 cD (1)ZEe M HL REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm inches DIMENSIONS (inch dimensions are derived from the original mm dimensions) SOT27-1 99-12-27 03-02-13 A min. A max. b max.wMEe1 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 3.60 7.80 10.0 0.068 0.044 0.021 0.015 0.77 0.73 0.014 0.009 0.26 0.24 0.14 0.31 0.39 050G04 MO-001 SC-501-14 MH c (e )1 ME A L seating plane w M e D Z b E pin 1 index 0 5 10 mm scale Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HC_HCT00_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 11 January 2010 9 of 15 NXP Semiconductors 74HC00; 74HCT00 Quad 2-input NAND gate Fig 9. Package outline SOT108-1 (SO14) UNIT A max. A1 A2 A3 bp cD (1) E(1) (1)eH E LL p QZ ywv θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 o o 0.25 0.1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 SOT108-1 X w M θ AA1 bp D HE Lp Q detail X E Z e c L v M A (A )3 A y 076E06 MS-012 pin 1 index 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.35 0.34 0.16 0.15 0.05 1.05 0.0410.244 0.228 0.028 0.024 0.028 0.0120.01 0.25 0.01 0.0040.039 0.016 99-12-27 03-02-19 0 2.5 5 mm scale SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
74HC_HCT00_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 11 January 2010 10 of 15 NXP Semiconductors 74HC00; 74HCT00 Quad 2-input NAND gate Fig 10. Package outline SOT337-1 (SSOP14) UNIT A 1 A2 A3 bp cD (1) E (1) eH E LL p QZ ywv θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 7.6 1.03 0.63 0.9 0.7 1.4 0.9 o o0.13 0.1 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. SOT337-1 99-12-27 03-02-19 (1) w M bp D HE E Z e c v M A X A y 1 7 14 8 θ AA1 Lp Q detail X L (A )3 MO-150 pin 1 index 0 2.5 5 mm scale SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 A max.
74HC_HCT00_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 11 January 2010 11 of 15 NXP Semiconductors 74HC00; 74HCT00 Quad 2-input NAND gate Fig 11. Package outline SOT402-1 (TSSOP14) UNIT A 1 A2 A3 bp cD (1) E (2) (1)eH E LL p QZ ywv θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.72 0.38 o o0.13 0.10.21 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 SOT402-1 MO-153 99-12-27 03-02-18 w M bp D Z e 0.25 14 8 θ AA1 Lp Q detail X L (A )3 HE E c v M A XA y 0 2.5 5 mm scale TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 A max. 1.1 pin 1 index
74HC_HCT00_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 11 January 2010 12 of 15 NXP Semiconductors 74HC00; 74HCT00 Quad 2-input NAND gate Fig 12. Package outline SOT762-1 (DHVQFN14) terminal 1 index area 0.51 A1 EhbUNIT ye 0.2 c REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 3.1 2.9 Dh 1.65 1.35 2.6 2.4 1.15 0.85 20.30 0.18 0.05 0.00 0.05 0.1 DIMENSIONS (mm are the original dimensions) 0.5 0.3 L 0.1 v 0.05 w 0 2.5 5 mm scale SOT762-1 DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm A(1) max. A c detail X yy1 Ce L Eh Dh e b 13 9 X D E C B A 02-10-17 03-01-27 terminal 1 index area AC C Bv M w M E(1) Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. D(1)
74HC_HCT00_4 © NXP B.V. 2010. All rights reserved. Table 10. Abbreviations Table 11. Revision history
- Legal texts have been adapted to the new company name where appropriate. 74HC_HCT00_3 20030630 Product data sheet - 74HC_HCT00_CNV_2 74HC_HCT00_CNV_2 19970826 Product specification - -
74HC_HCT00_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 11 January 2010 14 of 15 NXP Semiconductors 74HC00; 74HCT00 Quad 2-input NAND gate 15. Legal information
15.1 Data sheet status
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15.2 Definitions
Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
15.3 Disclaimers
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15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For sales office addresses, please send an email to: info@sycelectronica.com.ar Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
NXP Semiconductors 74HC00; 74HCT00 Quad 2-input NAND gate 17. Contents