681000

681000 SYC | Alldatasheet

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128K x8 bit Low Power CMOS Static RAM The KM681000B family is fabricated by SAMSUNG's advanced CMOS process technology. The family can support various operating temperature ranges and have various package types for user flexibility of system design. The family also support low data retention voltage for battery back-up operation with low data retention current. GENERAL DESCRIPTIONFEATURES ¡Ü Process Technology : 0.6§­ CMOS ¡Ü Organization : 128Kx8 ¡Ü Power Supply Voltage : Single 5.0V ¡¾ 10% ¡Ü Low Data Retention Voltage : 2V(Min) ¡Ü Three state output and TTL Compatible ¡Ü Package Type : JEDEC Standard 32-DIP, 32-SOP, 32-TSOP I R/F PIN DESCRIPTION Name Function A0~A16 Address Inputs WE Write Enable Input CS1,CS2 Chip Select Inputs OE Output Enable Input I/O1~I/O18 Data Inputs/Outputs Vcc Power Vss Ground N.C No Connection X-Decoder Cell Array PRODUCT FAMILY Product Family Operating Temperature Speed PKG Type Power Dissipation Standby (ISB1, Max) Operating (ICC2) KM681000BL Commercial(0~7¡É) 55/70ns 32-DIP,32-SOP 32-TSOP I R/F 100§Ë 70mA KM681000BL-L 20§Ë KM681000BLE Extended(-25~85¡É) 70/100ns 32-SOP 32-TSOP I R/F 100§Ë KM681000BLE-L 50§Ë KM681000BLI Industrial(-40~85¡É) 70/100ns 32-SOP 32-TSOP I R/F 100§Ë KM681000BLI-L 50§Ë Control Logic Y-Decoder I/O Buffer FUNCTIONAL BLOCK DIAGRAM A0~3, A8~11 A4~7, I/O1~8 32-TSOP Type I-Reverse A12~16 CS1,CS2 WE,OE A11 A13 WE CS2 A15 VCC NC A16 A14 A12 OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 32-TSOP Type I - Forward N.C A16 A14 A12 I/O1 I/O2 I/O3 VSS VCC A15 CS2 WE A13 A11 OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 32-DIP 32-SOP A11 A13 WE CS2 A15 VCC NC A16 A14 A12 OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 681000ALP-70

PRODUCT LIST & ORDERING INFORMATION PRODUCT LIST Commercial Temp Product (0~70¡É) Extended Temp Products (-25~85¡É) Industrial Temp Products (-40~85¡É) Part Name Function Part Name Function Part Name Function KM681000BLP-5 KM681000BLP-5L KM681000BLP-7 KM681000BLP-7L KM681000BLG-5 KM681000BLG-5L KM681000BLG-7 KM681000BLG-7L KM681000BLT-5 KM681000BLT-5L KM681000BLT-7 KM681000BLT-7L KM681000BLR-5 KM681000BLR-5L KM681000BLR-7 KM681000BLR-7L 32-DIP,55ns,L-pwr 32-DIP,55ns,LL-pwr 32-DIP,70ns,L-pwr 32-DIP,70ns,LL-pwr 32-SOP,55ns,L-pwr 32-SOP,55ns,LL-pwr 32-SOP,70ns,L-pwr 32-SOP,70ns,LL-pwr 32-TSOP F,55ns,L-pwr 32-TSOP F,55ns,LL-pwr 32-TSOP F,70ns,L-pwr 32-TSOP F,70ns,LL-pwr 32-TSOP R,55ns,L-pwr 32-TSOP R,55ns,LL-pwr 32-TSOP R,70ns,L-pwr 32-TSOP R,70ns,LL-pwr KM681000BLGE-7 KM681000BLGE-7L KM681000BLGE-10 KM681000BLGE-10L KM681000BLTE-7 KM681000BLTE-7L KM681000BLTE-10 KM681000BLTE-10L KM681000BLRE-7 KM681000BLRE-7L KM681000BLRE-10 KM681000BLRE-10L 32-SOP,70ns,L-pwr 32-SOP,70ns,LL-pwr 32-SOP,100ns,L-pwr 32-SOP,100ns,LL-pwr 32-TSOP F,70ns,L-pwr 32-TSOP F,70ns,LL-pwr 32-TSOP F,100ns,L-pwr 32-TSOP F,100ns,LL-pwr 32-TSOP R,70ns,L-pwr 32-TSOP R,70ns,LL-pwr 32-TSOP R,100ns,L-pwr 32-TSOP R,100ns,LL-pwr KM681000BLGI-7 KM681000BLGI-7L KM681000BLGI-10 KM681000BLGI-10L KM681000BLTI-7 KM681000BLTI-7L KM681000BLTI-10 KM681000BLTI-10L KM681000BLRI-7 KM681000BLRI-7L KM681000BLRI-10 KM681000BLRI-10L 32-SOP,70ns,L-pwr 32-SOP,70ns,LL-pwr 32-SOP,100ns,L-pwr 32-SOP,100ns,LL-pwr 32-TSOP F,70ns,L-pwr 32-TSOP F,70ns,LL-pwr 32-TSOP F,100ns,L-pwr 32-TSOP F,100ns,LL-pwr 32-TSOP R,70ns,L-pwr 32-TSOP R,70ns,LL-pwr 32-TSOP R,100ns,L-pwr 32-TSOP R,100ns,LL-pwr

ABSOLUTE MAXIMUM RATINGS* * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Item Symbol Ratings Unit Remark Voltage on any pin relative to Vss VIN,VOUT -0.5 to 7.0 V - Voltage on Vcc supply relative to Vss VCC -0.5 to 7.0 V - Power Dissipation PD 1.0 W - Storage temperature TSTG -65 to 150 ¡É - Operating Temperature TA 0 to 70 ¡É KM681000BL/L-L -25 to 85 ¡É KM681000BLE/LE-L -40 to 85 ¡É KM681000BLI/LI-L Soldering temperature and time TSOLDER 260¡É, 10sec (Lead Only) - - RECOMMENDED DC OPERATING CONDITIONS* * 1) Commercial Product : TA=0 to 70¡É, unless otherwise specified 2) Extended Product : TA=-25 to 85¡É, unless otherwise specified 3) Industrial Product : TA=-40 to 85¡É, unless otherwise specified TA=25¡É * VIL(min)=-3.0V for ¡Â 50ns pulse width Item Symbol Min Typ Max Unit Supply voltage Vcc 4.5 5.0 5.5 V Ground Vss 0 0 0 V Input high voltage VIH 2.2 - Vcc+0.5 V Input low voltage VIL -0.5* - 0.8 V CAPACITANCE* (f=1MHz, TA=25¡É) * Capacitance is sampled not 100% tested Item Symbol Test Condition Min Max Unit Input capacitance CIN Vin=0V - 6 pF Input/Output capacitance CIO Vio=0V - 8 pF

DC AND OPERATING CHARACTERISTICS * 1) Commercial Product : TA=0 to 70¡É, Vcc=5.0V¡¾10%, unless otherwise specified 2) Extended Product : TA=-25 to 85¡É, Vcc=5.0V¡¾10%, unless otherwise specified 2) Industrial Product : TA=-40 to 85¡É, Vcc=5.0V¡¾10%, unless otherwise specified 20mA for Exteneded and Industrial Products * 15mA for Extended and Industrial Products Item Symbol Test Conditions* Mi Typ Max Unit Input leakage current ILI VIN=Vss to Vcc -1 - 1 §Ë Output leakage current ILO CS1=VIH or CS2=VIL or WE=VIL, VIO=Vss to Vcc -1 - 1 §Ë Operating power supply current ICC CS1=VIL, CS2=VIH, VIN=VIH or VIL, IIO=0mA - 7 15 mA Average operating current ICC1 Cycle time=1§Á 100% duty CS1¡Â0.2V, CS2¡ÃVCC-0.2V - - 10*** mA ICC2 IIO=0mA CS1=VIL,CS2=VIH Min cycle, 100% duty - - 70 mA Output low voltage VOL IOL=2.1mA - - 0.4 V Output high voltage VOH IOH=-1.0mA 2.4 - - V Standby Current(TTL) ISB CS1=VIH, CS2=VIL - - 3 mA Standby Current (CMOS) KM681000BL KM681000BL-L ISB1 CS1¡ÃVcc-0.2V CS2¡ÃVcc-0.2V or CS2¡Â0.2V Other input=0~Vcc L (Low Power) LL (Low Low Power) 100 KM681000BLE KM681000BLE-L L (Low Power) LL (Low Low Power) 100 KM681000BLI KM681000BLI-L L (Low Power) LL (Low Low Power) 100 TEST CONDITIONS (1.Test Load and Test Input/Output Reference)* * See DC Operating conditions Item Value Remark Input pulse level 0.8 to 2.4V - Input rising & falling time 5ns - input and output reference voltage 1.5V - Output load (See right) CL=100pF+1TTL - A.C CHARACTERISTICS CL* * Including scope and jig capacitance

TEST CONDITIONS (2. Temperature and Vcc Conditions) Product Family Temperature Power Supply(Vcc) Speed Bin Comments KM681000BL/L-L 0~70¡É 5.0V¡¾10% 55/70ns Commercial KM681000BLE/LE-L -25~85¡É 5.0V¡¾10% 70/100ns Extended KM681000BLI/LI-L -40~85¡É 5.0V¡¾10% 70/100ns Industrial PARAMETER LIST FOR EACH SPEED BIN Parameter List Symbol Speed Bins Units55ns 70ns 100ns Min Max Min Max Min Max Read Read cycle time tRC 55 - 70 - 100 - ns Address access time tAA - 55 - 70 - 100 ns Chip select to output tCO1,tCO2 - 55 - 70 - 100 ns Output enable to valid output tOE - 25 - 35 - 50 ns Chip select to low-Z output tLZ1,tLZ2 10 - 10 - 10 - ns Output enable to low-Z output tOLZ 5 - 5 - 5 - ns Chip disable to high-Z output tHZ1,tHZ2 0 20 0 25 0 30 ns Output disable to high-Z output tOHZ 0 20 0 25 0 30 ns Output hold from address change tOH 10 - 10 - 10 - ns Write Write cycle time tWC 55 - 70 - 100 - ns Chip select to end of write tCW 45 - 60 - 80 - ns Address set-up time tAS 0 - 0 - 0 - ns Address valid to end of write tAW 45 - 60 - 80 - ns Write pulse width tWP 40 - 50 - 60 - ns Write recovery time tWR 0 - 0 - 0 - ns Write to output high-Z tWHZ 0 20 0 25 0 30 ns Data to write time overlap tDW 25 - 30 - 40 - ns Data hold from write time tDH 0 - 0 - 0 - ns End write to output low-Z tOW 5 - 5 - 5 - ns

DATA RETENTION CHARACTERISTICS * 1) Commercial Product : TA=0 to 70¡É, unless otherwise specified 2) Extended Product : TA=-25 to 85¡É, unless otherwise specified 2) Industrial Product : TA=-40 to 85¡É, unless otherwise specified TA=25¡É * CS1¡ÃVCC-0.2V,CS2¡ÃVCC-0.2V(CS1 controlled) or CS2¡Â0.2V(CS2 controlled) Item Symbol Test Condition* Min Typ Max Unit Vcc for data retention VDR CS1*¡ÃVcc-0.2V 2.0 - 5.5 V Data retention current IDR KM681000BL KM681000BL-L Vcc=3.0V CS1¡ÃVcc-0.2V L-Ver LL-Ver 0.5 §ËKM681000BLE KM681000BLE-L L-Ver LL-Ver KM681000BLI KM681000BLI-L L-Ver LL-Ver Data retention set-up time tRDR See data retention waveform 0 - - ms Recovery time tRDR 5 - - VCC 0.4V VDR CS2 GND Data Retention Mode CS2 ¡Â 0.2V 2) CS2 controlled 4.5V DATA RETENTION TIMING DIAGRAM VCC 4.5V 2.2V VDR CS1 GND Data Retention Mode CS1¡Ã VCC - 0.2V 1) CS1 Controlled tSDR tRDR tSDR tRDR

Data Out Previous Data Valid Data Valid TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE (1) (Address Controlled) (CS1=OE=VIL, CS2= WE= VIH) TIMING WAVEFORM OF READ CYCLE (WE=VIH) Data ValidHigh-Z CS1 Address CS2 OE Data out NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(max.) is less than tLZ(min.) both for a given device and from device to device. tRC tOH tOH tAA tOLZ tLZ tOHZ tHZ(1,2) tCO1 tAA tRC tCO2 tOE

TIMING WAVEFORM OF WRITE CYCLE (1) (WE Controlled) TIMING WAVEFORM OF WRITE CYCLE (2) (CS1 Controlled) Address CS1 Data Valid CS2 WE Data in Data out High-Z High-Z Address CS1 Data Undefined Data Valid CS2 WE Data in Data out tWC tCW(2) tWR1(4) tAW tCW(2) tWP(1) tAS(3) tDW tDH tOWtWHZ tCW(2) tWR1(4) tAW tWP(1) tDW tDH tAS(3) tWC

TIMING WAVEFORM OF WRITE CYCLE (2) (CS2 Controlled) NOTES (WRITE CYCLE) 1. A write occurs during the overlap of low CS1, high CS2 and low WE. A write begins at the latest transition among CS1 going low, CS2 going high and WE going low. A write ends at the earliest transition among CS1 going high, CS2 going low and WE going high, tWP is measured from the beginning or write to the end of write. 2. tCW is measured from the later of CS1 going low or CS2 going high to the end of write. 3. tAS is measured from the address calid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR1 applied in case a write ends at CS1, or WE going high, tWR2 applied in case a write ends at CS2 going to low. FUNCTIONAL DESCRIPTION * X means don't care CS1 CS2 WE OE Mode I/O Pin Current Mode H X X X Power Down High-Z ISB,ISB1 X L X X Power Down High-Z ISB,ISB1 L H H H Output Disable High-Z ICC L H H L Read Dout ICC L H L X Write Din ICC tWC tCW(2) tWR2(4) tAW tWP(1) tDW tDH tAS(3) tCW(2)

PACKAGE DIMENSIONS Units :MillimeterS(Inches) 0~15¡É 1.91

32 DUAL INLINE PACKAGE (600mil)

#32 13.60 ¡¾ 0.20 0.535 ¡¾ 0.008 4.191 ¡¾ 0.20 1.650 ¡¾ 0.008 ( )0.075 15.24 0.600 +0.10 MAX42.31 1.666 0.25 -0.05 +0.0040.010 -0.002 2.54 0.100 MAX 3.81 ¡¾ 0.20 0.150 ¡¾ 0.008 5.08 0.200 MIN0.015 0.38 0.130 ¡¾ 0.012 3.30 ¡¾ 0.30 #16 #17 1.52 ¡¾ 0.10 0.060 ¡¾ 0.004 0.46 ¡¾ 0.10 0.018 ¡¾ 0.004

32 PLASTIC SMALL OUTLINE PACKAGE (525mil)

0~8¡É #32 20.47 ¡¾ 0.20 0.806 ¡¾ 0.008 MAX20.87 0.822 MAX 2.74 ¡¾ 0.20 0.108 ¡¾ 0.008 3.00 0.118 MIN0.002 0.05

0.004 MAX

0.10 MAX

0.71( )0.028 13.34 0.525 11.43 ¡¾ 0.20 0.450 ¡¾ 0.008 0.80 ¡¾ 0.20 0.031 ¡¾ 0.008 +0.100.20 -0.05 +0.0040.008 -0.002 14.12 ¡¾ 0.30 0.556 ¡¾ 0.012 #17 #16 1.27 0.050 +0.1000.41 -0.050 +0.0040.016 -0.002

32 THIN SMALL OUTLINE PACKAGE TYPE I (0820F)

#32 1.00 ¡¾ 0.10 0.039 ¡¾ 0.004 MAX8.40 0.331

1.10 MAX

0.50( )0.020 18.40 ¡¾ 0.10 0.724 ¡¾ 0.004 0.45 ~0.75 0.018 ~0.030 20.00 ¡¾ 0.20 0.787 ¡¾ 0.008 #17 +0.100.15 -0.05 +0.0040.006 -0.002 0~8¡É +0.100.20 -0.05 +0.0040.008 -0.002 0.50 0.0197 0.25( )0.010 MIN0.05 0.002 MAX1.20 0.047 8.00 0.315 TYP0.25 0.010 #16 PACKAGE DIMENSIONS Units :MillimeterS(Inches)

32 THIN SMALL OUTLINE PACKAGE TYPE I (0820R)

#32 1.00 ¡¾ 0.10 0.039 ¡¾ 0.004 MAX8.40 0.331 0.50( )0.020 18.40 ¡¾ 0.10 0.724 ¡¾ 0.004 0.45 ~0.75 0.018 ~0.030 20.00 ¡¾ 0.20 0.787 ¡¾ 0.008 #17 +0.100.15 -0.05 +0.0040.006 -0.002 0~8¡É +0.100.20 -0.05 +0.0040.008 -0.002 0.50 0.0197 0.25( )0.010 MIN0.05 0.002 MAX1.20 0.047 8.00 0.315 TYP0.25 0.010 #16