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Technical content
Features
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Description
The Si590/591 XO utilizes Silicon Laboratories’ advanced DSPLL® circuitry to provide a low jitter clock at high frequencies. The Si590/591 is available with any-rate output frequency from 10 to 525 MHz. Unlike a traditional XO, where a unique crystal is required for each output frequency, the Si590/591 uses one fixed crystal to provide a wide range of output frequencies. This IC based approach allows the crystal resonator to provide exceptional frequency stability and reliability. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low jitter clocks in noisy environments typically found in communication systems. The Si590/591 IC based XO is factory configurable for a wide variety of user specifications including frequency, supply voltage, output format, and temperature stability. Specific configurations are factory programmed at time of shipment, thereby eliminating long lead times associated with custom oscillators. Functional Block Diagram Available with any-rate output frequencies from 10 MHz to 525 MHz 3rd generation DSPLL® with superior jitter performance: 1 ps max jitter Better frequency stability than SAW- based oscillators Internal fundamental mode crystal ensures high reliability Available CMOS, LVPECL, LVDS, and CML outputs 3.3, 2.5, and 1.8 V supply options Industry-standard 5 x 7 mm package and pinout Pb-free/RoHS-compliant –40 to +85 ºC operating temperature range SONET/SDH (OC-3/12/48) Networking SD/HD SDI/3G SDI video Test and measurement Storage FPGA/ASIC clock generation Fixed Frequency XO Any-rate 10–525 MHz DSPLL® Clock Synthesis VDD CLK+CLK– GND OE 17 k * 17 k * *Note: Output Enable High/Low Options Available – See Ordering Information Ordering Information: See page 6. Pin Assignments: See page 5. (Top View) Si5602 4GND OE VDD CLK+ CLK– NC 4GND NC VDD CLK NC OE 4GND NC VDD CLK+ CLK– OE Si590 (LVDS/LVPECL/CML) Si590 (CMOS) Si591 (LVDS/LVPECL/CML)
- Electrical Specifications
Table 1. Recommended Operating Conditions
- Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 6 for further details.
- OE pin includes an internal 17 k pullup resistor to VDD for output enable active high or a 17 k pull-down resistor to
GND for output enable active low. See 3. "Ordering Information" on page 6. Table 2. CLK± Output Frequency Characteristics
- See Section 3. "Ordering Information" on page 6 for further details.
- Specified at time of order by part number.
- Includes initial accuracy, temperature, shock, vibration, power supply and load drift, and 10 years aging at 40 °C. See
- "Ordering Information" on page 6.
- Includes initial accuracy, temperature, shock, vibration, power supply and load drift, and 15 years aging at 70 °C. See
- "Ordering Information" on page 6.
- Time from powerup or tristate mode to fO.
Table 3. CLK± Output Levels and Symmetry
- Rterm = 100 (differential).
Table 4. CLK± Output Phase Jitter
- Single-ended CMOS output phase jitter measured using 33 series termination into 50 phase noise test equipment.
3.3 V supply voltage option only. Table 5. CLK± Output Period Jitter *Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
Table 6. Absolute Maximum Ratings1
2 TPEAK 260 ºC
- Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional
extended periods may affect device reliability.
- The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at
www.silabs.com/VCXO for further information, including soldering profiles. Table 7. Environmental Compliance The Si590/591 meets the following qualification test requirements.
Table 8. Pinout for Si590 Series
4 CLK+ Oscillator Output Oscillator Output
5 CLK– Complementary Output No connection
GND for output enable active low. See 3. "Ordering Information" on page 6. Table 9. Pinout for Si591 Series
1 OE* Output enable
2 No connection
4 CLK+ Oscillator Output
5 CLK– Complementary output
GND for output enable active low. See 3. "Ordering Information" on page 6.
The Si590/591 XO supports a variety of options including frequency, temperature stability, output format, and VDD. Figure 1. Part Number Convention assigned for the specific frequency. range operation and is shipped in tape and reel format.
- Si590/Si591 Mark Specification
Figure 3 illustrates the mark specification for the Si590/Si591. Table 11 lists the line information. Figure 3. Mark Specification Table 11. Si53x Top Mark Description
3 Trace Code
Preliminary Rev. 0.25 10 DOCUMENT CHANGE LIST Revision 0.2 to Revision 0.25 Total Stability Maximum changed to ±30 in Table 2 on page 2. Total Stability Maximum changed to ±30 in Figure 1 on page 6.
Preliminary Rev. 0.25 11 NOTES:
12 Preliminary Rev. 0.25 CONTACT INFORMATION Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse- quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per- sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.