SI552 SILABS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 8
Technical content
Features
Applications
Description
The Si552 dual frequency VCXO utilizes Silicon Laboratories advanced DSPLL® circuitry to provide a very low jitter clock for all output frequencies. The Si552 is available with any-rate output frequency from 10 to 945 MHz and selected frequencies to 1400 MHz. Unlike traditional VCXO’s where a different crystal is required for each output frequency, the Si552 uses one fixed crystal frequency to provide a wide range of output frequencies. This IC based approach allows the crystal resonator to be optimized for superior frequency stability and reliability. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low jitter clocks in noisy environments often found in communication systems. The Si552 IC based VCXO is factory configurable for a wide variety of user specifications including frequency, supply voltage and output format. Specific configurations are factory programmed into the Si552 at time of shipment, thereby eliminating the long lead times associated with custom oscillators. Functional Block Diagram Available with any-rate output frequencies from 10 to 945 MHz and selected frequencies to 1.4 GHz Two selectable output frequencies Industry-standard 7x5 mm package Available CMOS, LVPECL, LVDS & CML outputs 3x better frequency stability than SAW-based oscillators 3rd generation DSPLL® with superior jitter performance Internal fixed crystal frequency ensures high reliability and low aging Lead-free/RoHS-compliant SONET / SDH xDSL 10 GbE LAN / WAN Low jitter clock generation Optical Modules Test and Measurement Fixed Frequency XO Any-rate 10–1400 MHz DSPLL™ Clock Synthesis VDD CLK+CLK- VC GNDFS ADC Ordering Information: See page 7. Si5602 PRELIMINARY D ATA S HEET
- Electrical Specifications
Table 1. Si552 Electrical Specifications Specified at time of order by P/N.
500 MHz
3.3 V option
2.5 V option
1.8 V option
Table 2. Absolute Maximum Ratings Table 1. Si552 Electrical Specifications (Continued)
Table 3. Environmental Conditions Table 4. Pinout
1 Vc Control Voltage
2 FS Frequency Select
3 Gnd Ground
4 Output Oscilla tor Output
5 Coutput
Preliminary Rev. 0.2 7 4. Ordering Information The Si552 was designed to support a variety of options in cluding frequency, tuning slope, output format, and VDD. Specific device configurations are programmed into the Si552 at time of ship ment. A unique part number associated with these options and freq uencies will be assigned. The Si552 D ual Frequency VCXO is provided in an industry-standard, 7x5 package. Part numbers for the Si552 Dual Frequency VCXO ar e determined by following conf iguration tables. Silicon Labs provides a Windows-based part number configuration tool to simplify this process. Refer to www.silabs.com/VCXO to access this tool and for further ordering instructions. 2nd Option Code (VCXO) Temp Stability Tuning Sl ope (ppm, max, ± ) (Kv,ppm/V, typ,) APR(typ)@3.3V APR(typ )@2.5V APR(typ)@1.8V A 100 180 185 115 50 B 100 90 38 Note 3 Note 3 C 50 180 235 165 100 D 50 90 85 50 20 E 20 45 40 25 Note 3 Notes: 1. Pull range (±) = 0.5 x V DD x tuning slope. 2. Absolute Pull Range ( ±APR) = Pull range – stability – lifetime aging = 0.5xV DD x tuning slope – stab ility – 10 ppm 3. Combination not available. APR is the ability of a VCXO to track a signal over the product lifetime . Thus, a VCXO with an APR of 50 ppm is able to lock to a clock with 50 ppm stability, for a 15 year life.
552 X X
A 3.3 LVPECL B 3.3 LVDS C 3.3 CMOS D 3.3 CML E 2.5 LVPECL F 2.5 LVDS G 2.5 CMOS H 2.5 CML J 1.8 CMOS K 1.8 CML Notes CMOS available to 160 MHz. B X R Tape & Reel Packaging Operating Temp Range (°C) G -40 to +85°C Part Revision Letter
552 VCXO
Two unique frequencies can be specified within the following bands of frequencies: 10 to 945 MHz 970 to 1134 MHz 1213 to 1417 MHz A six digit code will be assigned by SiLabs for the specified combination of frequencies . X X X X X X
8 Preliminary Rev. 0.2 CONTACT INFORMATION Silicon Laboratories Inc.
4635 Boston Lane
Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: VCXOinfo@silabs.com Internet: www.silabs.com Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse- quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per- sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.