SI534 SILABS | Alldatasheet

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The Si534 quad frequency XO utilizes Silicon Laboratories’ advanced DSPLL® circuitry to provide a low jitter clock at high frequencies. The Si534 is available with any-rate output frequency from 10 to 945 MHz and select frequencies to 1400 MHz. Unlike a traditional XO where a different crystal is required for each output frequency, the Si534 uses one fixed crystal to provide a wide range of output frequencies. This IC based approach allows the crystal resonator to provide exceptional frequency stability and reliability. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low jitter clocks in noisy environments typically found in communication systems. The Si534 IC-based XO is factory configurable for a wide variety of user specifications including frequency, supply voltage, output format, and temperature stability. Specific configurations are factory programmed at time of shipment, thereby eliminating long lead times associated with custom oscillators. Functional Block Diagram „ Available with any-rate output frequencies from 10 MHz to 945 MHz and select frequencies to 1.4 GHz „ Four selectable output frequencies „ 3rd generation DSPLL® with superior jitter performance „ 3x better frequency stability than SAW-based oscillators „ Internal fixed crystal frequency ensures high reliability and low aging „ Available CMOS, LVPECL, LVDS, and CML outputs „ 3.3, 2.5, and 1.8 V supply options „ Industry-standard 5 x 7 mm package and pinout „ Pb-free/RoHS-compliant „ SONET/SDH „ Networking „ SD/HD video „ Clock and data recovery „ FPGA/ASIC clock generation Fixed Frequency XO Any-rate 10–1400 MHz DSPLL® Clock Synthesis VDD CLK+CLK– OE GND FS[1] FS[0] Ordering Information: See page 6. Pin Assignments: See page 5. (Top View) Si5602 (LVDS/LVPECL/CML) (CMOS) 4GND OE VDD CLK+ CLK– NC FS[1] FS[0] 4GND OE VDD CLK NC NC FS[1] FS[0] PRELIMINARY D ATA S HEET

  1. Electrical Specifications

Table 1. Recommended Operating Conditions

  1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 6 for further details.
  2. OE pin includes a 17 kΩ pullup resistor to VDD. Pulling OE to ground causes outputs to tristate.

Table 2. CLK± Output Frequency Characteristics

  1. See Section 3. "Ordering Information" on page 6 for further details.
  2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
  3. Selectable parameter specified by part number.
  4. Time from powerup or tristate mode to fO.

Table 3. CLK± Output Levels and Symmetry

  1. Rterm = 100 Ω (differential).

Table 4. CLK± Output Phase Jitter *Note: Differential Modes: LVPECL/LVDS/CML. Refer to AN256 for further information. Table 5. CLK± Output Period Jitter *Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles.

Table 6. CLK± Output Phase Noise (Typical)

81.25 MHz

312.5 MHz

1066 MHz

10 MHz

100 MHz

Table 7. Absolute Maximum Ratings1

2 TPEAK 260 ºC

  1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional

operation or specification compliance is not implied at these conditions.

  1. Refer to Si5xx Packaging FAQ available for download at www.silabs.com/VCXO for further information, including

Table 8. Environmental Compliance The Si534 meets the following qualification test requirements.

Table 9. Pin Descriptions

1 NC No connection No connection

4 CLK+ Oscillator Output Oscillator Output

5 CLK– Complementary output No connection

7 FS[1]* Frequency Select MSB Frequency Select MSB

8 FS[0]* Frequency Select LSB Frequency Select LSB

compliant, 6-pad, 5 x 7 mm package. Figure 1. Part Number Convention 000100, f0 is 644.53125 MHz (lower frequency) and f1 is 693.48299 (higher frequency), with a 3.3 V supply and LVPECL output. shipped in tape and reel format.

534 Quad XO

534 X X XXXXXX B G R

Preliminary Rev. 0.4 9 DOCUMENT CHANGE LIST Revision 0.3 to Revision 0.4 „ Updated 1. "Electrical Specifications" on page 2. z Updated ordering and format of Tables 1–9. z Updated LVDS and CML in Table 3, “CLK± Output Levels and Symmetry,” on page 3. „ Added Table 6, “CLK± Output Phase Noise (Typical),” on page 4.

10 Preliminary Rev. 0.4 CONTACT INFORMATION Silicon Laboratories Inc.

4635 Boston Lane

Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: VCXOinfo@silabs.com Internet: www.silabs.com Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse- quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per- sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.