SI550 SILABS | Alldatasheet
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The Si550 VCXO utilizes Silicon Laboratories’ advanced DSPLL® circuitry to provide a low-jitter clock at high fre quencies. The Si550 is available with any-rate output frequency from 10 to 945 MHz and selected frequencies to 1400 MHz. Unlike traditional VCXO’s where a different crystal is required for each output frequency, the Si550 uses one fixed crystal to provide a wide range of output frequencies. This IC based approach allows the crystal resonator to provide exceptional frequency stability and reliability. In addition, DSPLL clock synthesis provid es superior supply noise rejection, simplifying the task of generating low-jitter clocks in noisy environments typically found in communication systems. The Si550 IC-based VCXO is factory configurable for a wide variety of user specifications, including frequency, supply voltage, output format, tuning slope, and temperature stability. Specific configurations are factory programmed at time of shipment, thereby eliminating long lead times associated with custom oscillators. Functional Block Diagram Available with any-rate output frequencies from 10 MHz to
945 MHz and selected frequencies
to 1.4 GHz 3rd generation DSPLL® with superior jitter performance 3x better frequency stability than SAW based oscillators Internal fixed crystal frequency ensures high reliability and low aging Available CMOS, LVPECL, LVDS, & CML outputs 3.3, 2.5, and 1.8 V supply options Industry-standard 5 x 7 mm package and pinout Lead-free/RoHS-compliant SONET / SDH xDSL 10 GbE LAN / WAN Low-jitter clock generation Optical modules Clock and data recovery Fixed Frequency XO Any-rate 10-1400 MHz DSPLL ® Clock Synthesis ADC VDD CLK+CLK– Vc OE GND Ordering Information: See page 8. Pin Assignments: See page 7. (Top View) Si5602 VC GND OE VDD CLK+ CLK– PRELIMINARY D ATA S HEET
- Electrical Specifications
Table 1. Recommended Operating Conditions
- Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 8 for further details.
- OE pin includes a 17 kΩ pullup resistor to VDD. Pulling OE to ground causes outputs to tristate.
Table 2. VC Control Voltage Input
- Positive slope; selectable option by part number. See Section 3. "Ordering Information" on page 8.
- For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
- KV variation is ±28% of typical values.
- BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope
determined with VC ranging from 10 to 90% of VDD.
Table 3. CLK± Output Frequency Characteristics
- See Section 3. "Ordering Information" on page 8 for further details.
- Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
- Nominal output frequency set by VCNOM =3 / 8xV DD.
- Selectable parameter specified by part number.
- Time from power up or tristate mode to fO.
Table 4. CLK± Output Levels and Symmetry
- Rterm = 100 Ω (differential).
Table 5. CLK± Output Phase Jitter
- Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.
- For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
- See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
rejection (PSR) advantage of Si55x versus SAW-based solutions. Table 4. CLK± Output Levels and Symmetry (Continued)
Table 6. CLK± Output Period Jitter *Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Table 7. CLK± Output Phase Noise (Typical)
74.25 MHz
300 MHz
622.08 MHz
10 MHz
100 MHz
Table 8. Absolute Maximum Ratings operation or specification compliance is not implied at these conditions. Table 9. Environmental Compliance The Si550 meets the following qualification test requirements.
Table 10. Si550 Pin Descriptions
1 VC Analog Input Control Voltage
2 OE* Input
3 GND Ground Electrical and Case Ground
4 CLK+ Output Oscillator Output
5 CLK–
6 VDD Power Power Supply Voltage
*Note: OE includes 17 kΩ pullup resistor to VDD.
8 Preliminary Rev. 0.3 3. Ordering Information The Si550 was designed to support a variety of options including frequency , temperature stabilit y, tuning slope, output format, and V DD. Specific device configurations are prog rammed into the Si550 at time of shipment. Configurations are specified using the Part Number Configuration chart shown below. Silicon Labs provides a web browser-based part number configuration utility to simplify this process. Refer to www.silabs.com/ VCXOPartNumber to access this tool and for further or dering instructions. The Si550 VCXO series is supplied in an industry-standard, RoHS compliant, lead-free, 6- pad, 5 x 7 mm package. Tape and reel packaging is an ordering option. Example Part Number: 550AF622M080BGR is a 5 x 7 mm VCXO in a 6 pad package. The nominal frequency is 622.080 MHz, with a 3.3 V supply and LVPECL output. Temperature stability is specified as ±50 ppm and the tuning slope is 135 ppm/V. The part is specified for a –40 to +85 C° ambient temperature range operation and is shipped in tape and reel format. DD R = Tape & Reel Blank = Trays Operating Temp Range (°C) G –40 to +85 °C Device Revision Letter 2nd Option Code Temperature Tuning Slope Minimum APR Stability Kv (±ppm) Code ± ppm (max) ppm/V (typ) @ 3.3 V @ 2.5 V @ 1.8 V A 100 180 100 75 25 B 100 90 30 Note 6 Note 6 C 50 180 150 125 75 D5 0 9 0 8 0 3 0 2 5 E 20 45 25 Note 6 Note 6 F 50 135 100 75 50 Notes: 1. For best jitter and phase noise performance, always choose the smallest Kv that meets the application’s minimum APR requirements. Unlike SAW-based solutions which require higher higher Kv values to account for their higher temperature dependence, the Si55x series provides lower Kv options to minimize noise coupling and jitter in real-world PLL designs. See AN255 and AN266 for more information. 2. APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO with an APR of ±25 ppm is able to lock to a clock with a ±25 ppm stability, over 15 years. 3. Nominal Pull range (±) = 0.5 x V DD x tuning slope. 4. Nominal Absolute Pull Range (±APR) = Pull range – stability – lifetime aging = 0.5 x VDD x tuning slope – stability – 10 ppm 5. Minimum APR values noted above include worst case values for all parameters. 6. Combination not available.
550 VCXO
A3 . 3 L V P E C L B3 . 3 L V D S C3 . 3 C M O S D3 . 3 C M L E2 . 5 L V P E C L F2 . 5 L V D S G2 . 5 C M O S H2 . 5 C M L J1 . 8 C M O S K1 . 8 C M L Notes: CMOS available to 160 MHz. Frequency (e.g. 622M080 is 622.080 MHz) Available frequency range is 10 to 945 MHz, 970 to 1134, and 1213 to 1417 MHz. The position of “M” shifts to denote higher or lower frequencies.
550 X X XXXMXXX B G R
Preliminary Rev. 0.3 11 DOCUMENT CHANGE LIST Revision 0.2 to Revision 0.3 Updated 1. "Electrical Specifications" on page 2. z Updated ordering and format of Table 1 through Table 9. z Updated LVDS and CML in Table 4, “CLK± Output Levels and Symmetry,” on page 3. z Updated RMS jitter values in Table 5, “CLK± Output Phase Jitter,” on page 4. z Added Typical Phase Noise performance data in Table 5, “CLK± Output Phase Jitter,” on page 4. Updated 3. "Ordering Information" on page 8. z Removed ordering option E at VDD = 2.5 V in table for the 2nd Option Code. z Typical APRs replaced with minimum APR values. z New 135 ppm/V KV option included.
12 Preliminary Rev. 0.3 CONTACT INFORMATION Silicon Laboratories Inc.
4635 Boston Lane
Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: VCXOinfo@silabs.com Internet: www.silabs.com Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse- quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per- sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.