5256V LATTICE | Alldatasheet
Document overview
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Technical content
Features
- SuperWIDE HIGH-DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 3.3V Power Supply — User Selectable 3.3V/2.5V I/O — 12000 PLD Gates / 256 Macrocells — Up to 192 I/O Pins — 256 Registers — High-Speed Global Interconnect — SuperWIDE 32 Generic Logic Block (GLB) Size for Optimum Performance — SuperWIDE Input Gating (68 Inputs) for Fast Counters, State Machines, Address Decoders, etc. — PCB Efficient Ball Grid Array (BGA) Package Options
- HIGH PERFORMANCE E 2CMOS ® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency — tpd = 7.5 ns Propagation Delay — TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels — Electrically Erasable and Reprogrammable — Non-Volatile — Programmable Speed/Power Logic Path Optimization
- IN-SYSTEM PROGRAMMABLE — Increased Manufacturing Yields, Reduced Time-to- Market, and Improved Product Quality — Reprogram Soldered Devices for Faster Debugging
- 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND 3.3V IN-SYSTEM PROGRAMMABLE
- ARCHITECTURE FEATURES — Enhanced Pin-Locking Architecture with Single- Level Global Routing Pool and SuperWide GLBs — Wrap Around Product Term Sharing Array Supports up to 35 Product Terms Per Macrocell — Macrocells Support Concurrent Combinatorial and Registered Functions — Macrocell Registers Feature Multiple Control Options Including Set, Reset and Clock Enable — Four Dedicated Clock Input Pins Plus Macrocell Product Term Clocks — Slew and Skew Programmable I/O (SASPI/O™) Supports Programmable Bus Hold, Pull-up, Open Drain and Slew and Skew Rate Options — Six Global Output Enable Terms, Two Global OE Pins and One Product Term OE per Macrocell
- ispDesignEXPERT™ – LOGIC COMPILER AND COM- PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Functional Block Diagram Global Routing Pool (GRP) Boundary Scan Interface Input Bus Generic Logic Block Input Bus Input Bus Input Bus Generic Logic Block Generic Logic Block Generic Logic Block Input Bus Generic Logic Block Input Bus Generic Logic Block Input Bus Input Bus Generic Logic Block Generic Logic Block ispLSI 5000V Description The ispLSI 5000V Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routing Pool (GRP) between the GLBs. Switching resources are pro- vided to allow signals in the Global Routing Pool to drive any or all the GLBs in the device. This mechanism allows fast, efficient connections across the entire device. Each GLB contains 32 macrocells and a fully populated, programmable AND-array with 160 logic product terms and 5 extra control product terms. The GLB has 68 inputs from the Global Routing Pool which are available in both true and complement form for every product term. The 160 product terms are grouped in 32 sets of five and sent into a Product Term Sharing Array (PTSA) which allows
Figure 1. ispLSI 5256V Functional Block Diagram (272 BGA Option)
- CLK2, CLK3 and TOE signals are multiplexed with I/O signals. Which I/O is multiplexed is
determined by the package type used – see table below.
208 PQFP I/O 89 / CLK2 I/O 98 / CLK3 I/O 0 / TOE
208 BGA I/O 89 / CLK2 I/O 98 / CLK3 I/O 0 / TOE
272 BGA I/O 119 / CLK2 I/O 131 / CLK3 I/O 0 / TOE
reset, clock, clock enable and output enable. macrocell allows efficient use of the hardware resources. type register, a D-type latch or a T-type flip flop. output and one line from each I/O pin. until the bus is driven again by some device. supported through the same interface. execute a bulk-erase instruction. 512 macrocells and operates from a 3.3V power supply. Table 1. ispLSI 5000V Family
Figure 2. ispLSI 5256V Block Diagram (192 I/O Version)
Figure 3. ispLSI 5000V Generic Logic Block (GLB)
Figure 4. ispLSI 5000V Macrocell
Figure 5. ispLSI 5000V Global Clock Structure
Figure 8. Boundary Scan Waveforms and Timing Specifications
Specifications ispLSI 5256V Absolute Maximum Ratings 1, 2 Max. Junction Temp. (T J) with Power Applied ... 150°C 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). 2. Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement. DC Recommended Operating Condition SYMBOL Table 2 - 0005/5256 VCC VCCIO PARAMETER Supply Voltage I/O Reference Voltage Commercial TA = 0°C to +70°C MIN. MAX. UNITS 3.00 2.3 3.60 3.60 V Industrial TA = -40°C to +85°C 3.00 3.60 V V Capacitance (TA =25°C,f=1.0 MHz) SYMBOL Table 2 - 0006/5384 C PARAMETER Clock Capacitance 10 UNITSTYPICAL TEST CONDITIONS 2 pf V = 3.3V, V = 2.0VCC CK C I/O Capacitance 101 pf V = 3.3V, V = 2.0VCC I/O C Global Input Capacitance 103 pf V = 3.3V, V = 2.0VCC G Erase Reprogram Specification Table 2-0008/3320 PARAMETER Data Retention MINIMUM MAXIMUM UNITS ispLSI Erase/Reprogram Cycles 10000 Years Cycles
- Typical values are at VCC = 3.3V and TA = 25°C.
Figure 9. Test Load *C L includes Test Fixture and Probe Capacitance.
Specifications ispLSI 5256V Over Recommended Operating Conditions SYMBOL 1. Typical values are at VCC = 3.3V and TA = 25°C. 2. Pullup is capable of pulling to a minimum voltage of VOH under no-load conditions. DC Char_5256V IPU IBHL PARAMETER IBHH IBHLO
2 I/O Active Pullup Current
Bus Hold Low Sustaining Current Bus Hold High Sustaining Current Bus Hold Low Overdrive Current IIH IIL Input or I/O High Leakage Current Input or I/O Low Leakage Current 0V ≤ V ≤ V (Max.)IN IL CONDITION MIN. TYP. MAX. UNITS -40 -10 -150 550 µA µA µA µA µA µA IBHLH IBHT Bus Hold High Overdrive Current Bus Hold Trip Points VIL -550 V IH µA V IVCCIO Current Needed for VCCIO Pin All I/Os Pulled-up, (Total I/Os * IPUmax ) –– 30 mA µA (VCCIO -0.2)V ≤ VIN ≤ VCCIO VCCIO ≤ VIN ≤ 5.25V 0V ≤ VIN ≤ VIL 0V ≤ VIN ≤ VCCIO 0V ≤ VIN ≤ VCCIO VIN ≥ VIL(max) VIN ≤ VIH(min) Over Recommended Operating Conditions VIH SYMBOL 2.5V/5000 VOH PARAMETER Input High Voltage Output High Voltage VOH(min) ≤ VOUT or VOUT ≤ VOL(max) VOH(min) ≤ VOUT or VOUT ≤ VOL(max) VCCIO=min , VIN=VIH or VIL, IOH = -2mA VCCIO=min , VIN=VIH or VIL, IOL = 2mA CONDITION MIN. TYP. MAX. UNITS 1.7 1.7 5.25 V VCCIO VIL I/O Reference Voltage Input Low Voltage 2.3 -0.3 2.7 0.7 V V V VCCIO=min , VIN=VIH or VIL, IOH = -100µA 2.1 –– V –– 0.7 V VCCIO=min , VIN=VIH or VIL, IOL = 100µA –– 0.2 V VOL Output Low Voltage
Specifications ispLSI 5256V External Switching Characteristics Over Recommended Operating Conditions .MARAP TSET 3 .DNOC #N OITPIRCSED 5,4 521-0 01-0 7- STINU t 1dp A1 s sapyBTP5,yaleD.porPataD — 5.7 — 01 — 51s n t 2dp A2 y aleDnoitagaporPataD — 5.9 — 31 — 91s n f xam A3 k cabdeeFlanretnIhtiwycneuqerFkcolC 1 521 — 001 — 07 — zHM f ).goT(xam — 5e lggoTxaM,ycneuqerFkcolC 2 761 — 521 — 38 — zHM t 1us — 6s sapybTP5,klCerofebemiTputeS.geRBLG6 — 8 — 21 — sn t 1oc A7 y aleDtuptuOotkcolC.geRBLG — 4 — 5.5 — 8s n t 1h — 8s sapybTP5,kcolCretfaemiTdloH.geRBLG0 — 0 — 0 — sn t 2us — 9k colCerofebemiTputeS.geRBLG5 .7 — 01 — 51 — sn t 2h — 01k colCretfaemiTdloH.geRBLG0 — 0 — 0 — sn t 3us — 11 .geRtupnI,kcolCerofebemiTputeS.geRBLG htaP 6 — 8 — 21 — sn t 3h — 21h taP.geRtupnI,kcolCretfaemiTdloH.geRBLG0 — 0 — 0 — sn t1r A3 1y aleDtuptuOotniPteseR.txE — 51 — 02 — 03s n t 1wr — 41n oitaruDesluPteseR.txE7 — 9 — 41 — sn t sid/eotp C/B5 1e lbasiD/elbanEtuptuOmreTtcudorPlacoL — 9 — 21 — 81s n t sid/eotpg C/B6 1e lbasiD/elbanEtuptuOmreTtcudorPlabolG — 81 — 42 — 03s n t sid/eog C/B7 1e lbasiD/elbanEtuptuOottupnIEOlabolG — 6 — 8 — 21s n t hw — 81h giH,noitaruDesluPkcolC.cnyS.txE3 — 4 — 6 — sn t lw — 91w oL,noitaruDesluPkcolC.cnyS.txE3 — 4 — 6 — sn .kcabdeefPRGgnisuretnuoctib-23dradnatS.1 .%05nahtrehtofoelcycytudkcolcarofwollaotsisihT.)lwt+hwt(/1nahtsselebyam)elggoT(xamf.2 .noitcessnoitidnoCtseTgnihctiwSecnerefeR.3 .0KLCdna,BLG1fodaolPRGa,tuonafASTPesactsrowhtiwnekaterasrebmungnimitlla,esiwrehtodetonsselnU.4 .revirdtuptuoevitcalamrongnisuderusaemsretemarapgnimiT.5 spe.6525.txEgnimiT
Specifications ispLSI 5256V Internal Timing Parameters1 Over Recommended Operating Conditions I/O Buffer tidcom 22 Input Pad and Buffer, Combinatorial Input – 0.7 – 0.9 – 1.4 ns tidreg 23 Input Pad and Buffer, Registered Input – 4.7 – 6.6 – 9.7 ns todcom 24 Output Pad and Buffer, Combinatorial Output – 1.3 – 2 – 2.6 ns todreg 25 Output Pad and Buffer, Registered Output – 1.8 – 2.8 – 4.6 ns todz 26 Output Buffer Enable/Disable – 1.3 – 1.7 – 2.6 ns tslf 27 Slew Rate Adder, Fast Slew – 0 – 0 – 0n s tsls 28 Slew Rate Adder, Slow Slew – 7.5 – 10 – 15 ns tslfd 29 Programmable Delay Adder, Fast Slew – 0.5 – 0.7 – 1n s tslsd 30 Programmable Delay Adder, Slow Slew – 8 – 10.7 – 16 ns GLB/Macrocell Delay Register tmbp 31 Macrocell Register/Latch Bypass – 0 – 0 – 0n s tmlat 32 Macrocell Latch Delay – 1 – 1.4 – 2n s tmco 33 Macrocell Register/Latch Clock to Output – 1 – 1 – 1n s tmsu 34 Macrocell Register/Latch Setup Time 1 – 1.1 – 1.7 – ns tmh 35 Macrocell Register/Latch Hold Time 2.5 – 3.9 – 5.3 – ns tmsuce 36 Macrocell Register/Latch CLKEN Setup Time 1 – 1.4 – 2 – ns tmhce 37 Macrocell Register/Latch CLKEN Hold Time 1 – 1.4 – 2 – ns tmrst 38 Macrocell Register/Latch Set/Reset Time – 1 – 1.4 – 2n s tftog 39 Toggle Flip-Flop Feedback – 1 – 1.3 – 2n s AND Array tandhs 40 AND Array, High Speed Mode – 3 – 4 – 6n s tandlp 41 AND Array, Low Power Mode – 5 – 6.0 – 10 ns PTSA t5ptcom 42 5 Product Term Bypass, Combinatorial – 1 – 1.4 – 2n s t5ptreg 43 5 Product Term Bypass, Registered – 1 – 1.7 – 2.3 ns t5ptxcom 44 5 Product Term XOR, Combinatorial – 2.5 – 3.6 – 5n s t5pxtreg 45 5 Product Term XOR, Registered – 1.5 – 2.2 – 3.3 ns tptsacom 46 Product Term Sharing Array, Combinatorial – 3 – 4.1 – 6n s tptsareg 47 Product Term Sharing Array, Registered – 2.0 – 2.7 – 4.3 ns PTSA Controls tpck 48 Product Term Clock Delay – 0.5 – 0.7 – 1n s tpcken 49 Product Term CLKEN Delay – 1 – 1.4 – 2n s tscken 50 Shared Product Term CLKEN Delay – 1 – 1.4 – 2n s tsck 51 Shared Product Term Clock Delay – 0.5 – 0.7 – 1n s tptsacken 52 Product Term Sharing Array CLKEN Delay – 2.0 – 2.4 – 4n s tsrst 53 Shared Product Term Set/Reset Delay – 2.5 – 3.4 – 5n s tprst 54 Product Term Set/Reset Delay – 1.5 – 2 – 3n s tpoe 55 Product Term Output Enable/Disable – 2.5 – 3.4 – 5n s tgpoe 56 Global PT Output Enable/Disable – 11.5 – 15.4 – 17 ns -125 -100 -70 MIN MAX MIN MAX MIN MAX UNIT PARAM # DESCRIPTION 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details.
Specifications ispLSI 5256V ispLSI 5256V Timing Model PT Controls Register Dedicated Input Buffers Output Buffer I/O PadI/O Pad INPUT OUTPUTPTSA GRP tgrpi GLB/Macrocell tandhs tgoe tgclk0 tgrst ttoe tslfd tandlp t5ptcom t5ptreg t5ptxreg t5ptxcom tptsacom tptsareg tscktpck tptsacken tsrst tpoe tgpoe tidcom tmh tmsuce tmrst tmhce tmco tgrpm tpcken tscken tslsd Slew Input Pad tprst tidreg Buffer Delays AND Array tgclken1 tgclken0 tgclk123 tftog tslf tsls Input Buffer #20 #21 #56 #38 #39 #40 #44 #42 #41 #45 #43 #49 #46 tmbp#29 todcom#22 #28 #27 #25 #26 todreg#23 todz#24 #37 tmlat#30 tmsu#32 #33 #31 #35 #34 #36 #50 #47 #48 #51 #52 #53 #54 #57 #58 #59 #60 #61 #62 #63 #55 GRP tgrpi 57 GRP Delay from I/O Pad – 1.5 – 2 – 3n s tgrpm 58 GRP Delay from Macrocell – 1.0 – 1.2 – 1.2 ns Global Control Delays tgclk01 59 Global Clock 0 or 1 Delay – 1.2 – 1.7 – 2.4 ns tgclk23 60 Global Clock 2 or 3 Delay – 2.2 – 2.7 – 4.4 ns tgclken0 61 Global CLKEN 0 Delay – 1.7 – 2.4 – 3.4 ns tgclken1 62 Global CLKEN 1 Delay – 2.7 – 3.4 – 5.4 ns tgrst 63 Global Set/Reset Delay – 12.2 – 15.8 – 23.4 ns tgoe 64 Global OE Delay – 4.7 – 6.3 – 9.4 ns ttoe 65 Test OE Delay – 4.7 – 6.2 – 9.4 ns Internal Timing Parameters1 Over Recommended Operating Conditions -125 -100 -70 MIN MAX MIN MAX MIN MAX UNIT PARAM # DESCRIPTION 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details.
relationship between power and operating speed. and the program in the device, the actual ICC should be verified. Figure 10. Typical Device Power Consumption vs fmax
Specifications ispLSI 5256V TMS Input - This pin is the Test Mode Select input, which is used to control the JTAG state machine. TCK Input - This pin is the Test Clock input pin used to clock through the JTAG state machine. TDI Input - This pin is the JTAG Test Data In pin used to load Data. TDO Output - This pin is the JTAG Test Data Out pin used to shift data out. TOE / I/O0 Input/Output - This pin functions as either the Test Output Enable pin or an I/O pin based upon customer's design. TOE tristates all I/O pins when a logic low is driven. GOE0, GOE1 Input - These two pins are the Global Output Enable input pins. GSET/GRST Dedicated Set/Reset Input - This pin is available to all registers in the device and can independently be configured as preset, reset or no effect on each register. The global polarity (active high or low input) for this pin is also selectable. I/O Input/Output – These are the general purpose I/O used by the logic array. GND Ground NC 1 No connect. VCC Vcc CLK0, CLK1 Dedicated clock inputs for all registers. Both clocks are muxed before being used as the clock input to all registers in the device. CLK2 / I/O, Input/Output - These pins function as either dedicated clock inputs for all registers or an I/O CLK3 / I/O pin based upon customer's design. Both clocks are muxed before being used as the clock input to all registers in the device. VCCIO Input - This pin is used if an optional 2.5V output is to be used. Every I/O can independently select either 3.3V or the optional voltage as its output level. If the optional output voltage is not required, this pin must be connected to the Vcc supply. Programmable pull-up resistors and bus-hold latches only draw current from this supply. Signal Descriptions Signal Name Description 1. NC pins are not to be connected to any active signals, VCC or GND.
Specifications ispLSI 5256V GOE0, GOE1 78, 79 TOE / I/O0 32 GSET/GRST 138 TCK 29 TDI 30 TDO 136 TMS 28 CLK0, CLK1 184,185 CLK2 / I/O89 162 CLK3 / I/O98 173 VCCIO 137 GND 3, 12, 19, 27, 39, 48, 58, 69, 77, 88, 99, 113, 121, 128, 135, 150, 164, 170, 179, 191, 199 VCC 7, 14, 22, 31, 41, 61, 80, 90, 110, 123, 139, 152, 156, 177, 186, 201 NC 49, 50, 51, 52, 101, 102, 103, 104, 105, 106, 107, 108, 109, 157, 158, 207, 208 Signal Locations (208-Pin PQFP) Signal Pin 1. NCs are not to be connected to any active signals, VCC or GND.
Specifications ispLSI 5256V I/O Locations (208-Pin PQFP) I/O # Pin I/O # Pin I/O # Pin I/O # Pin I/O # Pin I/O # Pin * I/O 89 is multiplexed with CLK2, I/O 98 is multiplexed with CLK3 and I/O 0 is multiplexed with TOE. 0* 32 13 3 23 4 33 5 43 6 53 7 63 8 74 0 84 2 94 3 10 44 11 45 12 46 13 47 14 53 15 54 16 55 17 56 18 57 19 59 20 60 21 62 22 63 23 64 24 65 25 66 26 67 27 68 28 70 29 71 30 72 31 73 32 74 33 75 34 76 35 81 36 82 37 83 38 84 39 85 40 86 41 87 42 89 43 91 44 92 45 93 46 94 47 95 48 96 49 97 50 98 51 100 52 111 53 112 54 114 55 115 56 116 57 117 58 118 59 119 60 120 61 122 62 124 63 125 64 126 65 127 66 129 67 130 68 131 69 132 70 133 71 134 72 140 73 141 74 142 75 143 76 144 77 145 78 146 79 147 80 148 81 149 82 151 83 153 84 154 85 155 86 159 87 160 88 161 89* 162 90 163 91 165 92 166 93 167 94 168 95 169 96 171 97 172 98* 173 99 174 100 175 101 176 102 178 103 180 104 181 105 182 106 183 107 187 108 188 109 189 110 190 111 192 112 193 113 194 114 195 115 196 116 197 117 198 118 200 119 202 120 203 121 204 122 205 123 206 124 1 125 2 126 4 127 5 128 6 129 8 130 9 131 10 132 11 133 13 134 15 135 16 136 17 137 18 138 20 139 21 140 23 141 24 142 25 143 26
Specifications ispLSI 5256V GOE0, GOE1 P9, P10 TOE / I/O0 K1 GSET/GRST H14 TCK K2 TDI K3 TDO G14 TMS J1 CLK0, CLK1 A7, B8 CLK2 / I/O89 B13 CLK3 / I/O98 A11 VCCIO H15 GND D10, D12, D13, D5, D7, D8, E4, F13, G4, G8, G9, H10, H13, H7, J10, J13, J4, J7, K8, K9, L13, L4, M13, N10, N12, N4, N5, N7, N8 VCC D11, D4, D6, D9, E13, F4, G10, G13, G7, H4, H8, H9, J8, J9, K10, K13, K4, K7, M4, N11, N13, N6, N9 NC
1 E15, C14
Signal Locations (208-Ball BGA) Signal Ball 1. NCs are not to be connected to any active signals, VCC or GND.
Specifications ispLSI 5256V I/O Locations (208-Ball BGA) I/O # Ball I/O # Ball I/O # Ball I/O # Ball I/O # Ball I/O # Ball * I/O 89 is multiplexed with CLK2, I/O 98 is multiplexed with CLK3 and I/O 0 is multiplexed with TOE. 0* K1 1L 2 2L 1 3L 3 4M 1 5M 2 6M 3 7N 1 8N 3 9N 2 10 P2 11 P1 12 R1 13 R2 14 R3 15 P3 16 T1 17 P4 18 R4 19 R5 20 P5 21 T2 22 R6 23 T3 24 T4 25 T5 26 R7 27 P6 28 T6 29 T7 30 R8 31 P8 32 P7 33 T8 34 T9 35 R9
36 R10
37 T10
38 T11
39 T12
40 T13
41 T14
42 P11
43 P12
44 R11
45 T15
46 T16
47 R14
48 R12
49 P14
50 P13
51 R13
52 R15
53 P15
54 R16
55 P16
56 N15
57 N14
58 M14
59 N16
60 M15
61 M16
62 L14
63 L15
64 L16
65 K14
66 K15
67 K16
68 J14
69 J15
70 J16
71 H16
72 G16
73 F14
74 G15
75 F16
76 E14
77 F15
78 E16
79 D16
80 C16
81 B16
82 D15
83 D14
84 A16
85 C15
86 B15
87 A15
88 B14
89* B13
90 C13
91 A14
92 C12
93 B12
94 A13
95 A12
96 C11
97 B11
98* A11
99 B10
100 A10
101 C10
Specifications ispLSI 5256V GOE0, GOE1 V11, U11 TOE / I/O 0 M2 SET/RST J18 TCK L4 TDI M1 TDO J20 TMS L3 CLK0, CLK1 C10, D10 CLK2 / I/O 119 A18 CLK3 / I/O 131 B13 VCCIO J19 GND A1, D4, D8, D13, D17, H4, H17, J9, J10, J11, J12, K9, K10, K11, K12, L9, L10, L11, L12, M9, M10, M11, M12, N4, N17, U4, U8, U13, U17 VCC D6, D11, D15, F4, F17, K4, L17, R4, R17, U6, U10, U15 NC
1 U1, W1, E2, U2, W2, Y2, B3, C3, D3, U3, C5, W4, T4, Y12, A17, T17, W17, B18, C18, B19, C19, D19,
W19, B20, T20, W20, Y20, P19, R3 Signal Locations (272-Ball Grid Array) Signal Ball 1. NCs are not to be connected to any active signals, VCC or GND.
Specifications ispLSI 5256V I/O Locations (272-Ball Grid Array) * I/O 119 is multiplexed with CLK2, I/O 131 is multiplexed with CLK3 and I/O 0 is multiplexed with TOE. 0* M2 1M 3 2M 4 3N 1 4N 2 5N 3 6P 1 7P 2 8R 1 9P 3 10 R2 11 T1 12 P4 13 T2 14 T3 15 V1 16 V2 17 V3 18 Y1 19 W3 20 V4 21 U5 22 Y3 23 Y4 24 V5 25 W5 26 Y5 27 V6 28 U7 29 W6 30 Y6 31 V7 32 W7 33 Y7 34 V8 35 W8 36 Y8 37 U9 38 V9 39 W9 40 Y9
41 W10
42 V10
43 Y10
44 Y11
45 W11
46 W12
47 V12
48 U12
49 Y13
50 W13
51 V13
52 Y14
53 W14
54 Y15
55 V14
56 W15
57 Y16
58 U14
59 V15
60 W16
61 Y17
62 V16
63 Y18
64 U16
65 V17
66 W18
67 Y19
68 V18
69 V19
70 U19
71 U18
72 V20
73 U20
74 T18
75 T19
76 R18
77 P17
78 R19
79 R20
80 P18
81 P20
82 N18
83 N19
84 N20
85 M17
86 M18
87 M19
88 M20
89 L19
90 L18
91 L20
92 K20
93 K19
94 K18
95 K17
96 J17
97 H20
98 H19
99 H18
100 G20
101 G19
102 F20
103 G18
104 F19
105 E20
106 G17
107 F18
108 E19
109 D20
110 E18
111 C20
112 E17
113 D18
114 A20
115 A19
116 B17
117 C17
118 D16
119* A18
120 C16
121 B16
122 A16
123 C15
124 D14
125 B15
126 A15
127 C14
I/O # Ball I/O # Ball I/O # Ball I/O # Ball I/O # Ball I/O # Ball
128 B14
129 A14
130 C13
131* B13
132 A13
133 D12
134 C12
135 B12
136 A12
137 B11
138 C11
139 A11
140 A10
141 B10
Specifications ispLSI 5256V Pin Configuration ispLSI 5256V 208-pin PQFP ispLSI 5256V Top View 208-PQFP/5256V 100 101 102 103 104 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 1. NC pins are not to be connected to any active signal, Vcc or GND. 2. Pins have dual function capability. I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 GND I/O 19 I/O 20 VCC I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 GND I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 GND GOE0 GOE1 VCC I/O 35 I/O 36 I/O 37 I/O 38 I/O 39 I/O 40 I/O 41 GND I/O 42 VCC I/O 43 I/O 44 I/O 45 I/O 46 I/O 47 I/O 48 I/O 49 I/O 50 GND I/O 51 1NC 1NC 1NC 1NC NC 1 NC 1 I/O 123 I/O 122 I/O 121 I/O 120 I/O 119 VCC I/O 118 GND I/O 117 I/O 116 I/O 115 I/O 114 I/O 113 I/O 112 I/O 111 GND I/O 110 I/O 109 I/O 108 I/O 107 VCC CLK1 CLK0 I/O 106 I/O 105 I/O 104 I/O 103 GND I/O 102 VCC I/O 101 I/O 100 I/O 99 I/O 98 / CLK32 I/O 97 I/O 96 GND I/O 95 I/O 94 I/O 93 I/O 92 I/O 91 GND I/O 90 I/O 89 / CLK22 I/O 88 I/O 87 I/O 86 NC 1 NC 1 VCC I/O 85 I/O 84 I/O 83 VCC I/O 82 GND I/O 81 I/O 80 I/O 79 I/O 78 I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 VCC GSET/GRST VCCIO TDO GND I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 GND I/O 65 I/O 64 I/O 63 I/O 62 VCC I/O 61 GND I/O 60 I/O 59 I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 GND I/O 53 I/O 52 VCC NC 1 NC 1 NC 1 NC 1 NC 1 I/O 124 I/O 125 GND I/O 126 I/O 127 I/O 128 VCC I/O 129 I/O 130 I/O 131 I/O 132 GND I/O 133 VCC I/O 134 I/O 135 I/O 136 I/O 137 GND I/O 138 I/O 139 VCC I/O 140 I/O 141 I/O 142 I/O 143 GND TMS TCK TDI VCC 2I/O 0 / TOE I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 GND I/O 7 VCC I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 GND 1NC 1NC 1NC 1NC
Specifications ispLSI 5256V Part Number Description
Ordering Information
Blank = Commercial ispLSI5256V XXX X XXXX Speed 125 = 125 MHz fmax 100 = 100 MHz fmax 70 = 70 MHz fmax Power L = Low Package B272 = 272-BGA Q208 = 208-PQFP B208 = 208-BGA Device Family X ylimaFf xam t dp rebmuNgniredrOe gakcaP ISLpsi 5215 .72 72BL521-V6525ISLpsiA GBllaB-272 *802QL521-V6525ISLpsiP FQPniP-802 *802BL521-V6525ISLpsiA GBllaB-802 ISLpsi 0010 12 72BL001-V6525ISLpsiA GBllaB-272 *802QL001-V6525ISLpsiP FQPniP-802 *802BL001-V6525ISLpsiA GBllaB-802 ISLpsi 075 12 72BL07-V6525ISLpsiA GBllaB-272 *802QL07-V6525ISLpsiP FQPniP-802 *802BL07-V6525ISLpsiA GBllaB-802 ytilibaliavArofyrotcaFtcatnoC*