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The Si510/511 XO utilizes Silicon Laboratories' advanced DSPLL technology to provide any frequency from 100 kHz to 250 MHz. Unlike a traditional XO where a different crystal is required for each output frequency, the Si510/511 uses one fixed crystal and Silicon Labs’ proprietary DSPLL synthesizer to generate any frequency across this range. This IC-based approach allows the crystal resonator to provide enhanced reliability, improved mechanical robustness, and excellent stability. In addition, this solution provides superior supply noise rejection, simplifying low jitter clock generation in noisy environments. Crystal ESR and DLD are individually production-tested to guarantee performance and enhance reliability. The Si510/511 is factory- configurable for a wide variety of user specifications, including frequency, supply voltage, output format, output enable polarity, and stability. Specific configurations are factory-programmed at time of shipment, eliminating long lead times and non-recurring engineering charges associated with custom frequency oscillators. Functional Block Diagram Supports any frequency from 100 kHz to 250 MHz Low jitter operation 2 to 4 week lead times Total stability includes 10-year aging Comprehensive production test coverage includes crystal ESR and DLD On-chip LDO regulator for power supply noise filtering 3.3, 2.5, or 1.8 V operation Differential (LVPECL, LVDS, HCSL) or CMOS output options Optional integrated 1:2 CMOS fanout buffer Runt suppression on OE and power on Industry standard 5 x 7 and 3 . 2x5 m m p a c k a g e s Pb-free, RoHS compliant –40 to 85 oC operation SONET/SDH/OTN Gigabit Ethernet Fibre Channel/SAS/SATA PCI Express 3G-SDI/HD-SDI/SDI Telecom Switches/routers FPGA/ASIC clock generation VDD Any-Frequency 0.1 to 250 MHz DSPLL® Synthesis Fixed Frequency Oscillator CLK+ CLK– OE GND Low Noise Regulator Ordering Information: See page 14. Pin Assignments: See page 12. Si5602 4GND OE VDD CLK+ CLK– NC 4GND NC VDD CLK+ CLK– OE Si510(LVDS/LVPECL/HCSL/ Dual CMOS) Si510 (CMOS) Si511(LVDS/LVPECL/HCSL/ Dual CMOS) 3GND VDD CLK OE 4GND NC VDD CLK+ CLK– OE
2 Rev. 1.1
Rev. 1.1 3 TABLE OF C ONTENTS Section Page
- Electrical Specifications
Table 1. Operating Specifications *Note: Active high and active low polarity OE options available. Active high option includes an internal pull-up. Active low option includes an internal pull-down. See ordering information on page 14.
Table 2. Output Clock Frequency Characteristics (not under operation), and 10 years aging at 40 oC.
Table 3. Output Clock Levels and Symmetry
2.5 V –6 — — mA
1.8 V –4 — — mA
2.5 V 6 — — mA
1.8 V 4 — — mA
Table 4. Output Clock Jitter and Phase Noise (LVPECL)
156.25 MHz
1 MHz — –136 — dBc/Hz
Table 5. Output Clock Jitter and Phase Noise (LVDS)
Table 6. Output Clock Jitter and Phase Noise (HCSL)
1 MHz — –140 — dBc/Hz
*Note: Applies to an output frequency of 100 MHz.
Table 7. Output Clock Jitter and Phase Noise (CMOS, Dual CMOS) Table 8. Environmental Compliance and Package Information
Table 9. Thermal Characteristics Table 10. Absolute Maximum Ratings1
- Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation or
periods may affect device reliability.
- The device is compliant with JEDEC J-STD-020.
*Supports integrated 1:2 CMOS buffer. See ordering information and section 2.1“Dual CMOS Buffer”. Table 11. Si510 Pin Descriptions (CMOS) internal pull-down for OE active low. See ordering information. Table 12. Si510 Pin Descriptions (LVPECL/LVDS/HCSL, Dual CMOS, OE Pin 2) 1 NC No connect. Make no external connection to this pin. internal pull-down for OE active low. See ordering information. 5 CLK– Complementary Clock Output. Table 13. Si511 Pin Descriptions (LVPECL/LVDS/HCSL, Dual CMOS, OE Pin 1) internal pull-down for OE active low. See ordering information. 2 NC No connect. Make no external connection to this pin. 5 CLK– Complementary Clock Output.
enables replacement of multiple XOs with a single Si510/11 device. Figure 1. Integrated 1:2 CMOS Buffer Supports Complementary or In-Phase Outputs
packages. Tape and reel packaging is an ordering option. Figure 2. Part Number Syntax low in 5 x 7 mm package across –40oC to 85oC temperature range. The output frequency is 156.25 MHz. Note: CMOS and Dual CMOS maximum frequency is 212.5 MHz. R = Tape & Reel; Blank = Trays.
510 CMOS OE on pin 1 4-pin
510 LVPECL, LVDS, HCSL, Dual CMOS OE on pin 2 6-pin
511 LVPECL, LVDS, HCSL, Dual CMOS OE on pin 1 6-pin
24 Rev. 1.1 DOCUMENT CHANGE LIST Revision 0.9 to Revision 1.0 Updated Table 1 on page 4. Updates to supply current typical and maximum values for CMOS, LVDS, LVPECL and HCSL. CMOS frequency test condition corrected to 100 MHz. Updates to OE VIH minimum and VIL maximum values. Updated Table 2 on page 5. Dual CMOS nominal frequency maximum added. Total stability footnotes clarified for 10 year aging at 40 °C. Disable time maximum values updated. Enable time parameter added. Updated Table 3 on page 6. CMOS output rise / fall time typical and maximum values updated. LVPECL/HCSL output rise / fall time maximum value updated. LVPECL output swing maximum value updated. LVDS output common mode typical and maximum values updated. HCSL output swing maximum value updated. Duty cycle minimum and maximum values tightened to 48/52%. Updated Table 4 on page 7. Phase jitter test condition and maximum value updated. Phase noise typical values updated. Additive RMS jitter due to external power supply noise typical values updated. Footnote 3 updated limiting the VDD to 2.5/3.3V Added Tables 5, 6, 7 for LVDS, HCSL, CMOS, and Dual CMOS operations. Moved Absolute Maximum Ratings table. Added note to Figure 2 clarifying CMOS and Dual CMOS maximum frequency. Updated Figure 10 outline diagram to correct pinout. Revision 1.0 to Revision 1.1 Updated Table 3. CMOS Output Rise/Fall Time Test Condition updated.
Rev. 1.1 25 NOTES:
26 Rev. 1.1 CONTACT INFORMATION Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse- quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per- sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.