4463C-915-PDK

4463C-915-PDK SILABS | Alldatasheet

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Description

Silicon Laboratories' Si446x devices are high-performance, low-current transceivers covering the sub-GHz freque ncy bands from 119 to 1050 MHz. The radios are part of the EZRadioPRO ® family, which includes a complete line of transmitters, receivers, and transceivers covering a wide range of applications. All parts offer outstanding sensitivity of –126 dBm while achieving extremely low active and standby current consumption. The Si4463/61/60 offers frequency coverage in all major bands. The Si4464 offers frequency coverage in bands not covered by Si4463/61/60. Typically, these are non-standard frequencies or licensed frequency bands. The Si446x in cludes optimal phase noise, blocking, and selectivity performance for narrow band and licensed band applications, such as FCC Part90 and 169 MHz wireless Mbus. The 60 dB adjacent channel selectivity with 12.5 kHz channel spaci ng ensures robust receive operation in harsh RF conditions, which is particular ly important for narrow band operation. The Si4464/63 offers exceptional output power of up to +20 dBm with outstanding TX efficiency. The high output power and sensitivity results in an industry-leading link budget of 146 dB allowing extended ranges and highly robust communication links. The Si4460 active mode TX current consumption of 18 mA at +10 dBm and RX current of 10 mA coupled with extremely low standby current and fast wake times ensure extended battery life in the most demanding applications. The Si4464/63 can achieve up to +27 dBm out put power with built-in ramping control of a low-cost external FET. The devices can meet worldwide regulatory standards: FCC, ETSI, and ARIB. All devices are designed to be compliant with 802.15.4g and WMbus smart metering standards. The devices are highly flexible and can be configured via the Wireless Development Suite (WDS) available on the Silicon Labs web site.  Frequency range = 119–1050 MHz  Receive sensitivity = –126 dBm  Modulation (G)FSK, 4(G)FSK, (G)MSK OOK  Max output power +16 dBm (Si4461) +13 dBm (Si4460)  PA support for +27 or +30 dBm  Low active power consumption 10/13 mA RX 18 mA TX at +10 dBm (Si4460)  Ultra low current powerdown modes 30 nA shutdown, 50 nA standby  Data rate = 100 bps to 1 Mbps  Fast wake and hop times  Power supply = 1.8 to 3.6 V  Excellent selectivity performance 60 dB adjacent channel 75 dB blocking at 1 MHz  Antenna diversity and T/R switch control  Highly configurable packet handler  TX and RX 64 byte FIFOs  Auto frequency control (AFC)  Automatic gain control (AGC)  Low BOM  Low battery detector  Temperature sensor  20-Pin QFN package  IEEE 802.15.4g compliant  FCC Part 90 Mask D, FCC part 15.247, RCR STD-30, China regulatory  ETSI Class-I Operation with SAW  Smart metering (802.15.4g & MBus)  Remote control  Home security and alarm  Telemetry  Garage and gate openers  Remote keyless entry  Home automation  Industrial control  Sensor networks  Health monitors  Electronic shelf labels Patents pending Pin Assignments GND PAD 17181920 6 7 8 9 GND GPIO1 nSEL SDI SDO SCLKNC SDN TX GPIO0 VDD nIRQ RXp RXn XIN GPIO3 GPIO2 XOUT TXRamp VDD

2 Rev 1.2 Functional Block Diagram Product Freq. Range Max Output Power TX Current RX Current Narrow Band Support Image Cal Si4464 Banded 119–960 MHz +20 dBm 915 MHz: 85 mA 10.6/13.6 mA  Si4463 Major bands 142-1050 MHz + 2 0d B m 1 6 9M H z : 7 0m A

915 MHz: 85 mA

10/13 mA  Si4461 Major bands 142-1050 MHz + 1 6d B m + 1 3d B m : 2 9m A +14 dBm: 33 mA 10/13 mA  Si4460 Major bands 142-1050 MHz + 1 3d B m + 1 0d B m : 1 8m A +11 dBm: 20 mA 10/13 mA  VCO Loop Filter PFD / CP Frac-N Div 30 MHz XO LO Gen LNA RF PKDET PGA ADC MODEM FIFO Packet Handler 32K LP OSC Bootup OSC LBD POR IF PKDET SPI Interface Controller Digital Logic PowerRamp Cntl PA LDO TX DIV RXP RXN TX VDD TXRAMP XOUTXIN nSEL SDI SDO SCLK nIRQ LDOs FBDIV PA VDD GPIO0 GPIO1 GPIO2GPIO3 SDN

Rev 1.2 3 TABLE OF C ONTENTS Section Page

1. Electrical Specifications

Table 1. DC Characteristics1

1. All specifications guaranteed by production test unless otherwise noted. Production test conditions and max limits are

listed in the "Production Test Conditions" section of "1.1. Definition of Test Conditions" on page 14.

1. Guaranteed by qualification. Qualification test conditions are listed in the “Qualification Test Conditions” section in "1.1.

Definition of Test Conditions" on page 14.

Table 2. Synthesizer AC Electrical Characteristics1 XOSC running to any frequency.

1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are

listed in the “Production Test Conditions” section in "1.1. Definition of Test Conditions" on page 14.

1. For applications that use the major bands covered by Si4463/61/60, customers should use those parts instead of
2. Default API setting for modulation deviation resolution is double the typical value specified.
3. Guaranteed by qualification. Qualification test conditions are listed in the "Qualification Test Conditions" section in "1.1.

Definition of Test Conditions" on page 14.

Table 3. Receiver AC Electrical Characteristics1

1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are

listed in the "Production Test Conditions" section in "1.1. Definition of Test Conditions" on page 14.

1. For applications that use the major bands covered by Si4463/61/60, customers should use those parts instead of
2. Guaranteed by qualification. BER is specified for the 450–470 MHz band. Qualification test conditions are listed in the

"Qualification Test Conditions" section in "1.1. Definition of Test Conditions" on page 14.

1. For PER tests, 48 preamble symbols, 4 byte sync word, 10 byte payload and CRC-32 was used. PER and BER tested
2. Guaranteed by bench characterization.

Table 3. Receiver AC Electrical Characteristics1 (Continued)

1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are

listed in the "Production Test Conditions" section in "1.1. Definition of Test Conditions" on page 14.

1. For applications that use the major bands covered by Si4463/61/60, customers should use those parts instead of
2. Guaranteed by qualification. BER is specified for the 450–470 MHz band. Qualification test conditions are listed in the

"Qualification Test Conditions" section in "1.1. Definition of Test Conditions" on page 14.

1. For PER tests, 48 preamble symbols, 4 byte sync word, 10 byte payload and CRC-32 was used. PER and BER tested
2. Guaranteed by bench characterization.

169 MHz3

450 MHz3

tion at the image frequency.

1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are

listed in the "Production Test Conditions" section in "1.1. Definition of Test Conditions" on page 14.

1. For applications that use the major bands covered by Si4463/61/60, customers should use those parts instead of
2. Guaranteed by qualification. BER is specified for the 450–470 MHz band. Qualification test conditions are listed in the

"Qualification Test Conditions" section in "1.1. Definition of Test Conditions" on page 14.

1. For PER tests, 48 preamble symbols, 4 byte sync word, 10 byte payload and CRC-32 was used. PER and BER tested
2. Guaranteed by bench characterization.

Table 4. Transmitter AC Electrical Characteristics1

1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are

listed in the "Production Test Conditions" section in "1.1. Definition of Test Conditions" on page 14.

1. For applications that use the major bands covered by Si4463/61/60, customers should use those parts instead of
2. Guaranteed by qualification. Qualification test conditions are listed in the "Qualification Test Conditions" section in "1.1.

Definition of Test Conditions" on page 14.

1. The maximum data rate is dependant on the XTAL frequency and is calculated as per the formula:

Maximum Symbol Rate = Fxtal/60, where Fxtal is the XTAL frequency (typically 30 MHz).

1. Default API setting for modulation deviation resolution is double the typical value specified.
2. Output power is dependent on matching components and board layout.

Table 4. Transmitter AC Electrical Characteristics1 (Continued)

1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are

listed in the "Production Test Conditions" section in "1.1. Definition of Test Conditions" on page 14.

1. For applications that use the major bands covered by Si4463/61/60, customers should use those parts instead of
2. Guaranteed by qualification. Qualification test conditions are listed in the "Qualification Test Conditions" section in "1.1.

Definition of Test Conditions" on page 14.

1. The maximum data rate is dependant on the XTAL frequency and is calculated as per the formula:

Maximum Symbol Rate = Fxtal/60, where Fxtal is the XTAL frequency (typically 30 MHz).

1. Default API setting for modulation deviation resolution is double the typical value specified.
2. Output power is dependent on matching components and board layout.

Table 5. Auxiliary Block Specifications1 32.768 kHz is also supported.

30 MHz XTAL Start-Up Time t 30M Using XTAL and board layout in

30 MHz XTAL Cap

1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are

listed in the "Production Test Conditions" section in "1.1. Definition of Test Conditions" on page 14.

1. Guaranteed by qualification. Qualification test conditions are listed in the "Qualification Test Conditions" section in "1.1.

Definition of Test Conditions" on page 14.

1. Microcontroller clock frequency tested in production at 1 MHz, 30 MHz and 32.768 kHz. Other frequencies tested in
2. XTAL Range tested in production using an external clock source (similar to using a TCXO).

Table 6. Digital IO Specifications (GPIO_x, SCLK, SDO, SDI, nSEL, nIRQ, SDN)1

1. All specifications guaranteed by qualification. Qualification test conditions are listed in the "Qualification Test

Conditions" section in "1.1. Definition of Test Conditions" on page 14.

1. 8 ns is typical for GPIO0 rise time.
2. 2.4 ns is typical for GPIO0 fall time.

Table 7. Absolute Maximum Ratings matching network design will influence TX VRF-peak on TX output pin. Caution: ESD sensitive device.

14 Rev 1.2 1.1. Definition of Test Conditions Production Test Conditions: TA =+ 2 5° C . VDD =+ 3 . 3V D C . TX output power measured at 915 MHz. External reference signal (XOUT) = 1.0 VPP at 30 MHz, centered around 0.8 VDC. Production test schematic (unless noted otherwise). All TX output levels are referred to the pins of the Si4464/63/61/60 (not the output of the RF module). All RX input levels are referred to the input of a tuned balun connected to the RX input pins of the Si4464/63/61/60. Qualification Test Conditions: TA = –40 to +85 °C (Typical TA = 25 °C). VDD = +1.8 to +3.6 VDC (Typical VDD =3 . 3V D C ) . Using TX/RX Split Antenna reference design or production test schematic. All RF input and output levels referred to the pins of the Si4464/63/61/60 (not the RF module).

Rev 1.2 15 2. Functional Description The Si446x devices are high-performance, low-current, wir eless ISM transceivers that cover the sub-GHz bands. The wide operating voltage range of 1.8–3.6 V and low curr ent consumption make the Si446x an ideal solution for battery powered applications. The Si4 46x operates as a time division dup lexing (TDD) transceiver where the device alternately transmits and receives data packets. The device uses a single-conversion mixer to downconvert the 2/4-level FSK/GFSK or OOK modulated receive signal to a low IF frequency. Following a programmable gain amplifier (PGA) the signal is converted to the digital domain by a high performance  ADC allowing filtering, demodulation, slicing, and packet handling to be perf ormed in the built-in DSP increasing the receiver’s performance and flexibility versus anal og based architectures. The demodulated signal is output to the system MCU through a programmable GPIO or via the standard SPI bus by reading the 64-byte RX FIFO. A single high precision local oscillator (LO) is used for both transmit and receive m odes since the transmitter and receiver do not operate at the same time. The LO is generated by an integrated VCO and  Fractional-N PLL synthesizer. The synthesizer is design ed to support configurable data rates from 100 bps to 1 Mbps. The Si4463/61/60 operate in the frequency bands of 142–175, 283–350, 420–525, and 850–1050 MHz with a maximum frequency accuracy step size of 28.6 Hz. The Si 4464 offers frequency coverage in bands not supported by Si4463/61/60. The transmit FSK data is modulated directly into the  data stream and can be shaped by a Gaussian low-pass filter to reduce unwanted spectral content. The Si4464/63 contains a power amplifier (PA) that supports output power up to +20 dBm with very high efficiency, consuming only 70 mA at 169 MHz and 85 mA at 915 MHz. The integrated +20 dBm power amplifier can also be used to compensate for the reduced performance of a lower cost, lower performance antenna or antenna with size constraints due to a small form-factor. Competing solutions require large and expensive external PAs to achieve comparable performance. The Si4461 supplies output power up to +16 dBm. The Si4460 is designed to support single coin cell operation with current consumption below 18 mA for +10 dBm output power. Two match topologies are available for the Si4461 and Si4460, class-E and swit ched-current. Class-E matching provides optimal current consumption, while switched-current matching demonstr ates the best performance ov er varying battery voltage and temperature with slightly higher current consumption. The PA is single-ended to allow for easy antenna matching and low BOM cost. The PA incorporates automatic ramp-up and ramp-down control to reduce unwanted spectral spreading. The Si446x family supports frequen cy hopping, TX/RX switch control, and antenna diversity switch control to extend the link range and improve pe rformance. Built-in antenna diversity and support for frequency hopping can be used to further extend range and enhance performance. Antenna diversity is completely integrated into the Si446x and can improve the system lin k budget by 8–10 dB, resulting in substantial range increases under adverse environmental conditions. A high ly configurable packet handler allows for autonomous encoding/decoding of nearly any packet structure. Addi tional system features, such as an automatic wake-up timer, low battery detector, 64 byte TX/RX FIFOs, and preamble detection, reduce overall current consumption and allows for the use of lower-cost system MCUs. An integrated temperature sensor, power-on-reset (POR), and GPIOs further reduce overall system co st and size. The Si446x is designed to work with an MCU, crystal, and a few passive components to create a very low-cost system. The application shown in Figure 1 is designed for a system with a TX/RX direct-tie configuration without the use of a TX/RX switch. Most applications with output power less than 17 dBm will use this configuration. Figure 2 demonstrates an application for +20 dBm using an external T/R-switch.

Figure 1. Si4461 Direct-Tie Application Example Figure 2. Si4463 Single Antenna with RF Switch Example

30 MHz

Figure 3. SPI Write Command SDO data on the rising edge of SCLK. Table 8. Serial Interface Timing Parameters

“FRR_CTL_X_MODE” properties. FRRs will not be updated unless NSEL is toggled. but any of the lower power states can be returned to automatically after RX or TX. Figure 6. State Machine Diagram

holding the SDN high for this period of time may cause the POR to be missed and the device to boot up incorrectly. host processor rather than tying it to GND on the board. interrupt registers must be read to achieve the minimum current consumption of this mode. must be read to achieve the minimum current consumption of this mode. return to either the standby or sleep modes. ramping up the PA. The following sequence of events will occur automatically when going from standby to TX state.

1. Start up crystal oscillator and wait until ready (controlled by an internal timer).

Table 10. POR Timing

Rev 1.2 23 3.4. Application Programming Interface (API) An application programming interfac e (API), which the host MCU will commun icate with, is embedded inside the device. The API is divided into two sections, commands and properties. The commands are used to control the chip and retrieve its status. The pr operties are general co nfigurations which will ch ange infrequen tly. The API descriptions can be found in“AN625: Si446x API Descriptions”. 3.5. Interrupts The Si446x is capable of generating an interrupt signa l when certain events occur. The chip notifies the microcontroller that an interrupt event has occurred by setting the nIRQ output pin LOW = 0. This interrupt signal will be generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits) occur. The nIRQ pin will remain low until the mi crocontroller reads the Interrupt Status Registers. The nIRQ output signal will then be reset until the next change in status is detected. The interrupts sources are grouped into three groups: packet handler, chip status, and modem. The individual interrupts in these groups can be enabled/disabled in t he interrupt property register s, 0101, 0102, and 0103. An interrupt must be enabled for it to trigger an event on the nIRQ pin. The interrupt group must be enabled as well as the individual interrupts in API property 0100. Once an interrupt event occurs and the nIRQ pin is low th ere are two ways to read and clear the interrupts. All of the interrupts may be read and cleared in the “GET_INT_STATUS” API command. By default all interrupts will be cleared once read. If only specific inte rrupts want to be read in the fastest possible method the individual interrupt groups (Packet Handler, Chip Status, Modem) may be read and cleared by the “GET_MODEM_STATUS”, “GET_PH_STATUS” (packet handler), and “GET_CHIP_STATUS” API commands. The instantaneous status of a specific function maybe read if the specific interrupt is enabled or disabled. The status results are provided after the interrupts and can be read with the same commands as the interrupts. The status bits will give the current state of the function whether the interrupt is enabled or not. The fast response registers can also give information about the interrupt groups but reading the fast response registers will not clear the interrupt and reset the nIRQ pin. Number Command Summary 0x20 GET_INT_STATUS Returns the interrupt status—packet handler, modem, and chip 0x21 GET_PH_STATUS Returns the packet handler status. 0x22 GET_MODEM_STATUS Returns the modem status byte. 0x23 GET_CHIP_STATUS Retur ns the chip status. Number Property Default Summary 0x0100 INT_CTL_ENABLE 0x04 Enables interrupt groups for PH, Modem, and Chip. 0x0101 INT_CTL_PH_ENABLE 0x00 Packet handler interrupt enable property. 0x0102 INT_CTL_MODEM_ENABLE 0x00 Modem interrupt enable property. 0x0103 INT_CTL_CHIP_ENABLE 0x04 Chip interrupt enable property.

GPIO_PIN_CFG command in address 13h. For a complete list of the GPIO options please see the API guide. drive strength than the other GPIOs. Table 11. GPIOs

Rev 1.2 25 4. Modulation and Hardware Configuration Options The Si446x supports different modulation options and can be used in various configurations to tailor the device to any specific application or legacy system for drop in replacement. The modulation and configuration options are set in API property, MODEM_MOD_TYPE. 4.1. MODEM_MOD_TYPE Summary: Modulation Type Purpose: This property selects between OOK, FSK, 4FSK and GFSK modulation, modulation source, and tx direct mode control. The modulator must be configured for one mode through the entire packet. If portions of the packet alternate between FSK and 4FSK modes, the modem should be programmed to 4FSK mode. Property: 0x2000 Default: 0x02 Fields: TX_DIRECT_MODE_TYPE - default:0 0 = Direct mode operates in synchronous mode, applies to TX only. 1 = Direct mode operates in asynchronous mode, applies to TX only. GFSK is not supported. TX_DIRECT_MODE_GPIO[1:0] - default:0x0 0 = TX direct mode uses gpio0 as data source, applies to TX only. 1 = TX direct mode uses gpio1 as data source, applies to TX only. 2 = TX direct mode uses gpio2 as data source, applies to TX only. 3 = TX direct mode uses gpio3 as data source, applies to TX only. MOD_SOURCE[1:0] - default:0x0 0 = Modulation source is packet handler fifo 1 = Modulation source is direct mode pin 2 = Modulation source is pseudo-random generator MOD_TYPE[2:0] - default:0x2 0=C W 1=O O K 2 = 2FSK 3 = 2GFSK 4 = 4FSK 5 = 4GFSK Register View MODEM_MOD_TYPE 76 5 4 3 2 1 0 TX_DIRECT_MODE_TYPE TX_DIR ECT_MODE_GPIO[1:0] MOD_SO URCE[1:0] MOD_TYPE[2:0] 0 0x0 0x0 0x2

26 Rev 1.2 4.2. Modulation Types The Si446x supports five different modulation options: Gaussian frequency shift keying (GFSK), frequency-shift keying (FSK), four-level GFSK (4GFSK), four-level F SK (4FSK), and on-off keying (OOK). Minimum shift keying (MSK) can also be created by using GFSK settings. GFSK is the recommended modulation type as it provides the best performance and clea nest modulation spectrum . The modulation type is set by the “M OD_TYPE[2:0]” registers in the “MODEM_MOD_TYPE” API property. A continuous-wave (CW) carrier may also be selected for RF evaluation purposes. The modulation source may also be selected to be a pseudo-random source for evaluation purposes. 4.3. Hardware Configuration Options There are different receive demodulator options to opti mize the performance and mutually-exclusive options for how the RX/TX data is transferred from the host MCU to the RF device. 4.3.1. Receive Demodulator Options There are multiple demodulators integrated into the device to optimize the performance for different applications, modulation formats, an d packet structures. The calcul ator built into WDS will choo se the optimal demodulator based on the input criteria. 4.3.1.1. Synchronous Demodulator The synchronous demodulator's internal frequency erro r estimator acquires the frequency error based on a 101010 preamble structure. The bit clock recovery circuit locks to the incoming data stream within four transactions of a “10” or “01” bit stream. The synchronous demodulator gives optimal performance for 2- or 4-level FSK or GFSK modulation that has a modulation index less than 2. 4.3.1.2. Asynchronous Demodulator The asynchronous demodulator should be used OOK modulation and for FSK/GFSK/4GFSK under one or more of the following conditions: Modulation index > 2 Non-standard preamble (not 1010101... pattern) When the modulation index exceeds 2, the asynchronous demodulator has better sensitivity compared to the synchronous demodulator. An internal deglitch circuit provides a glitch-free data output and a data clock signal to simplify the interface to the host. There is no requirement to perform deglitching in the host MCU. The asynchronous demodulator will typically be utilized for legacy system s and will have many performance benefits over devices used in legacy designs. Unlike the Si4432/31 solution for non-standard packet structures, there is no requirement to perform deglitching on the data in the host MCU. Glitch-free data is output from Si446x devices, and a sample clock for the asynchronous data can also be supplied to the host MCU; so, oversampling or bit clock recovery is not required by the host MCU. There are multiple detector options in the asynchronous demodulator block, which will be selected based upon the options entered into the WDS calc ulator. The asynchronous demodulator's internal frequency error estimator is able to acquire the frequency error based on any preamble structure. 4.3.2. RX/TX Data Interface With MCU There are two different options for transferring the data from the RF device to the host MCU. FIFO mode uses the SPI interface to transfer the data, while direct mode transfers the data in real time over GPIO. 4.3.2.1. FIFO Mode In FIFO mode, the transmit and receive data is stored in integrated FIFO register memory. The TX FIFO is accessed by writing Command 66h followed directly by the dat a/clk that the host wants to write into the TX FIFO. The RX FIFO is accessed by writing command 77h followed by the number of clock cycles of data the host would like to read out of the RX FIFO. The RX data will be clocked out onto the SDO pin. In TX mode, if the packet handler is enabled, the data by tes stored in FIFO memory are “packaged” together with other fields and bytes of information to construct the fina l transmit packet structure. These other potential fields include the Preamble, Sync word, Header, CRC checksum, etc. The configuration of the packet structure in TX mode is determined by the Automatic Packet Handler (if e nabled), in conjunction with a variety of Packet Handler properties. If the Automatic Packet Handler is disabled, th e entire desired packet structure should be loaded into FIFO memory; no other fields (such as Preamble or Sync word) will be automatically added to the bytes stored in

Rev 1.2 27 FIFO memory. For further information on the configuration of the FIFOs for a specific application or packet size, see "6. Data Handling and Packet Handler" on page 39. In RX mode, only the bytes of the received packet structure that are considered to be “data bytes” are stored in FIFO memory. Which bytes of the received packet are considered “data bytes” is determined by the Automatic Packet Handler (if enabled) in conjunction with the Packet Handler configuration. If the Automatic Packet Handle r is disabled, all bytes following the Sync word are considered data bytes and are stored in FIFO memory. Th us, even if Automatic Packet Handling operation is not desired, the preamble detection threshold and Sync word still need to be progra mmed so that the RX Modem knows when to start filling data into th e FIFO. When the FIFO is being used in RX mode, all of the received data may still be observed directly (in realtime) by properly programming a GPIO pin as the RXDATA output pin; this can be quite useful during application development. When in FIFO mo de, the chip will automatica lly exit the TX or RX State when either the PACKET_SENT or PACKET_RX interr upt occurs. The chip will re turn to the IDLE state programmed in the argument of the “START TX” or “START RX” API command, TXCOMPLETE_STATE[3:0] or RXVALID_STATE[3:0]. For example, the chip may be placed into TX mode by sending the “START TX” command and by writing the 30h to the TXCOMPLETE_STATE[3:0] argument. The chip will transmit all of the contents of the FIFO, and the ipksent interrupt will occur. When this event occurs, the chip will return to the ready state as defined by TXCOMPLETE_STATE[3:0] = 30h. 4.3.2.2. Direct Mode For legacy systems that perform packet handling within the host MCU or other baseband chip, it may not be desirable to use the FIFO. For this scenario, a Direct mode is provided, which bypasses the FIFOs entirely. In TX Direct mode, the TX modulation data is applied to an inpu t pin of the chip and processed in “real time” (i.e., not stored in a register for transmission at a later time). Any of the GPIOs may be configured for use as the TX Data input function. Furthermore, an additional pin may be required for a TX Clock output function if GFSK modulation is desired (only the TX Data input pin is required for FSK). To achieve direct mode, the GPIO must be configured in the “GPIO_PIN_CFG” API command as well as the “MODEM_MOD_TYPE” API property. For GFSK, “TX_DIRECT_MODE_TYPE” must be set to Synchronous. For 2FSK or OOK, the type can be set to asynchronous or synchronous. The MOD_SOURCE[1:0] should be set to 01h for are all direct mode configurations. In RX Direct mode, the RX Data and RX Clock can be programmed for direct (real-time) output to GPIO pins. The microcontroller may then process the RX data without using the FIFO or packet handler functions of the RFIC. 4.4. Preamble Length The preamble length requirement is only relevant if using the synchronou s demodulator. If the asynchronous demodulator is being used, then there is no requirement for a conventional 101010 pattern. The preamble detection threshold determines the number of valid preamble bits the radio must receive to qualify a valid preamble. The preamble threshold should be adjusted depending on the nature of the application. The required preamble length threshold depends on when rece ive mode is entered in relation to the start of the transmitted packet and the length of the transmit prea mble. With a shorter than recommended preamble detection threshold, the probability of false detection is directly related to how long the receiver operates on noise before the transmit preamble is received. False detection on noise may cause the actual packet to be missed. The preamble detection threshold may be adjusted in the modem calculator by modifying the “PM detection threshold” in the “RX parameters tab” in the radio control panel. For most app lications with a preamble length longer than 32 bits, the default value of 20 is recommended for the preamble detection threshold. A shorter Preamble Detection Threshold may be chosen if occasional false detections may be to lerated. When antenna diversity is enabled, a 20- bit preamble detection threshold is recommended. When the receiver is synchronously enabled just before the start of the packet, a shorter preamble detection threshold may be used. Table 12 demonstrates the recommended preamble detection threshold and preamble length for various modes.

Table 12. Recommended Preamble Length

1. The recommended preamble length and preamble detection thresholds listed above are to achieve 0% PER. They may

be shortened when occasional packet errors are tolerable.

1. All recommended preamble lengths and detection thresholds include AGC and BCR settling times.
2. “Standard” preamble type should be set for an alternating data sequence at the max data rate (…10101010…)
3. “Non-standard” preamble type can be set for any preamble type including …10101010...
4. When preamble detection threshold = 0, sync word needs to be 3 Bytes to avoid false syncs. When only a 2 Byte sync

1. Internal Functional Blocks

The following sections provide an overview to the key internal blocks and features. PGA for use in the AGC algorithm. reference designs on the Silicon Labs web site for more details. modulated IF. There are trade-offs between the architectures in terms of sensitivity, selectivity, and image rejection. applications. Fixed-IF obtains the best sensitivity, but it has the effect of degraded selectivity at the image frequency. An autonomous image rejection calibration is included in Si446x devices and described in more detail in "5.2.3. Figure 9. RX Architecture vs. Data Rate

30 Rev 1.2 5.2. RX Modem Using high-performance ADCs allows cha nnel filtering, image rejection, and demodulation to be performed in the digital domain, which allows for flexib ility in optimizing the device for part icular applications. The digital modem performs the following functions: Channel selection filter TX modulation RX demodulation Automatic Gain Control (AGC) Preamble detection Invalid preamble detection Radio signal strength indicator (RSSI) Automatic frequency compensation (AFC) Image Rejection Calibration Packet handling including EZMAC® features Cyclic redundancy check (CRC) The digital channel filter and demodulator are opti mized for ultra-low-power consumption and are highly configurable. Supported modulation types are GFSK, FSK, 4GFSK, 4FSK, GMSK, and OOK. The channel filter can be configured to support bandwidths ranging from 850 down to 1.1 kHz. A large variety of data rates are supported ranging from 100 bps up to 1 Mbps. The confi gurable preamble detector is used with the synchronous demodulator to improve the reliability of the sync-word detection. Preamble detection can be skipped using only sync detection, which is a valuable feature of the asyn chronous demodulator when very short preambles are used in protocols, such as MBus. The received signal stre ngth indicator (RSSI) provides a measure of the signal strength received on the tuned channel. The resolution of the RSSI is 0.5 dB. This high-resolution RSSI enables accurate channel power measurements for clear channel assessment (CCA), carrier sense (CS), and listen before talk (LBT) functionality. A compreh ensive programmable pa cket handler including key features of Silicon Labs’ EZMAC is integrated to create a variety of communication topologies ranging from peer-to-peer networks to mesh networks. The extensive programmability of the packet header allows for advanc ed packet filtering, which, in turn enables a mix of broadcast, group, and point-to-point communication. A wireless communication channel can be corrupted by noise and interference, so it is important to know if the received data is free of errors. A cyclic redundancy check (CRC) is used to detect the presence of erroneous bits in each packet. A CRC is computed and appended at the end of each transmitted packet and veri fied by the receiver to co nfirm that no errors have occurred. The packet handler and CRC can significantly reduce the load on the system microcontroller allowing for a simpler and cheaper microcontroller. The digital modem includes the TX modulator, which converts the TX data bits into the corresponding stream of digital modulati on values to be summed with the fractional input to the sigma-delta modulator. This modulation approach results in highly accurate resolution of the frequency deviation. A Gaussian filter is implemented to support GFSK and 4GFSK, considerably reducing the energy in adjacent channels. The default bandwidth-time product (BT) is 0.5 for all programmed data rates, but it may be adjusted to other values. 5.2.1. Automatic Gain Control (AGC) The AGC algorithm is implemented digitally using an advanced control loop optimized for fast response time. The AGC occurs within a single bit or in less than 2 µs. Peak detectors at the output of the LNA and PGA allow for optimal adjustment of the LNA gain and PGA gain to optimize IM3, selectivity, and sensitivity performance. 5.2.2. Auto Frequency Correction (AFC) Frequency mistuning caused by crystal inaccuracies c an be compensated for by enabling the digital automatic frequency control (AFC) in receive mode. There are tw o types of integrated freq uency compensation: modem frequency compensation, and AFC by adjusting the PLL frequency. With AFC disabled, the modem compensation can correct for frequency offsets up to ±0.25 times the IF bandwidth. When the AFC is enabled, the received signal will be centered in the pass-band of the IF filter, providing optimal sensitivity and selectiv ity over a wider range of frequency offsets up to ±0.35 times the IF bandwidth. When AFC is enabled, the preamble length needs to be long enough to settle the AFC. As shown in Table 12 on page 28, an additional byte of preamble is typically required to settle the AFC.

Rev 1.2 31 5.2.3. Image Rejection and Calibration Since the receiver utilizes a low-IF architecture, the selectiv ity will be affected by th e image frequency. The IF frequency is 468.75 kHz (Fxtal/64), an d the image frequency will be at 937.5 kHz below the RF frequency. The native image rejection of the Si446x family is 35 dB. Im age rejection calibra tion is available in the Si446x to improve the image rejection to more than 55 dB. The calibration is initiated with the IRCAL API command. The calibration uses an internal signal source, so no external signal generator is required. The initial calibration takes 250 ms, and periodic re-calibration takes 100 ms. Re-calib ration should be initiated when the temperature has changed more than 30 °C. 5.2.4. Received Signal Strength Indicator The received signal strength indicator (RSSI) is an estimate of the signal strength in the channel to which the receiver is tuned. The RSSI measurement is done after the channel filter, so it is only a measurement of the desired or undesired in-band signal power. There are two different methods for reading the RSSI value and several different options for configuring the RSSI value that is returned. The fastest method for reading the RSSI is to configure one of the four fast response registers (FRR) to return a latched RSSI valu e. The latched RSSI value is measured once per packet and is latched at a configurab le amount of time after RX mode is entered. The fast response registers can be read in 16 SPI clock cycles with no requirement to wait for CTS. The RSSI value may also be read out of the GET_MODEM_STATUS command. In this command, both the current RSSI and the latched RSSI are available. The current RSSI value represents the signal strength at the instant in time the GET_MODEM_STATUS command is processed and may be read multiple times per packet. Reading the RSSI in the GET_MODEM_STATUS command takes longer than reading the RSSI out of the fast response register. After the initial command, it will take 33 μs for CTS to be set and then the four or five bytes of SPI clock cycles to read out the respective current or latched RSSI values. The RSSI configuration options are set in the MODEM_ RSSI_CONTROL API property. The latched RSSI value may be latched and stored based on the following events: preamble detection, sync de tection, or a configurable number of bit times measured after the start of RX mode (minimum of 4 bit times). The requirement for four bit times is determined by the processing delay and sett ling through the modem and digital channel filter. In MODEM_RSSI_CONTROL, the RSSI may be defined to upda te every bit period or to be averaged and updated every four bit periods. If RSSI averag ing over four bits is enabled, the latched RSSI value will be delayed to a minimum of 7 bits after the start of RX mode to allow for the averaging. The latched RSSI values are cleared when entering RX mode so they may be read after the packet is received or after dropping back to standby mode. If the RSSI value has been cleared by the start of RX but not latched yet, a value of 0 will be returned if it is attempted to be read. The RSSI value read by the API could be translated to dBm by the following linear equation: RSSI (in dBm) = (RSSI_value /2) – RSSIcal RSSIcal in the above formula depends on the matching network, modem settings, and external LNA gain (if present). The RSSIcal value can be obtained by a simple calibration with a signal generator connected at the antenna input. Without external LNA, the value of RSSIcal is around 130 ±30. During packet reception, it may be useful to detect wh ether a secondary interfering signal (desired or undesired) arrives. To detect this event, a feature for RSSI jump detection is available. If the RSSI level changes by a programmable amount during the reception of a packet, an inte rrupt or GPIO can be configured to notify the host. The level of RSSI increase or decrease (jump) is programmable through the MODEM_RSSI_JUMP_THRESH API property. If an RSSI jump is detected, the modem may be programmed to automatically reset so that it may lock onto the new stronger signal. The chip may also be co nfigured to automatically reset the receiver upon jump detection in order to acquire the new signal. The configuration and options for RSSI jump detection are programmed in the MODEM_RSSI_CONTROL2 API property. By default, RSSI jump detection is not enabled.

corresponds to a positive offset of 8 dB. by a configurable divider, which will divide the signal down to the desired output frequency band. Note: The fc_frac/219 value in the above formula has to be a number between 1 and 2. Table 13. Output Divider (Outdiv) Values for the Si4460/61/63 Table 14. Output Divider (Outdiv) for the Si4464

Rev 1.2 33 5.3.1.1. EZ Frequency Programming In applications that utilize multiple frequencies or channels, it may not be desirable to write four API registers each time a frequency change is required. EZ frequency programming is provided so that only a single register write (channel number) is required to change frequency. A bas e frequency is first set by first programming the integer and fractional compone nts of the synthesizer. This base frequency will correspond to channel 0. Next, a channel step size is programmed into the FR EQ_CONTROL_CHANNEL_STEP_SIZE_1 and FREQ_CONTROL_CHANNEL_STEP_SIZE_0 API registers. The resulting frequency will be: The second argument of the START_RX or START_TX is CHANNEL, which sets the channel number for EZ frequency programming. For example, if the channel step size is set to 1 MHz, the base frequency is set to

900 MHz with the INTE and FRAC API registers, and a CHANNEL number of 5 is programmed during the

START_TX command, the resulting frequency will be 905 MHz. If no CHANN EL argument is written as part of the START_RX/TX command, it will default to the previous value. The initial value of CHANNEL is 0; so, if no CHANNEL value is written, it will result in the programmed base frequency. 5.3.1.2. Automatic RX Hopping and Hop Table The transceiver supports an automatic hopping feature that can be fully configured through the API. This is intended for RX hopping where the device has to hop from channel to channel and look for packets. Once the device is put into the RX state, it automatically starts hopping through the hop table if the feature is enabled. The hop table can hold up to 64 entries and is maintained in firmware. Each entry is a channel number; so, the hop table can hold up to 64 channels. The number of entri es in the table is set by RX HOP TABLE_SIZE API. The specified channels correspond to the EZ frequency programming method for programming the frequency. The receiver starts at the base channel and hops in sequence from the top of the hop table to the bottom. The table will wrap around to the base channel once it reaches the end of the table. An entry of 0xFF in the table indicates that the entry should be skipped. The device will hop to the next non 0xFF entry. There are three conditions that can be used to determine whether to continue hopping or to stay on a particular channel. These conditions are: RSSI threshold Preamble timeout (invalid preamble pattern) Sync word timeout (invalid or no sync word detected after preamble) These conditions can be used individually, or th ey can be enabled all together by configuring the RX_HOP_CONTROL API. However, the firmware will make a decision on whether or not to hop based on the first condition that is met. The RSSI that is monitored is the current RSSI value. This is compared to the thresh old, and, if it is above the threshold value, it will stay on the channel . If the RSSI is below the threshold, it will continue hopping. There is no averaging of RSSI done during the automatic hopping from channel to channel. Since the preamble timeout and the sync word timeout are features that require packet hand ling, the RSSI threshold is the only condition that can be used if the user is in “direct” or “RAW” mode where packet handling features are not used. Note that the RSSI threshold is not an absolute RSSI value; instead, it is a relative value and should be verified on the bench to find an optimal threshold for the application. The turnaround time from RX to RX on a different channe l using this method is 115 µs. The time spent in receive mode will be determined by the config uration of the hop cond itions. Manual RX hoppi ng will have the fastest turn-around time but will require more overhead and management by the host MCU. The following are example steps for using Auto Hop: 1. Set the base frequency (inte + frac) and channel step size. 2. Define the number of entries in the hop table (RX_HOP_TABLE_SIZE). 3. Write the channels to the hop table (RX_HOP_TABLE_ENTRY_n) 4. Configure the hop condition and enable auto hopping- RSSI, preamble, or sync (RX_HOP_CONTROL). 5. Set preamble and sync parameters if enabled. RF Frequency Base Frequency Channel+ Stepsi ze=

34 Rev 1.2 6. Program the RSSI threshold property in the modem using “MODEM_RSSI_THRESH”. 7. Set the preamble threshold using “PREAMBLE_CONFIG_STD_1”. 8. Program the preamble timeout property using “PREAMBLE_CONFIG_STD_2”. 9. Set the sync detection parameters if enabled. 10. If needed, use “GPIO_PIN_CFG” to configure a GPIO to toggle on hop and hop table wrap. 11. Use the “START_RX” API with channel number set to the first valid entry in the hop table (i.e., the first non 0xFF entry). 12. Device should now be in auto hop mode. 5.3.1.3. Manual RX Hopping The RX_HOP command provides the fastest method for hopping from RX to RX but it requires more overhead and management by the host MCU. Using th e RX_HOP command, the turn-around ti me is 75 µs. The timing is faster with this method than Start_RX or RX hopping because one of the calculations required for the synthesizer calibrations is offloaded to the host and must be calcul ated/stored by the host, VCO_CNT0. For information about using fast manual hopping, contact customer support. 5.4. Transmitter (TX) The Si4464/63 contains an integrated +20 dBm transmitter or power amplifier that is capable of transmitting from –20 to +20 dBm. The output power steps are less than 0.25 dB within 6 dB of max power but become larger and more non-linear close to minimum output power. The Si446 4/63 PA is designed to provide the highest efficiency and lowest current consumption possible. The Si4461 PA is capable of transmitting from –40 to +16 dBm. The Si4461 PA can be optimized for either optimum current co nsumption (Class E) or for fine output power steps and performance over voltage and temperat ure (switched-current). Switched-curre nt matching will have fine output power steps and more constant output power over VDD, but it will have higher cu rrent consumption than the class-E matching. The class E will have the most efficient current consumption, but it will have more coarse output power steps and variation across VDD. The Si4460 is designed to supply +10 dBm output power for less than 20 mA for applications that require operation from a sing le coin cell battery. The Si4460 can also operate with either class-E or switched current matching and output up to +13 dBm Tx power. All PA options are single-ended to allow for easy antenna matching and low BOM cost. Automatic ramp-up and ramp-down is automatically performed to reduce unwanted spectral spreading. Chip’s TXRAMP pin is disabled by default to save cu rrent in cases where on-chip PA will be able to drive the antenna. In cases where on-chip PA will drive the exte rnal PA, and the external PA needs a ramping signal, TXRAMP is the signal to use. To enable TXRAMP, se t the API Property PA_MODE[7] = 1. TXRAMP will start to ramp up, and ramp down at the SAME time as the internal on-chip PA ramps up/down. The ramping speed is programmed by TC[3:0] in the PA_RAMP_EX API property, which has the following characteristics: TC Ramp Time (µs) 0.0 2.0 1.0 2.1 2.0 2.2 3.0 2.4 4.0 2.6 5.0 2.8 6.0 3.1 7.0 3.4 8.0 3.7

The ramping profile is close to a linear ramping profile with smoothed out corner when approaching Vhi and Vlo. equivalent to a 10 k pull-down resistor. to the PA Matching application note. Figure 10. +20 dBm TX Power vs. PA_PWR_LVL 0x2200 PA_MODE Sets PA type. 0x2201 PA_PWR_LVL Adjust TX power in fine steps.

40 Rev 1.2 The fields are highly programmable and can be used to check any kind of pattern in a packet structure. The general functions of the packet handler include the following: Detection/validation of Preamble quality in RX mode (PREAMBLE_VALID signal) Detection of Sync word in RX mode (SYNC_OK signal) Detection of valid packets in RX mode (PKT_VALID signal) Detection of CRC errors in RX mode (CRC_ERR signal) Data de-whitening and/or Manchester decoding (if enabled) in RX mode Match/Header checking in RX mode Storage of Data Field bytes into FIFO memory in RX mode Construction of Preamble field in TX mode Construction of Sync field in TX mode Construction of Data Field from FIFO memory in TX mode Construction of CRC field (if enabled) in TX mode Data whitening and/or Manchester encoding (if enabled) in TX mode For details on how to configure the packet handler, see “AN626: Packet Handler Operation for Si446x RFICs”.

Rev 1.2 41 7. RX Modem Configuration The Si446x can easily be configured for different data rate , deviation, frequency, etc. by using the WDS settings calculator, which generates an initialization file for use by the host MCU. 8. Auxiliary Blocks 8.1. Wake-up Timer and 32 kHz Clock Source The chip contains an integrated wake-up timer that can be used to periodically wake the chip from sleep mode. The wake-up timer runs from either the internal 32 kHz RC Oscillator, or from an external 32 kHz XTAL. The wake-up timer can be configured to run when in sleep mode. If WUT_EN = 1 in the GLOBAL_WUT_CONFIG property, prior to entering sleep mode, the wake-up timer will count for a time specified defined by the GLOBAL_WUT_R and GLOBAL_WUT_M properties. At the expiration of this period, an interrupt will be generated on the nIRQ pin if this in terrupt is enabled in the INT_CTL_CHIP_ENABLE propert y. The microcontroller will then need to verify the interrupt by reading the chip interr upt status either via GET_INT_STATUS or a fast response register. The formula for calculating the Wake-Up Period is as follows: The RC oscillator frequency will change with temperature; so, a periodic recalibration is required. The RC oscillator is automatically calibrated during the POWER_UP command and exits from the Shutdown state. To enable the recalibration feature, CAL_EN must be set in the GLOBAL_WUT_CONFIG property, and the desired calibration period should be selected via WUT_CAL_PERIOD[2:0] in the same API property. During the calibration, the 32 kHz RC oscillator frequency is compared to the 30 MHz XTAL and then adjusted ac cordingly. The calibration needs to start the 30 MHz XTAL, which increases the average current consumption; so, a longer CAL_PERIOD results in a lower average current consumption. The 32 kHz XTAL accuracy is comprised of both the XTAL parameters and the internal circuit. The XTAL accuracy can be defined as the XTAL initial error + XTAL aging + XTAL temperature drift + det uning from the internal osc illator circuit. The error caused by the internal circuit is typically less than 10 ppm. WUT WUT_M 42 WUT_R

Table 15. WUT Specific Commands and Properties GLOBAL_WUT_CONFIG GLOBAL WUT configuration WUT_EN—Enable/disable wake up timer. measurement on WUT interval. 0 = Disable low duty cycle operation. WUT_CAL_PERIOD[2:0]—Sets calibration period. GLOBAL_WUT_M_15_8 Sets HW WUT_M[15:8] WUT_M—Parameter to set the actual wakeup time. GLOBAL_ WUT_M_7_0 Sets HW WUT_M[7:0] WUT_M—Parameter to set the actual wakeup time. WUT_R—Parameter to set the actual wakeup time. (Auto RX Wake-Up)" on page 43. Table 16. WUT Related API Commands and Properties INT_CTL_CHIP_ENABLE Chip interrupt enable property WUT_EN—Enables WUT interrupt.

44 Rev 1.2 8.3. Temperature, Battery Voltage, and Auxiliary ADC The Si446x family contains an integrated auxiliary AD C for measuring internal ba ttery voltage, an internal temperature sensor, or an external component ov er a GPIO. The ADC utilizes a SAR architecture and achieves 11-bit resolution. The Effective Number of Bits (ENOB) is 9 bits. When measuring external components, the input voltage range is 1 V, and the conversion rate is between 300 Hz to 2.44 kHz. The ADC value is read by first sending the GET_ADC_READING command and enabling the inputs that are desired to be read: GPIO, battery, or temp. The temperature sensor accuracy at 25 °C is typically ±2 °C. Command Stream Reply Stream Parameters TEMPERATURE_EN 0 = Do not perform ADC conversion of temperature. This will read 0 value in reply TEMPERATURE. 1 = Perform ADC conversion of temperature. This results in TEMP_ADC. Temp (°C) = TEMP_ADC[15:0] x 568/2560 – 297 BATTERY_VOLTAGE_EN 0 = Don't do ADC conversion of battery voltage, will read 0 value in reply BATTERY_ADC 1 = Do ADC conversion of battery voltage, results in BATTERY_ADC. Vbatt = 3*BATTERY_ADC/1280 ADC_GPIO_EN 0 = Don't do ADC conversion on GPIO, will read 0 value in reply 1 = Do ADC conversion of GPIO, results in GPIO_ADC. Vgpio = GPIO_ADC/GPIO_ADC_DIV where GPIO_ADC_DIV is defined by GPIO_ATT selection. ADC_GPIO_PIN[1:0] - Select GPIOx pin. The pin must be set as input. 0 = Measure voltage of GPIO0 1 = Measure voltage of GPIO1 2 = Measure voltage of GPIO2 3 = Measure voltage of GPIO3 UDTIME[7:4] - ADC conversion Time = SYS_CLK / 12 / 2^(UDTIME + 1). Defaults to 0xC if ADC_CFG is 0. GET_ADC_READING Command 765 4 3 2 1 0 CMD 0x14 ADC_EN 0 0 0 TEMPERATURE_EN BATTERY_VOLTAGE_ EN ADC_GPIO_EN ADC_GPIO_PIN[1:0] ADC_CFG UDTIME[3:0] GPIO_ATT[3:0] GET_ADC_READING Reply 76543210 CTS CTS[7:0] GPIO_ADC GPIO_ADC[15:8] GPIO_ADC GPIO_ADC[7:0] BATTERY_ADC BATTERY_ADC[15:8] BATTERY_ADC BATTERY_ADC[7:0] TEMP_ADC TEMP_ADC[15:8] TEMP_ADC TEMP_ADC[7:0] RESERVED Reserved RESERVED Reserved

Rev 1.2 45 Selecting shorter conversion times will result in lower ADC resolution and longer times will result in higher ADC resolution. GPIO_ATT[3:0] - Sets attenuation of gpio input voltage when vgpio measured. Defaults to 0xC if ADC_CFG is 0. 0x0 = ADC range 0 to 0.8V. GPIO_ADC_DIV = 2560 0x4 = ADC range 0 to 1.6V. GPIO_ADC_DIV = 1280 0x8 = ADC range 0 to 2.4V. GPIO_ADC_DIV = 853.33 0x9 = ADC range 0 to 3.6V. GPIO_ADC_DIV = 426.66 0xC = ADC range 0 to 3.2V. GPIO_ADC_DIV = 640 Response GPIO_ADC[15:0] - ADC value of voltage on GPIO BATTERY_ADC[15:0] - ADC value of battery voltage TEMP_ADC[15:0] - ADC value of temperature sensor voltage RESERVED[7:0] - RESERVED FOR FUTURE USE RESERVED[7:0] - RESERVED FOR FUTURE USE 8.4. Low Battery Detector The low battery detector (LBD) is enabled and utilized as part of the wake-up-timer (WUT). The LBD function is not available unless the WUT is enabled, but the host MCU c an manually check the battery voltage anytime with the auxiliary ADC. The LBD function is enabled in the GLOBAL_WUT_CONFIG API property. The battery voltage will be compared against the threshold each time the WUT ex pires. The threshold for the LBD function is set in GLOBAL_LOW_BATT_THRESH. The threshold steps are in increments of 50 mV, ranging from a minimum of 1.5 V up to 3.05 V. The accuracy of the LBD is ±3%. The LBD notification can be configured as an interrupt on the nIRQ pin or enabled as a direct function on one of the GPIOs. 8.5. Antenna Diversity To mitigate the problem of frequency-selective fading due to multipath propagation, some transceiver systems use a scheme known as antenna diversity. In this scheme, two antennas are used. Each time the transceiver enters RX mode the receive signal strength from each antenna is evaluated. This evaluation process takes place during the preamble portion of the packet. The antenna with the stro ngest received signal is then used for the remainder of that RX packet. The same antenna will also be used for the next corresponding TX packet. This chip fully supports antenna diversity with an integrated antenna diversity control algorithm. The required signals needed to control an external SPDT RF switch (such as a PIN diode or GaAs switch) are available on the GPIOx pins. The operation of these GPIO signals is programmable to allow for different antenna diversity architectures and configurations. The antdiv[2:0] bits are found in the MODEM_ANT_DIV_CONTROL API property descriptions and enable the antenna diversity mode. The GPIO pins are capable of sourcing up to 5 mA of current; so, it may be used directly to forward-bias a PIN diode if desired. The antenna diversity algorithm will au tomatically toggle back and forth between the antennas until the packet starts to arrive. The recommended preamble length for optimal antenna selection is 8 bytes.

46 Rev 1.2 9. Pin Descriptions: Si4464/63/61/60 Pin Pin Name I/0 Description 1S D N I Shutdown Input Pin. 0–VDD V digital input. SDN should be = 0 in all modes except Shutdown mode. When SDN = 1, the chip will be completely shut down, and the contents of the registers will be lost. 2R X p I Differential RF Input Pins of the LNA. See application schematic for example matching network.3R X n I 4T X O Transmit Output Pin. The PA output is an open-drain connection, so the L-C match must supply VDD (+3.3 VDC nominal) to this pin. 5N C No Connect. Not connected internally to any circuitry. 6V D D V D D +1.8 to +3.6 V Supply Voltage Input to Internal Regulators. The recommended VDD supply voltage is +3.3 V. 7 TXRAMP O Programmable Bias Output with Ramp Capability for External FET PA. See "5.4. Transmitter (TX)" on page 34. 8V D D V D D +1.8 to +3.6 V Supply Voltage Input to Internal Regulators. The recommended VDD supply voltage is +3.3 V. 9 GPIO0 I/O General Purpose Digital I/O. May be configured through the registers to perform various functions including: Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery Detect, TRSW, AntDiversity control, etc.

10 GPIO1 I/O

General Microcontroller Interrupt Status Output. When the Si4463/61 exhibits any one of the interrupt events, the nIRQ pin will be set low = 0. The Microcontroller can then determine the state of the inter- rupt by reading the interrupt status. No external resistor pull-up is required, but it may be desirable if multiple interrupt lines are connected. GND PAD 17181920 6 7 8 9 GND GPIO1 nSEL SDI SDO SCLKNC SDN TX GPIO0 VDD nIRQ RXp RXn XIN GPIO3 GPIO2 XOUT TXRamp VDD

Rev 1.2 47

12 SCLK I

Serial Clock Input. 0–VDD V digital input. This pin provides the serial data clock function for the 4-line serial data bus. Data is clocked into the Si4463/61 on positive edge tran- sitions.

13 SDO O

0–VDD V Digital Output. Provides a serial readback function of the internal control registers.

14 SDI I

Serial Data Input. 0–VDD V digital input. This pin provides the serial data stream for the 4-line serial data bus. 15 nSEL I Serial Interface Select Input. 0–VDD V digital input. This pin provides the Select/Enable function for the 4-line serial data bus.

16 XOUT O

Crystal Oscillator Output. Connect to an external 25 to 32 MHz crystal, or leave floating when driving with an external source on XIN. 17 XIN I Crystal Oscillator Input. Connect to an external 25 to 32 MHz crystal, or connect to an external source. 18 GND GND Connect to PCB ground. 19 GPIO2 I/O General Purpose Digital I/O. May be configured through the registers to perform various functions, including Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery Detect, TRSW, AntDiversity control, etc.

20 GPIO3 I/O

PKG PADDLE_GND GND The exposed metal paddle on the bottom of the Si446x supplies the RF and cir- cuit ground(s) for the entire chip. It is very important that a good solder connec- tion is made between this exposed metal paddle and the ground plane of the PCB underlying the Si446x. Pin Pin Name I/0 Description

48 Rev 1.2 10. Ordering Information Part Number1,2 Description Package Type Operating Temperature Si4464-Bxx-FM ISM EZRadioPRO Transceiver QFN-20 Pb-free –40 to 85 °C Si4463-Bxx-FM ISM EZRadioPRO Transceiver QFN-20 Pb-free –40 to 85 °C Si4461-Bxx-FM ISM EZRadioPRO Transceiver QFN-20 Pb-free –40 to 85 °C Si4460-Bxx-FM ISM EZRadioPRO Transceiver QFN-20 Pb-free –40 to 85 °C Notes: 1. Add an “(R)” at the end of the device part number to denote tape and reel option. 2. For Bxx, the first “x” indicates the ROM version, and the second “x” indicates the FW version in OTP.

Table 17. Package Dimensions

1. All dimensions are shown in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220,
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C

specification for Small Body Components.

Table 18. PCB Land Pattern Dimensions

1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal

walls should be used to assure good solder paste release.

1. The stencil thickness should be 0.125 mm (5 mils).
2. The ratio of stencil aperture to land pad size should be 1:1 for the
3. A 2x2 array of 1.10 x 1.10 mm openings on 1.30 mm pitch should be

used for the center ground pad.

1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020

specification for small body components.

Rev 1.2 53 13. Top Marking 13.1. Si4464/63/61/60 Top Marking 13.2. Top Marking Explanation Mark Method YAG Laser Line 1 Marking Part Number 44641B = Si4464 Rev 1B1 44631B = Si4463 Rev 1B1 44611B = Si4461 Rev 1B1 44601B = Si4460 Rev 1B1 Line 2 Marking TTTTT = Internal Code Internal tracking code. 2 Line 3 Marking YY = Year WW = Workweek Assigned by the Assembly House. Corresponds to the last significant digit of the year and workweek of the mold date. Notes: 1. The first letter after the part number is part of the ROM revision. The last letter indicates the firmware revision. 2. The first letter of this line is part of the ROM revision.

54 Rev 1.2 DOCUMENT CHANGE LIST Revision 0.4 to Revision 1.0  Updated Table 3 on page 6.  Updated Table 6 on page 12.  Updated Figure 13 on page 37.  Replaced Table 12 on page 28.  Updated "11. Package Outline: Si4464/63/61/60" on page 49. Revision 1.0 to Revision 1.1  Updated RX Mode Current in Table 1 on page 4.  Updated Synthesizer Frequency Range in Table 2 on page 5.  Updated RX Frequency Range and RX Sensitivity in Table 3 on page 6.  Updated TX Frequency Range in Table 4 on page 9.  Updated Temperature Sensor Sensitivity in Table 5 on page 11.  Updated Drive Strength in Table 6 on page 12.  Updated Figure 1 and Figure 2 on page 16.  Updated "3.2. Fast Response Registers" on page 19.  Updated Table 9 on page 20.  Updated Figure 9 on page 29.  Updated "5.2.4. Received Signal Strength Indicator" on page 31.  Updated "5.4. Transmitter (TX)" on page 34.  Updated "8.3. Temperature, Battery Voltage, and Auxiliary ADC" on page 44.  Updated "9. Pin Descriptions: Si4464/63/61/60" on page 46.  Updated "11. Package Outline: Si4464/63/61/60" on page 49. Revision 1.1 to Revision 1.2  Updated all instances of frequency range for Si4463/61/60 and Si4464, primarily in the electrical specifications Tables.  Removed emissions and harmonics specifications from the electrical specifications.  Updated Tables 13 and 14 to reflect frequency coverage.  Updated “13.1. Si4464/63/61/60 Top Marking”.  Updated “9. Pin Descriptions: Si4464/63/61/60” for pins 16 and 17.

Rev 1.2 55 NOTES:

56 Rev 1.2 CONTACT INFORMATION Silicon Laboratories Inc.

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