3256

3256 LATTICE | Alldatasheet

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oo . a Specifications ispLS/ and oe 3256 on r} ® @ Lattice ispLSI°and pLSI° 3256 auaaeecemiconductor i H

118 TtE Corporation High Density Programmable Logic

$$ SSSsSsSSSSSSSSsSSSSSSSSSSSSSSSSSSSSSSS Features Functional Block Diagram + HIGH-DENSITY PROGRAMMABLE LOGIC Do nit GnGD oman Gee — 128 VO Pins S Paria — 11000 PLD Gates [rs] JOn][vo] _ [os}(ea)(ei][eo) [le — 384 Registers = — High Speed Global Interconnect En F3 ia 38 — Wide Input Gating for Fast Counters, State fg oa |F4 28 Machines, Address Decoders, etc. ba a Aray Ey — Small Logic Block Size for Random Logic Bs i A + HIGH PERFORMANCE E*CMOS® TECHNOLOGY Be] ig FI Be — fmax = 77 MHz Maximum Operating Frequency IS — tpd = 15 ns Propagation Delay < F — TTL Compatible Inputs and Outputs as ra Bl z — Electrically Erasable and Reprogrammable aie way |P | baie — Non-Volatile ER (al HlE8 — 100% Tested at Time of Manufacture F 2 2 FI — Unused Product Term Shutdown Saves Power 2 Global Routing Poot I + ispLSI OFFERS THE FOLLOWING ADDED FEATURES fis eg — In-System Programmable™ (ISP™) 5-Volt Only [Bo] — Increased Manufacturing Yields, Reduced Time-to- 2 = c2][cs] [0] ay [ea] [o3] Market, and Improved Product Quality . duh, — Reprogram Soldered Devices for Faster Debugging ory * 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE Description * OFFERS THE EASE OF USE AND FAST SYSTEM - - . SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY The ispLSI and pLSI 3256 are High Density Program- OF FIELD PROGRAMMABLE GATE ARRAYS mable Logic Devices which contain 384 Registers, 128 — Complete Programmable Device Can Combine Glue _ Universal I/O pins, five Dedicated Clock Input Pins, eight Logic and Structured Designs Output Routing Pools (ORP), and a Global Routing Pool — Five Dedicated Clock Input Pins (GRP) which allows complete inter-connectivity between — Synchronous and Asynchronous Clocks all ofthese elements. The ispLS! 3256 features 5-Volt in- _ programmable Output Stew Rate Control to Mink system programmability and in-system diagnostic _ Flexible Pin Plocement capabilities. The ispLSI 3256 offers non-volatile “on-the- — Optimized Global Routing Poo! Provides Global fly" reprogrammability of the logic, as well as the Interconnectivity interconnect to provide truly reconfigurable systems. Itis + ispLS! AND pLSI DEVELOPMENT TOOLS architecturally and parametrically compatible to the pLSI pDS® Software evices. — Easy to Use PC Windows™ Interface The basic unit of logic on the ispLSI and pLSI 3256 — Boolean Logic Compiler devices is the Twin Generic Logic Block (Twin GLB) — Manual Partitioning labelled AO, A1...H3. There are a total of 32 of these Twin — Automatic Place and Route GLBs in the ispLS! and pLS! 3256 devices. Each Twin — Static Timing Table GLB has 24 inputs, a programmable AND array and two ispDS+™ Software - OR/Exclusive-OR Arrays, and eight outputs which can _ paustry Standar 4, Third Party Design be configured to be either combinatorial or registered. All vironments iT i — Schematic Capture, State Machine, HDL Twin GLB inputs come from the GRP. — Automatic Partitioning and Place and Route — Comprehensive Logic and Timing Simulation — PC and Workstation Platforms Copyright® 1997 Latice Semiconductor Corp. Allrand or product names are trademarks or registered vademarks of heirrespe tivehoders, The specifications and ivormation herein are subject to change without note. Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; htto://www.latticesemi.com ISP Encyclopedia 3256_03 1 1996 ISP Encylopedia M@ 5386949 0005774 T2b a

Figure 1. ispLSI and pLSI 3256 Functional Block Diagram

7LAllice Specifications ispLSI and pLSI 3256 ansees Corporation Description (continued) All local logic block outputs are brought back into the Clocks in the ispLSI and pLSI 3256 devices are provided GRP so they can be connected to the inputs of any other through five dedicated clock pins. The five pins provide logic block on the device. The device also has 128 I/O _ three clocks to the Twin GLBs and two clocks to the I/O cells, each of which is directly connected to an I/O pin. cells. Each W/O cell can be individually programmed to be a . . combinatorial input, a registered input, alatched input, an The table below lists key attributes of the device along output or a bidirectional /O pin with 3-state control. The with the number of resources available. signal levels are TTL compatible voltages and the output ™ ' drivers can source 4 mA or sink 8 mA. Each output can Ba saationa I feature ome ‘sore anos oe is re be programmed independently for fast or slow output ry Scan capability, . pose s slew rate to minimize overall output switching noise. connected between the on-chip system logic and the . device's input and output pins. All I/O pins have associ- The 128 V/O Cells are grouped into eight sets of 16 bits. ated boundary scan registers, with 3-state V/O using three Each of these I/O groups is associated with a logic boundary scan registers and inputs using one. Megablock through the use of the ORP. These groups of -

16 I/O cells share one Product Term Output Enable which Addis trae olan Seek suppers ASS Sieet

is associated with a specific pair of Megablocks and two and S MELE " , Global Output Enables. “ Four Twin GLBs, 16 I/O Cells and one ORP are con- [DQ EMULE CS SUES TESTS ESS nected together to make a logic Megablock. The Megablock is defined by the resources that it shares. The [Attribute [Quantity | outputs of the four Twin GLBs are connected to a set of 16 VO cells by the ORP. The ispLSI and pLS! 3256 | Twin GLBs The GRP has as its inputs the outputs from allof the Twin | /O Pins GLBs and all of the inputs from the bidirectional I/O cells. Global Clock: All of these signals are made available to the inputs of the | GlobalCiocks TC Twin GLBs, Delays through the GRP have been equal- |GobacE | ized to minimize timing skew and logic glitching. Test OE 0sAisp/9256 3 1996 ISP Encylopedia MM 53486949 0005776 4T5

“Lattice ications i EESt Somiecndentor Specifications ispLSI and pLSI 3256 wunens Corporation SSS Absolute Maximum Ratings 1 Storage Temperature... 5 to 150°C 1. Stresses above those listed under the “Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specific tion is not implied (while programming, follow the programming specifications). DC Recommended Operating Condition SYMBOL PARAMETER [ min. | max. | unrrs | Supply Voltage “Table 2- 000870258 Capacitance (T,=25°C,f=1.0 MHz) SYMBOL PARAMETER [maximum'] UNITS | TEST CONDITIONS 1. Guaranteed but not 100% tested. Table 2 oo06.8256 Data Retention Specifications PARAMETER winimum [Maximum [uns | pLSI Erase/Reprogram Cycles 100 - Cycles as oO — Table 2- 00088 mS 4 1996 ISP Encylopedia M@™ 5386949 0005777 735 a

one . Lattice ifications i HTS cnaweter Specifications ispLSI and pLSI 3256

221225 Corporation

a Switching Test Conditions Input Pulse Levels GND to 3.0V Figure 2. Test Load Input Rise and Fall Time <3ns 10% to 90% +5V Input Timing Reference Levels a Ouput Timing Reference Levels 1 Output Load See figure 2 Device Test Table 20003 Output Point 3-state levels are measured 0.5V from steady-state active level. Ro T o* Output Load conditions (See figure 2) *oL includes Test Fixture and Probe Capacitance. casa Testconomion | _At_| rz | co | pay | 4700 | ss00 | apr 3908 | 85pF Active High to Z ¢ fawmem? | = [eco | oo | Active Low to Z Tab B-OOGT Over Recommended Operating Conditions Output Low Voltage inzemA | | foe |v Output High Voltage [loy=-ama | ea | TK Input or VO Low Leakage Current OVS VS Vi (Max.) [ - | - | -t0 | pa | Input or /O High Leakage Current 3.5V < Vins Voc | - | - [| 10 [ ya | livisp _ | Bscan/ispEN input Low Leakage Current OV < Vivs Vit | - | - | 150] na | li-pu | VO Active Pull-Up Current OV < Vs Vi. [ = | - | -150 | ya | Output Short Circuit Current Veo= 5V, Vour= 0.5V [| - | - | -200| ma | 2A , Vi= O.0V, Viy= 3.0V Icc’ Operating Power Supply Current te 150 | 270 | mA Table 2 0007S 1. One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground degradation. Guaranteed but not 100% tested. 2. Measured using sixteen 16-bit counters. 3. Typical values are at Voc = SV and Ta = 25°C. 4. Maximum Igc varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this datasheet and Thermal Management section of this Data Book to estimate maximum Igo. 5 1996 ISP Encylopedia M™ 5346949 0005778 b7]

“Lattice Specifications ispLSI and pLSI 3256 =2228 Corporation —$ eS Over Recommended Operating Conditions | [e[ en‘ [tos1_ |__| 1 [ Data Propagation Delay, 4PT Bypass, ORP Bypass | - [150] - [200] ans _| [toaz | A | 2[DataPropegatonDeay dt = dt) - 0] ns | [Ymax | A_| 8 | Cook Frequency wihntraiFeosbacr® ‘| | - [ar | - | wae | [fmax ext) | - [4 | Glock Frequency with Exemal Feedback (sama) | 60 | — | 37 | - | wie | [Ymex Tog) | [5 | Crook Frequency: Max Toooe® «ite | = pos | — | wie | [toui____|_— [6 | G1 eg. Setup Tine below Cook APT Bypass | as | - [128] - | ws | [teo1 | A_| 7 [ 8 Reg. Gecko Output Oeay,ORP Bypass | - | 90| - [120] ns | [tir |= Ts | 616 Reg. Hot Tine ator Cook 4 PTBypass | 00] - [oo] - | ms | jtsve |= [9 | cis reg. Setup Time before Ciock [14.0 — [150] - | ns _| [tooe | [10 | GLB Reg. Ciockto Ouput Delay | = [108] - [140] ns | [ti [= [rr] ots reg HolsTine ator Cick ——~—S*idt | = ‘poo - | oe | [twi [= [16] Ext Reset Pulse Durston ———=SSCS~S~«~ TO ‘| t88| - | nw | [Yorosen |B [14] iputtoOuiptenable ————S~S~wC ‘no | [2 |e] [Roiects | C[15] puto Out isabe———SSS*d C= ‘ft | — [205 | vw | [taocen | 8 | 16] Gloval OF Ouputenabie———SSCS~S~S~S~s ng) = v8 | ew | [tooecis [6 [17] aobal O€ ouput Disa ———SSSSCS~d Co = [008 | re | [ttoven [8 [718] Test Oupuienabo ——SSSCS~S~S~sd C7] fen || [feeds | ~C[19) Teste Ouputdsenle———SSSS*d ‘|r| ~ [200] ne | [tun |= [20] External Synctronous Cock Puse Guraion High | 60| - | @0| - | 1s | [tw | = [21] External Syncironous Cock Puse Duration, iw | 60 | = [80 | — | rs | [tad |= [22/10 Reg. Soup Time before Ext. Sy. Cook (VS, 4) | 50 | = | 70] = | vs | [tho |= [28] v0 Reg. Hold Te afar Ex. Syne. Cock (v8.4) | 00 | = | 00 | = | vs | 1. Unless noted otherwise, all parameters use 20 PTXOR path and ORP. Table 2 - 00S0A/3256 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-bit counter using GRP feedback. 4. imax (Toggle) may be less than 1/(twh + tw). This is to allow for a clock duty cycle of other than 50%. 5. Reference Switching Test Conditions section. ee 6 1996 ISP Encylopedia MM 5366949 0005779 SoS a

i: LAllice Specifications ispLSI and pLSI 3256 =i nee= Corporation a SeeeSSeSSSSSSSSSSSSSSSSSSSSSSSSSSSSeeeeeeeeeee Internal Timing Parameters Over Recommended Operating Conditions PARAMETER | # DESCRIPTION “anc pon ta oS | tiosp __| 24 | v0 Register Bypass | - |24] - [33] ns | Pet [2 |v Late tay [= [ee[ = [ss [re | | tiosy _| 26 | VO Register Setup Time before Clock [ez] - [se[- | ns | | tioco | 28 | V0 Register Clock to Out Delay | - [19 | - 26 | as _| [tr | 20] 0 Register Reset o Out Delay [= [ast - [49] 1s | [tum [30 | GAP Delay | = [so] - [ar [ns] [tows [Si] #Proaua Ter Bypass Path bety _——=—SS—S~d CS ee t20ptvor 20 Product Term/XOR Path Delay [ - [74] - [101] ns | XOR Adjacent Path Delay? | = [es] - [ata] ns | [toss | 98 GL Register Setup Te bor Cock [ae] - [aa] - [ne | GLB Register Clock to Output Delay | - [18] - [22 | ns_| | taro __| 30 | GLB Register Reset to Output Delay | - [28] - [3a | ns | GLB Product Term Output Enable to VO Cell Delay | - [54] - [73] ns | [tow [8 [ORP Baap [= [27] - [ee [e_] 1. Internal Timing Parameters are not tested and are for reference only. Table 2 O0S6A/S256 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Se 7 1996 ISP Encylopedia M@™ 5386949 0005780 227 a

See TT Somioondueter Specifications ispLSI and pLSI 3256 tunes Corporation a Internal Timing Parameters! Over Recommended Operating Conditions PARAMETER DESCRIPTION mea UNITS [tobe [ Outta Doay [- [ea[ = [ss] | [tots | 4 ouput ute Doay, Stow Sow [= [real = [109] | | toais _| 48 | vo Gell OF to Output Disabled | - [72] - [es] ns _| tayo/t2 [49] Clock Delay, YO or Yt or ¥2 to Global GLB Clock Line [36] 36|49[ 49] ns | Clock Delay, Y3 or Y4 to VO Cell Global Clock Line [i2|[s2fiel7o[n | Global Reset Global Reset to GLB and /O Registers [- [71 [ - [oe] ns _| 1. Internal Timing Parameters are not tested and are for reference only. Table 2 0S7AIS256 2. Refer to Timing Model in this data sheet for further details. ee 8 1996 ISP Encylopedia MH 5386949 0005781 lbb mm

LAllice Specifications ispLSI and pLSI 3256 s88225 Corporation SSMS ispLSI and pLSI 3256 Timing Model vO Col GRP ais onP vO Cel oo eS Ss Feedback GO Pin» LO Rea Bypass CORP Bypass > LOT input) oer | Rll Pay eqs (ua Input 20 PT GLB Reg ORP b Register XOR Delays Delay Delay [Reset > W98-99 ‘Control RE] PTs OE] [s0E0.1» consi Derivations of tsu, th and tco from the Product Term Clock! tsu = Logic + Reg su - Clock (min) = (tiobp + tgrp + t20ptxor) + (tgsu) - (tiobp + tgrp + tptck(min)) th = Clock (max) + Reg h - Logic = (tiobp + tgrp + tptck(max)) + (tgh) - (tiobp + tgrp + t20ptxor) tco = Clock (max) + Reg co + Output = (tiobp + tgrp + tptck(max)) + (tgco) + (torp + tob) Table 2- 0042-16/3256 Note: Calculations are based on timing specs for the ispLS! 3256-70L. SSS 9 1996 ISP Encylopedia M™ 5386949 0005782 OTe mm

Figure 3. Typical Device Power Consumption vs fmax Program in the device, the actual ICC should be verified.

even when the power is turned off. section in this Data Book. on-chip programming circuitry where a state machine _ is generated when a read ID command is performed. Figure 4. ISP Programming Interface

“Lattice Specifications ispLSI and pLSI 3256 sane s Corporation eee ispLSI 3256 Shift Register Layout D D A A T T A A Data In >>| 337... High Order Shift Register 20 Z (spl) "| }-+[676... Low Order Shift Register 338|-»/ SPO SDI 179 o a E2CMOS Cell Array ° Zz =| | 2 | | Qiy SDO oreanrease Note: A logic “1” in the address shift register enables the row for programming or verification. A logic “0” disables it. 12 1996 ISP Encylopedia M@™ 5366949 0005785 501 a

the Test Access Port (TAP). The TAP consists of a thru 100 to 1064 thru 10127 to TDO. . - below. The waveforms are shown in figure 5. (TMS), Test Reset (TRST) and Test Clock (TCK). Figure 5. Boundary Scan Waveforms

7 Laulice Specifications ispLSI and pLSI 3256

[NAME | MQFP PIN NUMBERS DESCRIPTION VO0-VO4 25, 26, 28, 29, 30, InpuvOutput Pins - These are the general purpose I/O pins used by the VO5-VO9 32, 33, 34, 35, 36, logic array. VO10-VO14 37, 38, 39, 40, 41, V0 15-VO19 42, 43, 44, 46, 47, VO 20-024 48, 49, 50, 52, 53, VO 25-029 54, 55, 56, 57, 58, VO 30 - O34 59, 60, 61, 62, 64, VO 35 - V039 65, 66, 67, 68, 69, VO 40 -/044 70, 72, 73, 74, 75, VO 45 - VO.49 76, 77, 78, 79, 80, VO50-V/O54 82, 83, 84, 85, 86, VO 55-VO59 87, 88, 89, 90, 92, VO 60 - VO 64 93, 94, 95, 96, 105, VO 65 - VO69 106, 108, 109, 110, 112, VO70-VO74 4113, (114, «115, 116, 117, VO75-VO79 118, 119, 120, 121, 122, VO 80 - /0.84 123, 124, 126, 127, 128, VO 85 - /0 89 129, 130, 132, 133, 134, VO90 - VO94 135, 136, 137, 138, 139, VO 95 - /O99 140, 141, 142, 144, 145, VO 100 - I/O 104 146, 147, 148, 149, 150, VO 105 - /0 109 152, 153, 154, 155, 156, VO 110-0 114 157, 158, 159, 160, 2, VO 115-0119 3, 4, 5, 6, 7, VO 120 - /0 124 8, 9, 11, 13, 14, VO 125 - VO 127 15, 16, 17 GOEO and GOE1 100 and 99 Global Output Enable input pins. TOE 98 Test output enable pin. RESET 20 Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device, YO, Y1 and Y2 18, 19, 103 Dedicated Clock inputs. These clock inputs are connected to one of the clock inputs of all the GLBs on the device. Y3 and Y4 102, 101 Dedicated Clock inputs. These clock inputs are connected to one of the clock inputs of all the I/O cells in the device. BSCAN/ispEN™* 4 Boundary Scan Enable. Input - Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK options become active. ToYSDI* 22 Input - This pin performs two functions. It is the Test Data input pin when ispEN Is logic high. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI is also used as ‘one of the two control pins for the isp state machine. TCLK/SCLK* 23 Input - This pin performs two functions. It is the Test Clock input pin when ispEN is logic high. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. TMS/MODE* 24 Input - This pin performs two functions. It is the Test Mode Select input pin when ispEN is logic high. When ispEN is logic low, it functions as pin to control the operation of the isp state machine. TRST 97 Input - Test Reset, active low to reset the Boundary Scan State Machine. TDO/SDO* 104 Output - This pin performs two functions. When ispEN is logic low, it functions as the pin to read the isp data. When ispEN is high it functions as Test Data Out. GND 1, 10, 27, 45, 63, Ground (GND) 81, 107, 125, 143 | vec 12, 31, 51, 71, 91, | Veo 414, 134, 151 | ~ ‘Table 2 - 0002Bisp/3256 * ispLSI 3256 only ** ispEN for ispLSI 3256 only, NC for pLSI 3256 must be left floating or tied to Veg, must not be grounded or tied to any other signal. ee 14 1996 ISP Encylopedia Mm 5386949 0005787 684

He -allice Specifications ispLSI and pLS!I 3256

222252 Corporation

[NAME | CPGA PIN NUMBERS DESCRIPTION VOO-VO4 Gi, G2, G3, Et, Fa, Input/Output Pins - These are the general purpose I/O pins used by the VO5-VO9 F3, Ct, E2, E3, D2, logic array. VO10-V0 14 D3, B2, C3, C4, B3, VO15-VO19 Bi, B4, C5, AS, B5, VO 20 - VO 24 C6, Ad, B6, AS, c7, VO 25 - VO 29 AG, AT, ce, BB, Bo, VO 30 - VO 34 co, AY, A1i0, B10, Alt, VO 35 - VO 39 Bil, At2, C11, A13, B12, VO 40 - VO 44 Al4, A15, At16, C13, B14, VO 45 - VO 49 B15, C14, B16, C15, 15, VO 50 - VO 54 A17, 016, E15, BI7, C17, VO 55 - VO 59 E16, 15, D17, «E17, FA7, VO 60 - VO 64 Gi6, G17, H15, H16, 16, VO 65 - VO 69 M17, N17, M16, P17, R17, VO 70 -VO74 N16, Si7, N15, P16, P15, VO 75 - VO 79 $16, R15, Ri4, S15, 17, VO 80 - /O 84 $14, R13, 115, $13, R12, VO 85 - V0 89 714, $12, 113, Rit, 12, VO 90 - VO 94 TH, R10, S10, S9, Ro, VO 95 - /0 99 T9, 8, S8, T7, s7, WO 100 - VO 104 6, RZ, 15, $6, T4, WO 105 - VO 109 3, = 2, RS, S4, $3, VO 110 - VO 114 R4, S2, RS, PS, 11, VO 115 - VO 119 P2, N3, St, Ri, N2, VO 120 - VO 124 M3, P41, Nt, Mi, La, VO 125 - VO 127 ut, K3, K2 GOEO and GOE1 J17 and J15, Global Output Enable input pins. TOE J16 Test output enable pin. RESET J3 Active Low (0) Reset pin which resets all of the GLB and V/O registers in the device. YO, Y1 and Y2 Kt, J2, K15 Dedicated Clock inputs. These clock inputs are connected to one of the clock inputs of all the GLBs on the device. Y3 and Y4 K16, K17 Dedicated Clock inputs. These clock inputs are connected to one of the clock inputs of all the /O cells in the device. BSCAN/ispEN** Jt Boundary Scan Enable. Input - Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK options become active. TOVSDI* Ht Input - This pin performs two functions. It is the Test Data input pin when TspEN is logic high. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI is also used as ‘one of the two control pins for the isp state machine. TCLK/SCLK* H2 Input ~ This pin performs two functions. It is the Test Clock input pin when ispEN is logic high. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. ‘TMS/MODE* HS Input - This pin performs two functions. It is the Test Mode Select input pin when ispEN is logic high. When ispEN is logic low, it functions as pin to control the operation of the isp state machine. TRST HI7 input - Test Reset, active low to reset the Boundary Scan State Machine. TDO/SDO* u7 Output - This pin performs two functions. When ISpEN is logic low, it functions as the pin to read the isp data. When ispEN is high it functions as Test Data Out. | GND FA, C2, A2, B7, C10, Ground (GND) B13, C16, F16, L15, R16, | M2 | veo D1, A8, G15, C12, M15, Veo T10, 13, R6 ~ — ™ ~ ‘Table 2 - 0002isp/3256 * ispLSI 3256 only ™ ispEN for ispLS! 3256 only, NC for pLS! 3256 must be left floating or tied to Veg, must not be grounded or tied to any other signal. ee 15 1996 ISP Encylopedia M@™@ 5346949 0005748 S10 a

oan . #Lattice ifications i TH ietSoaconametes Specifications ispLSI and pLSI 3256 tisss Corporation ——— SSSSSSSSSSSSSSSSSesee Pin Configuration ispLSI and pLSI 3256 160-pin MQFP. ZEESSSESS SSSSSea asses essRBBs. SSSSIq5BRR BeaeegegeseesscogseoeseesocesSoegoescces OOO000000noNNnNn ANNAN ANNNNNNONANANAONon SSSESRSERERETESTELTELSSSSSSASSSSRSRSR NS e ono 1 10f5 wo77 vor G2 11955 vor vous Ca 11855 075 vors Ga 11765 vor vor? Is 11655 wore voris Gs 11565 vor vors G7 11465 vo7t vorz0 Ce 11355 v070 vora C9 11265 voes en | 10 11 vee vor Gn 110 vo08s vee E12 109 voer vores Chia 10855 voss vor v4 1075 ono vors Cis 1085 voes vo 126 C416 . 1055 ose toe Glu ispLSI 3256 tee Tooro0 _ vi ie 10255 va noo, 52 pLSI 3256 SP ie sTpusDi S| 22 995 Goet “rsnnooe >t Top View ov Test vo0 Ej 25 9655 vo6s vor Chas 955 vo8 eno Cl 27 98[5 vost vo2 C20 35 v6 wos G20 #25 059 v0.4 Cj o0 91 vee vee S]a1 90/5 vose vos Gi a2 99f5 vos voe Ha #5 ose vor S34 a7 oss vos Clas 2855 ose vos C136 2565 vos vowo Cl s7 3455 vos vor C28 > vost vo12 Gfas #215 vos vo1s E40 11 ano EPPTISESISFSRSSSERSISESESSSSSEKHRERERLLS UUUUUUUUUCUUUUUU UCU Do ELSES SARANYRARKRRASSSBISRRHSSSYSITTLSESS Seggecogee=oeceeocogessogogggsseagegeses *Pins have dual function capability for ispLSI 3256 only. or eee 16 1996 ISP Encylopedia WM 5386949 0005789 4S?

aLatlice Specifications ispLSI and pLSI 3256 CISISICICISISISICICICICNICICNCIONE ISIS IOISISISISISISCICISISISICIC) CIOISICISIOISICISISCISICISISISICNS) QOS? OOO} © ©) ©}: © © &|s ispLSI 3256 © © @) pLSI 3256 @ @ @): Ore) Bottom View @2) Co) |x Oe} OOO 69 @) ©" SISIS Ih SISIT SIOISITISISICISICICISIOISISIS ICIS) IIIS ISICIOISISISICISIONS IS ISIS) SIOICICISICICICICICICISISICICISIS

HLAUUICE Specifications ispLSI and pLS!I 3256 IIEIE Corporation a Part Number Description (isjpLS| 3256- XX X X X Device Family ne LH Grade Blank = Commercial Package Device Number G=CPGA M=MQFP Speed 70 = 77 MHz fmax Power 50 = 57 MHz fmax L=Low cotanigtons

Ordering Information

FAMILY |fmax(MHz)| tpd(ns) | ORDERING NUMBER _ PACKAGE 15 ispLSI 3256-70LM 160-Pin MQFP 15 ispLSI 3256-70LG 167-Pin CPGA ispLS! 20 ispLS! 3256-50LM 160-Pin MFP 57 20 ispLSI 3256-50LG 167-Pin CPGA 77 16 | pLSI 3256-70LM 160-Pin MQFP vs 6 | pLS! 3256-70LG 167-Pin CPGA p 20 | pLSI 3256-S0LM 160-Pin MQFP 57 pLSI 3256-50LG 167-Pin CPGA as Table 2- O08TA-Otiapise56 ee 18 1996 ISP Encylopedia mm 5386949 0005791 OOS mm