28C64

28C64 SYC | Alldatasheet

Document overview

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Technical content

Features

• Fast Read Access Time – 150 ns  Automatic Page Write Operation – Internal Address and Data Latches for 64 Bytes  Fast Write Cycle Times – Page Write Cycle Time: 10 ms Maximum – 1 to 64-byte Page Write Operation  Low Power Dissipation – 40 mA Active Current – 100 µA CMOS Standby Current  Hardware and Software Data Protection  DATA Polling and Toggle Bit for End of Write Detection  High Reliability CMOS Technology – Endurance: 100,000 Cycles – Data Retention: 10 Years  Single 5V ± 10% Supply  CMOS and TTL Compatible Inputs and Outputs  JEDEC Approved Byte-wide Pinout  Commercial and Industrial Temperature Ranges

Description

The AT28C64B is a high-performance electrically-erasable and programmable read only memory (EEPROM). Its 64K of memory is organized as 8,192 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 150 ns with power dissipation of just 220 mW. When the device is deselected, the CMOS standby current is less than 100 µA. 64K (8K x 8) Parallel EEPROM with Page Write and Software Data Protection AT28C64B Rev. 0270H–12/99 Pin Configurations Pin Name Function A0 - A12 Addresses CE Chip Enable OE Output Enable WE Write Enable I/O0 - I/O7 Data Inputs/Outputs NC No Connect DC Don ’t Connect PDIP , SOIC T op View NC A12 I/O0 I/O1 I/O2 GND VCC WE NC A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 TSOP Top View OE A11 NC WE VCC NC A12 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 PLCC Top View Note: PLCC package pins 1 and 17 are DON’T CONNECT. NC I/O0 A11 NC OE A10 CE I/O7 I/O6 I/O1 I/O2 GND DC I/O3 I/O4 I/O5 A12 NC DC VCC WE NC (continued)

The AT28C64B is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other operations. Fol- lowing the initiation of a write cycle, the device will automat- ically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA POLL- ING of I/O 7. Once the end of a write cycle has been detected, a new access for a read or write can begin. Atmel’s AT28C64B has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protec- tion mechanism is available to guard against inadvertent writes. The device also includes an extra 64 bytes of EEPROM for device identification or tracking. Block Diagram Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability All Input Voltages (including NC Pins) All Output Voltages CC + 0.6V Voltage on OE and A9

READ: The AT28C64B is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high- impedance state when either CE or OE is high. This dual line control gives designers flexibility in preventing bus con- tention in their systems. BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE , whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started, it will automatically time itself to completion. Once a pro- gramming operation has been initiated and for the duration of t WC , a read operation will effectively be a polling operation. PAGE WRITE: The page write operation of the AT28C64B allows 1 to 64 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; after the first byte is written, it can then be followed by 1 to 63 additional bytes. Each successive byte must be loaded within 150 µs (tBLC) of the previous byte. If the t BLC limit is exceeded, the AT28C64B will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A6 to A12 inputs. For each WE high to low transition during the page write opera- tion, A6 to A12 must be the same. The A0 to A5 inputs specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. DATA POLLING: The AT28C64B features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O 7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at any time during the write cycle. TOGGLE BIT: In addition to DATA Polling, the AT28C64B provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O 6 toggling between one and zero. Once the write has completed, I/O 6 will stop toggling, and valid data will be read. Toggle bit reading may begin at any time during the write cycle. DATA PROTECTION: If precautions are not taken, inad- vertent writes may occur during transitions of the host sys- tem power supply. Atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes. HARDWARE DATA PROTECTION: Hardware features protect against inadvertent writes to the AT28C64B in the following ways: (a) V CC sense – if VCC is below 3.8V (typi- cal), the write function is inhibited; (b) V CC power-on delay – once VCC has reached 3.8V, the device will automatically time out 5 ms (typical) before allowing a write; (c) write inhibit – holding any one of OE low, CE high, or WE high inhibits write cycles; and (d) noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle. SOFTWARE DATA PROTECTION: A software controlled data protection feature has been implemented on the AT28C64B. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28C64B is shipped from Atmel with SDP disabled. SDP is enabled by the user issuing a series of three write commands in which three specific bytes of data are written to three specific addresses (refer to the “Software Data Protection Algorithm” diagram in this datasheet). After writ- ing the 3-byte command sequence and waiting t WC, the entire AT28C64B will be protected against inadvertent writes. It should be noted that even after SDP is enabled, the user may still perform a byte or page write to the AT28C64B by preceding the data to be written by the same 3-byte command sequence used to enable SDP. Once set, SDP remains active unless the disable command sequence is issued. Power transitions do not disable SDP, and SDP protects the AT28C64B during power-up and power-down conditions. All command sequences must conform to the page write timing specifications. The data in the enable and disable command sequences is not actually written into the device; their addresses may still be written with user data in either a byte or page write operation. After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device. However, for the duration of t WC, read operations will effectively be poll- ing operations. DEVICE IDENTIFICATION: An extra 64 bytes of EEPROM memory are available to the user for device identification. By raising A9 to 12V ± 0.5V and using address locations 1FC0H to 1FFFH, the additional bytes may be written to or read from in the same manner as the regular memory array.

Notes: 1. X can be V IL or VIH. 2. Refer to the “AC Write Waveforms” diagrams in this datasheet. DC and AC Operating Range AT28C64B-15 AT28C64B-20 AT28C64B-25 Operating Temperature (Case) VCC Power Supply 5V ± 10% 5V ± 10% 5V ± 10% Operating Modes Mode CE OE WE I/O Read V IL VIL VIH DOUT Write(2) VIL VIH VIL DIN Standby/Write Inhibit V IH X(1) X High Z Write Inhibit X X V IH Write Inhibit X V IL X Output Disable X V IH X High Z Chip Erase V IL VH (3) VIL High Z DC Characteristics Symbol Parameter Condition Min Max Units ILI Input Load Current V IN = 0V to VCC + 1V 10 µA ILO Output Leakage Current V I/O = 0V to VCC 10 µA ISB1 VCC Standby Current CMOS CE = VCC - 0.3V to VCC + 1V Com., Ind. 100 µA ISB2 VCC Standby Current TTL CE = 2.0V to VCC + 1V 2 mA ICC VCC Active Current f = 5 MHz; I OUT = 0 mA 40 mA VIL Input Low Voltage 0.8 V VIH Input High Voltage 2.0 V VOL Output Low Voltage I OL = 2.1 mA 0.40 V VOH Output High Voltage I OH = -400 µA 2.4 V

AC Read Waveforms(1)(2)(3)(4) Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. t DF is specified from OE or CE whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. Input Test Waveforms and Measurement Level Output Test Load Note: 1. This parameter is characterized and is not 100% tested. AC Read Characteristics Symbol Parameter AT28C64B-15 AT28C64B-20 AT28C64B-25 UnitsMin Max Min Max Min Max tACC Address to Output Delay 150 200 250 ns tCE (1) CE to Output Delay 150 200 250 ns tOE (2) OE to Output Delay 0 70 0 80 0 100 ns tDF (3)(4) CE or OE to Output Float 0 50 0 55 0 60 ns tOH Output Hold from OE, CE or Address, whichever occurred first 000 n s tR, tF < 5 ns Pin Capacitance f = 1 MHz, T = 25°C(1) Symbol Typ Max Units Conditions CIN 46 p F V IN = 0V COUT 81 2 p F V OUT = 0V

Symbol Parameter Min Max Units tAS, tOES Address, OE Setup Time 0 ns tAH Address Hold Time 50 ns tCS Chip Select Setup Time 0 ns tCH Chip Select Hold Time 0 ns tWP Write Pulse Width (WE or CE) 100 ns tDS Data Setup Time 50 ns tDH, tOEH Data, OE Hold Time 0 ns

Page Mode Write Waveforms(1)(2) Notes: 1. A6 through A12 must specify the same page address during each high to low transition of WE (or CE). 2. OE must be high only when WE and CE are both low. Chip Erase Waveforms tS = tH = 1 µsec (min.) tW = 10 msec (min.) VH = 12.0 ± 0.5V Page Mode Characteristics Symbol Parameter Min Max Units tWC Write Cycle Time 10 ms tWC Write Cycle Time (option available; contact Atmel sales office for ordering part number) 02 m s tAS Address Setup Time 0 ns tAH Address Hold Time 50 ns tDS Data Setup Time 50 ns tDH Data Hold Time 0 ns tWP Write Pulse Width 100 ns tBLC Byte Load Cycle Time 150 µs tWPH Write Pulse Width High 50 ns

Enable Algorithm(1) Notes for software program code: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A12 - A0 (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 64 bytes of data are loaded. Software Data Protection Disable Algorithm(1) Software Protected Write Cycle Waveforms(1)(2) Notes: 1. A6 through A12 must specify the same page address during each high to low transition of WE (or CE) after the software code has been entered. 2. OE must be high only when WE and CE are both low. LOAD DATA AA TO ADDRESS 1555 LOAD DATA 55 TO ADDRESS 0AAA LOAD DATA A0 TO ADDRESS 1555 LOAD DATA XX TO ANY ADDRESS(4) LOAD LAST BYTE TO LAST ADDRESS ENTER DATA PROTECT STATE WRITES ENABLED(2) LOAD DATA AA TO ADDRESS 1555 LOAD DATA 55 TO ADDRESS 0AAA LOAD DATA 80 TO ADDRESS 1555 LOAD DATA AA TO ADDRESS 1555 LOAD DATA 20 TO ADDRESS 1555 LOAD DATA XX TO ANY ADDRESS(4) LOAD LAST BYTE TO LAST ADDRESS LOAD DATA 55 TO ADDRESS 0AAA EXIT DATA PROTECT STATE(3)

Notes: 1. These parameters are characterized and not 100% tested. 2. See “AC Read Characteristics”. Data Polling Waveforms Notes: 1. These parameters are characterized and not 100% tested. 2. See “AC Read Characteristics”. Toggle Bit Waveforms(1)(2)(3) Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. Data Polling Characteristics(1) Symbol Parameter Min Typ Max Units tDH Data Hold Time 0 ns tOEH OE Hold Time 0 ns tOE OE to Output Delay(2) ns tWR Write Recovery Time 0 ns Toggle Bit Characteristics(1) Symbol Parameter Min Typ Max Units tDH Data Hold Time 10 ns tOEH OE Hold Time 10 ns tOE OE to Output Delay(2) ns tOEHP OE High Pulse 150 ns tWR Write Recovery Time 0 ns

Note: 1. See “Valid Part Numbers” table below. Ordering Information(1) tACC (ns) ICC (mA) Ordering Code Package Operation RangeActive Standby 150 40 0.1 AT28C64B-15JC AT28C64B-15PC AT28C64B-15SC AT28C64B-15TC 32J 28P6 28S 28T Commercial (0°C to 70°C) AT28C64B-15JI AT28C64B-15PI AT28C64B-15SI AT28C64B-15TI 32J 28P6 28S 28T Industrial (-40°C to 85°C) 200 40 0.1 AT28C64B-20JC AT28C64B-20PC AT28C64B-20SC AT28C64B-20TC 32J 28P6 28S 28T Commercial (0°C to 70°C) AT28C64B-20JI AT28C64B-20PI AT28C64B-20SI AT28C64B-20TI 32J 28P6 28S 28T Industrial (-40°C to 85°C) 250 40 0.1 AT28C64B-25JC AT28C64B-25PC AT28C64B-25SC AT28C64B-25TC 32J 28P6 28S 28T Commercial (0°C to 70°C) AT28C64B-25JI AT28C64B-25PI AT28C64B-25SI AT28C64B-25TI 32J 28P6 28S 28T Industrial (-40°C to 85°C) Valid Part Numbers The following table lists standard Atmel products that can be ordered. Device Numbers Speed Package and Temperature Combinations AT28C64B 15 JC, JI, PC, PI, SC, SI, TC, TI AT28C64B 20 JC, JI, PC, PI, SC, SI, TC, TI AT28C64B 25 JC, JI, PC, PI, SC, SI, TC, TI AT28C64B – W Die Products Reference Section: Parallel EEPROM Die Products Package Type 32J 32-lead, Plastic J-leaded Chip Carrier (PLCC) 28P6 28-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 28S 28-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 28T 28-lead, Plastic Thin Small Outline Package (TSOP) W Die

.045(1.14) X 45˚ PIN NO. 1 IDENTIFY .012(.305) .008(.203) .021(.533) .013(.330) .530(13.5) .490(12.4) .030(.762) .015(.381) .095(2.41) .060(1.52) .140(3.56) .120(3.05) .032(.813) .026(.660) .050(1.27) TYP .553(14.0) .547(13.9) .595(15.1) .585(14.9) .300(7.62) REF .430(10.9) .390(9.90) AT CONTACT POINTS .453(11.5) .447(11.4) .495(12.6) .485(12.3) 1.47(37.3) 1.44(36.6) PIN .566(14.4) .530(13.5) .090(2.29) MAX .005(.127) MIN .065(1.65) .015(.381) .022(.559) .041(1.04)

15 REF

.630(16.0) .590(15.0) .690(17.5) .610(15.5) .012(.305) .008(.203) .110(2.79) .090(2.29) .161(4.09) .125(3.18) SEATING PLANE .220(5.59) MAX 1.300(33.02) REF INDEX MARK AREA 0.55 (0.022) BSC 0.20 (0.008) 0.10 (0.004) 7.15 (0.281) REF 8.10 (0.319) 7.90 (0.311) 1.25 (0.049) 1.05 (0.041) 0.27 (0.011) 0.18 (0.007) 11.9 (0.469) 11.7 (0.461) 13.7 (0.539) 13.1 (0.516) 5 0.20 (0.008) 0.15 (0.006) REF 0.70 (0.028) 0.30 (0.012) 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-016 AE 28P6, 28-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-011 AB 28S, 28-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) Dimensions in Inches and (Millimeters) 28T, 28-lead, Plastic Thin Small Outline Package (TSOP) Dimensions in Millimeters and (Inches)*