27C8001 SYC | Alldatasheet

Document overview

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Technical content

Features

  • Read Access Time - 100 ns
  • Word-wide or Byte-wide Configurable
  • 8-Megabit Flash and Mask ROM Compatable
  • Low Power CMOS Operation -1 0 0 µA Maximum Standby - 50 mA Maximum Active at 5 MHz
  • Wide Selection of JEDEC Standard Packages - 42-Lead 600 mil Cerdip and PDIP - 44-Lead SOIC (SOP) - 48-Lead TSOP (12 mm x 20 mm)
  • 5V ± 10% Power Supply
  • High Reliability CMOS Technology - 2,000 ESD Protection - 200 mA Latchup Immunity
  • RapidTM Programming Algorithm - 50 µs/word (typical)
  • CMOS and TTL Compatible Inputs and Outputs
  • Integrated Product Identification Code
  • Commercial and Industrial Temperature Ranges

Description

The AT27C800 is a low-power, high performance 8,388,608-bit UV erasable program- mable read only memory (EPROM) organized as either 512K by 16 or 1024K by 8 bits. It requires a single 5V power supply in normal read mode operation. Any word can be accessed in less than 100 ns, eliminating the need for speed-reducing WAIT states. The x16 organization makes this part ideal for high-performance 16- and 32-bit microprocessor systems. 0801A-A 8-Megabit (512K x 16 or 1024K x 8) UV Erasable EPROM Pin Configurations Pin Name Function A0 - A18 Addresses O0 - O15 Outputs O15/A-1 Output/Address BYTE /VPP Byte Mode/ Program Supply CE Chip Enable OE Output Enable NC No Connect TSOP Type 1 A15 A14 A13 A12 A11 A10 NC NC NC NC NC NC NC A18 A17 A16 BYTE/VPP GND O15/A-1 O14 O13 O12 VCC O11 O10 OE GND CE CDIP , PDIP Top View A18 A17 CE GND OE O10 O11 NC A10 A11 A12 A13 A14 A15 A16 BYTE/VPP GND O15/A-1 O14 O13 O12 VCC SOIC (SOP) NC A18 A17 CE GND OE O10 O11 NC NC A10 A11 A12 A13 A14 A15 A16 BYTE/VPP GND O15/A-1 O14 O13 O12 VCC (continued) 27C8001

The AT27C800 can be organized as either word-wide or byte-wide. The organization is selected via the BYTE/VPP pin. When BYTE/VPP is asserted high (VIH), the word-wide organization is selected and the O15/A-1 pin is used for O15 data output. When BYTE /VPP is asserted low (VIL),the byte wide organization is selected and the O15/A-1 pin is used for the address pin A-1. When the AT27C800 is logi- cally regarded as x16 (word-wide), but read in the byte- wide mode, then with A-1=V IL the lower eight bits of the 16 bit word are selected with A-1 =VIH the upper 8 bits of the 16-bit word are selected. In read mode, the AT27C800 typically consumes 15 mA. Standby mode supply current is typically less than 10 µA. The AT27C800 is available in industry standard JEDEC- approved one-time programmable (OTP)PDIP, SOIC (SOP), and TSOP as well as UV erasable windowed Cer- dip packages. The device features two-line control(CE ,OE) to eliminate bus contention in high-speed systems. With high density 512K word or 1024K-bit storage capabil- ity, the AT27C800 allows firmware to be to be stored reli- ably and to be accessed by the system without the delays of mass storage media. Atmel’s AT27C800 has additional features that ensure high quality and efficient production use. The Rapid TM Program- ming Algorithm reduces the time required to program the part and guarantees reliable programming. Programming time is typically only 50 µs/word. The Integrated Product Identification Code electronically identifies the device and manufacturer. This feature is used by industry standard programming equipment to select the proper programming equipment and voltages. Erasure Characteristics The entire memory array of the AT27C800 is erased (all outputs read as V OH ) after exposure to ultraviolet light at a wavelength of 2,537Å. Complete erasure is assured after a minimum of 20 minutes of exposure using 12,000 µW/cm 2 intensity lamps spaced one inch away from the chip. Mini- mum erase time for lamps at other intensity ratings can be calculated from the minimum integrated erasure dose of 15 W .sec/cm 2. To prevent unintentional erasure, an opaque label is recommended to cover the clear window on any UV erasable EPROM that will be subjected to continuous flourescent indoor lighting or sunlight. System Considerations Switching between active and standby conditions via the Chip Enable pin may produce transient voltage excursions. Unless accommodated by the system design, these tran- sients may exceed data sheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high frequency, low inherent inductance, ceramic capacitor should be uti- lized for each device. This capacitor should be connected between the V CC and Ground terminals of the device, as close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again connected between the VCC and Ground terminals. This capacitor should be positioned as close as possible to the point where the power supply is connected to the array. Block Diagram

Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: 1. Minimum voltage is -0.6V DC which may under- shoot to -2.0V for pulses of less than 20 ns. Max- imum output pin voltage is Vcc + 0.75V DC which may overshoot to + 7.0V for pulses of less than 20 ns. Voltage on Any Pin with Voltage on A9 with (1) VPP Supply Voltage with Operating Modes Notes: 1. X can be VIL or VIH. 2. Refer to the programming characteristics tables in this data sheet. 4. Two identifier words may be selected. All Ai inputs are held low (VIL) except A9,which is set to VH , and A0, which is toggled low (VIL) to select the Manufacturer’s Identification word and high (VIH) to select the Device Code word. 5. Standby VCC current (ISB ) is specified with VPP = VCC . VCC > VPP will cause a slight increase in ISB . Mode\\Pin CE OE Ai BYTE /VPP Outputs O 0-O7 O 8-O14 O 15/A-1 Read Word-wide V IL VIL X(1) VIH D OUT D OUT D OUT Read Byte-wide Upper V IL VIL X(1) VIL D OUT High Z V IH Read Byte-wide Lower V IL VIL X(1) VIL D OUT High Z V IL Output Disable X (1) VIH X(1) XH i g h Z Standby V IH X(1) X(1) X(5) High Z Rapid Program(2) VIL VIH Ai V PP D IN PGM Verify X V IL Ai V PP D OUT PGM Inhibit V IH VIH X(1) VPP High Z Product Identification(4) VIL VIL A9 = VH (3) A0 = VIH or VIL A1 - A18 = VIL VIH Identification Code

Byte-Wide Read Mode AC Waveforms(1) Note: 1. BYTE /VPP = VIL BYTE Transition AC Waveforms 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE. 3. OE may be delayed up to tACC - tOE after the address is valid without impact on tACC . 4. This parameter is only sampled and is not 100% tested. 5. Output float is defined as the point when data is no longer driven. A0 - A18 A-1 O- O07 BYTE/V PP tACC tST tSTD tOH tOH O- O81 5 HI-Z VALID VALID DATA OUT DATA OUT DATA OUT Byte-Wide Read Mode AC Waveforms(1) Note: 1. BYTE /VPP = VIH

Note: 1. CL = 100 pF including jig capacitance. Pin Capaticance (f = 1 MHz, T = 25°V)(1) Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. Typ Max Units Conditions C IN 41 0 p F V IN = 0V C OUT 81 2 p F V OUT = 0V Input Test Waveforms and Measurement Levels tR , tF < 20 ns (10% to 90%)

Programming Waveforms (1) Notes: 1. The Input Timing reference is 0.8V for VIL and 2.0V for VIH. 2. tOE and tDFP are characteristics of the device but must be accommodated by the programmer. 3. When programming the AT27C800, a 0.1 µF capacitor is required across VPP and ground to suppress voltage transients. DC Programming Characteristics TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V Symbol Parameter Test Conditions Limits UnitsMin Max ILI Input Load Current V IN = VIL, VIH ±10 µA VIL Input Low Level -0.6 0.8 V VIH Input High Level 2.0 V CC + 0.5 V VOL Output Low Voltage I OL = 2.1 mA 0.4 V VOH Output High Voltage I OH = -400 µA2 . 4 V ICC2 VCC Supply Current (Program and Verify) 50 mA IPP2 VPP Supply Current CE = VIL 30 mA VID A9 Product Identification Voltage 11.5 12.5 V

AC Programming Characteristics TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V Notes: 1. V cc must be applied simultaneously or before VPP and removed simultaneously or after VPP. 2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven— see timing diagram. 3. Program Pulse width tolerance is 50 µs ± 5%. Symbol Parameter Test Conditions (1) Limits UnitsMin Max tAS Address Setup Time Input Rise and Fall Times: Input Pulse Levels: 45V to 2.4V Input Pulse Levels: 0.8V to 2.0V Input Timing Reference Level: 0.8V to 2.0V Output Timing Reference Level: 0.8V to 2.0V 2 µs tOES OE Setup Time 2 µs tDS Data Setup Time 2 µs tAH Address Hold Time 0 µs tDH Data Hold Time 2 µs tDFP OE High to Output Float Delay(2) 0 130 ns tVPS VPP Setup Time 2 µs tVCS VCC Setup Time 2 µs tPW CE Program Pulse Width(3) 47.5 52.5 µs tOE Data Valid from OE 150 ns tPRT BYTE /VPP Pulse Rise Time During Programming 50 ns Atmel’s 27C800 Integrated Product Identification Code Codes Pins Hex Data A0 015 014 013 012 011 010 09 08 07 06 05 04 03 02 01 00 Manufacturer 000011110 1 E 1 E D e v i c e T y p e 111111000 F 8 F 8

Rapid Programming Algorithm A 50 µs CE pulse width is used to program. The address is set to the first location. VCC is raised to 6.5V and BYTE/VPP is raised to 13.0V. Each address is first programmed with one 50 µs CE pulse without verification. Then a verification/ reprogramming loop is executed for each address. In the event a word fails to pass verification, up to 10 successive µs pulses are applied with a verification after each pulse. If the word fails to verify after 10 pulses have been applied, the part is considered failed. After the word verifies properly, the next address is selected until all have been checked. V PP is then lowered to 5.0V and VCC to 5.0V. All words are read again and compared with the original data to determine if the device passes or fails.

Ordering Information

(ns) ICC (mA) Ordering Code Package Operation RangeActive Standby 100 50 0.1 AT27C800-10DC AT27C800-10PC AT27C800-10RC AT27C800-10TC 42DW6 42P6 44R 48T Commercial (0°C to 70°C) 50 0.1 AT27C800-10DI AT27C800-10PI AT27C800-10RI AT27C800-10TI 42DW6 42P6 44R 48T Industrial (-40°C to 85°C) 120 50 0.1 AT27C800-12DC AT27C800-12PC AT27C800-12RC AT27C800-12TC 42DW6 42P6 44R 48T Commercial (0°C to 70°C) 50 0.1 AT27C800-12DI AT27C800-12PI AT27C800-12RI AT27C800-12TI 42DW6 42P6 44R 48T Industrial (-40°C to 85°C) 150 50 0.1 AT27C800-15DC AT27C800-15PC AT27C800-15RC AT27C800-15TC 42DW6 42P6 44R 48T Commercial (0°C to 70°C) 50 0.1 AT27C800-15DI AT27C800-15PI AT27C800-15RI AT27C800-15TI 42DW6 42P6 44R 48T Industrial (-40°C to 85°C) Package Type 42DW6 42 Lead, 0.600" Wide, Ceramic Dual Inline Package (CDIP) 42P6 42 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 44R 44 Lead, 0.525" Wide, Plastic Gull Wing Small Outline Package (SOIC/SOP) 48T 48 Lead, Plastic Thin Small Outline Package (TSOP) 12 x 20 mm