26LS31

26LS31 SYC | Alldatasheet

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Technical content

QUADRUPLE DIFFERENTIAL LINE DRIVER SLLS114D – JANUARY 1979 – REVISED OCTOBER 1998 /C0068Meets or Exceeds the Requirements of ANSI TIA/EIA-422-B and ITU Recommendation V.11 /C0068Operates From a Single 5-V Supply /C0068TTL Compatible /C0068Complementary Outputs /C0068High Output Impedance in Power-Off Conditions /C0068Complementary Output-Enable Inputs

description

The AM26LS31C is a quadruple complementary-output line driver designed to meet the requirements of ANSI TIA/EIA-422-B and ITU (formerly CCITT) Recommendation V.11. The 3-state outputs have high-current capability for driving balanced lines such as twisted-pair or parallel-wire transmission lines, and they provide a high-impedance state in the power-off condition. The enable function is common to all four drivers and offers the choice of an active-high or active-low enable (G, G ) input. Low-power Schottky circuitry reduces power consumption without sacrificing speed. The AM26LS31C is characterized for operation from 0°°C. FUNCTION TABLE (each driver) INPUT ENABLES OUTPUTS A G G Y Z H H X H L L H XL H H X LH L L X LL H X L H Z Z H = high level, L = low level, X = irrelevant, Z = high impedance (off) G GND VCC G D OR N PACKAGE (TOP VIEW)

QUADRUPLE DIFFERENTIAL LINE DRIVER SLLS114D – JANUARY 1979 – REVISED OCTOBER 1998 logic symbol† G EN G logic diagram (positive logic) G G

QUADRUPLE DIFFERENTIAL LINE DRIVER SLLS114D – JANUARY 1979 – REVISED OCTOBER 1998 schematic (each driver) 22 kΩ To Three Other Drivers Common to All Four Drivers GND Enable G Enable G VCC V V Output Y 9 Ω Input A 22 kΩ 22 kΩ All resistor values are nominal. Output Z 9 Ω absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential output voltage VOD , are with respect to network GND. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero.

QUADRUPLE DIFFERENTIAL LINE DRIVER SLLS114D – JANUARY 1979 – REVISED OCTOBER 1998 recommended operating conditions (unless otherwise noted) MIN NOM MAX UNIT Supply voltage, VCC 4.75 5 5.25 V High-level input voltage, VIH 2 V Low-level input voltage, VIL 0.8 V High-level output current, IOH –20 mA Low-level output current, IOL 20 mA Operating free-air temperature, TA 0 70 °C electrical characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VIK Input clamp voltage VCC = 4.75 V, II = –18 mA –1.5 V VOH High-level output voltage VCC = 4.75 V, IOH = –20 mA 2.5 V VOL Low-level output voltage VCC = 4.75 V, IOL = 20 mA 0.5 V IOZ Off state (high impedance state) output current VCC = 4 75 V VO = 0.5 V –20 µAIOZ Off-state (high-impedance-state) output current VCC = 4.75 V VO = 2.5 V 20 µA II Input current at maximum input voltage VCC = 5.25 V, VI = 7 V 0.1 mA IIH High-level input current VCC = 5.25 V, VI = 2.7 V 20 µA IIL Low-level input current VCC = 5.25 V, VI = 0.4 V –0.36 mA IOS Short-circuit output current‡ VCC = 5.25 V –30 –150 mA ICC Supply current VCC = 5.25 V, All outputs disabled 32 80 mA † All typical values are at VCC = 5 V and TA = 25°C. ‡ Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second. switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low-to-high-level output C L =3 0pF S1 and S2 open 14 20 nstPHL Propagation delay time, high-to-low-level outputC L = 30 pF, S1 and S2 open 14 20 ns tPZH Output enable time to high level C L =3 0pF R L = 75 Ω 25 40 ns tPZL Output enable time to low level C L = 30 pF R L = 180 Ω 37 45 ns tPHZ Output disable time from high level C L =1 0pF S1 and S2 closed 21 30 ns tPLZ Output disable time from low level C L = 10 pF, S1 and S2 closed 23 35 ns Output-to-output skew C L = 30 pF, S1 and S2 open 1 6 ns

NOTES: A. C L includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω , tr ≤ 15 ns, tf ≤ 6 ns. C. When measuring propagation delay times and skew, switches S1 and S2 are open. D. Each enable is tested separately. E. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. Figure 1. Test Circuit and Voltage Waveforms