25Q16BVSIG

HM25Q128A HMSEMI | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 5.2.1 Security Register
• 5.2.2 Serial Flash Discoverable Parameters (SFDP)Address Map
• 5.2.3 SFDPHeader Field Definitions
• 5.2.4 JEDEC SFDPBasic SPI Flash Parameter
• 6.1 SPI Operations
• 6.1.1 SPI Modes
• 6.1.2 Dual SPI Modes
• 6.1.3 Quad SPI Modes
• 6.1.4 QPI Function
• 6.1.5 Hold Function
• 6.1.6 Software Reset &Hardware RESET# pin
• 6.2.1 BUSY
• 6.2.2 Write Enable Latch (WEL)
• 6.2.3 Block Protect Bits (BP2, BP1, BP0)
• 6.2.4 Top / Bottom Block Protect (TB)
• 6.2.5 Sector / Block Protect (SEC)
• 6.2.6 Complement Protect (CMP)
• 6.2.7 The Status Register Protect (SRP1, SRP0)
• 6.2.8 Erase / Program Suspend Status (SUS)
• 6.2.9 Security Register Lock Bits (LB3, LB2, LB1)
• 6.2.10 Quad Enable (QE)
• 6.2.12 Output Driver Strength (DRV1, DRV0)
• 6.2.13 High Frequency Enable Bit (HFQ)
• 6.2.14 Write Protect Selection (WPS)
• 6.2.15 Latency Control (LC)
• 6.3.1 Write Protect Features
• 6.3.2 Block Protection Maps
• 7.1 Configuration and Status Commands
• 7.1.1 Read Status Register (05h/35h/15h)

DUALAND QUAD SPI&QPI V1.1 HM25Q128A

FEATURES

 Lowpower supplyoperation - Single 2.3V-3.6Vsupply  128 MbitSerial Flash - 128 M-bit/16M-byte/65,536 pages - 256 bytes per programmable page - Uniform 4K-byte Sectors, 32K/64K-byte Blocks  New Family of SpiFlash Memories - Standard SPI: CLK, CS#, DI, DO, WP#, HOLD# / RESET# - Dual SPI: CLK, CS#, DI, DO, WP#, HOLD# / RESET# - Quad SPI: CLK, CS#, IO0, IO1, IO2, IO3 - QPI: CLK, CS#, IO0, IO1, IO2, IO3 - Software & HardwareReset - Auto-increment Read capability  Temperature Ranges - Industrial (-40°C to +85°C) - Extended (-20°C to +85°C)  Lowpower consumption - 9 mAtypical active current - 2 uAtypical power down current  Efficient “ContinuousRead” and QPI Mode - Continuous Read with 8/16/32/64-Byte Wrap - As few as 8clocks toaddress memory - Quad Peripheral Interface(QPI) reduces instruction overhead  FlexibleArchitecture with 4KB sectors - Sector Erase (4K-bytes) - BlockErase (32K/64K-bytes) - PageProgram up to256 bytes - More than 100K erase/program cycles - More than 20-year data retention  Advanced Security Feature - Softwareand HardwareWrite-Protect - Power Supply Lock-Down and OTP protection - Top/Bottom,Complement array protection - Individual Block/Sector array protection - 64-Bit Unique ID foreach device - Discoverableparameters(SFDP) register - 3X256-Bytes Security Registers with OTP locks - Volatile& Non-volatile Status Register Bits  High performance program/erase speed - Pageprogram time: 500us typical - Sector erase time: 35mstypical - Blockerase time: 250mstypical - Chip erase time: 50 Seconds typical  Package Options - 8-pin SOIC 150/208-mil - 8-pad WSON6x5-mm - 8-pin PDIP300-mil - All Pb-free packages are RoHS compliant GENERALDESCRIPTION The HM25Q128A-PWof non-volatile flash memorydevice supports the standard Serial Peripheral Interface (SPI).Traditional SPI single bit serial input and output (Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit (quad I/O or QIO) serial protocols.This multiple width interface is called SPI Multi-I/O or MIO. The SPI protocols useonly 4to 6 signals:  ChipSelect (CS#)  Serial Clock (CLK)  Serial Data - IO0(DI) - IO1(DO) - IO2(WP#) - IO3(HOLD# / RESET#) HM25Q128A

The HM25Q128A support thestandard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI as well as 2-clocks instruction cycle Quad Peripheral Interface (QPI): Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2(WP#), and I/O3(HOLD#/ RESET#). SPI clock frequencies of up to 104MHz are supported allowing equivalent clockrates of 208MHz (104MHz x 2)forDual I/O and 416MHz (104MHz x4)forQuad I/O when using theFast Read Dual/Quad I/O and QPI instructions.These transferrates canoutperform standard Asynchronous 8 and 16-bit Parallel Flash memories.The Continuous Read Mode allows for efficient memory access with as few as 8-clocks of instruction-overhead to reada 24-bit address, allowing trueXIP(executein place) operation. AHoldpin, WriteProtectpinandprogrammable writeprotection, with toporbottom array control, provide further control flexibility.Additionally,the device supports JEDEC standard manufacturer and device ID and SFDPRegister,a64-bit Unique Serial Number and three256-bytes Security Registers. The HM25Q128A provi des an ideal storage solution for systems with limited space, signal connections, and powe r. These memories' flexibility and performance is better than ordinary serial flash devices. They are ideal for code shadowing to RAM, executingcode directly (XIP), and storing reprogrammable data. HM25Q128A

1. ORDERINGINFORMATION The ordering part number is formedby a validcombination of thefollowing: Figure 1.1 Ordering Information HM25Q128A

1. BLOCK DIAGRAM Figure21 Block Diagram HM25Q128A

1. CONNECTION DIAGRAMS Figure3.1 8-pin SOP(150/208mil)/ PDIP(300mil) Figure3.2 8-Contact 6x 5mm WSON HM25Q128A

1. SIGNAL DESCRIPTIONS Table4.1 Pin Descriptions Symbol PinName CLK SerialClockInput DI(IO0) SerialDataInput(Data inputoutput0) (1) DO(IO1) SerialDataOutput(Datainput output1) (1) CS# ChipEnable WP#(IO2)(3) WriteProtect(Datainputoutput2) (2) HOLD#/RESET# (3)(IO3) Hold or Resetinput(Data inputoutput 3)(2) VCC Power Supply(2.3-3.6V) GND Ground Notes: (1)IO0andIO1 areused forStandard and DualSPIinstructions. (2)IO0—IO3are used forQUADSPI/QPIinstructions. (3)WP#andHOLD# /RESET#functionsareonlyavailable forStandard and Dual SPI. 4.1. SerialDataInput(DI)/ IO0 The SPI Serial Data Input (DI) pin is usedto transfer data serially into the device. It receives instructions, address and data tobe programmed. Data is latched on the rising edge of the Serial Clock (CLK) input pin. The DI pin becomesIO0 - aninput and output during Dual and Quad commandsfor receiving instructions, address, and data to be programmed (values latched on rising edge of serial CLK clock signal) as well as shifting out data (onthe falling edge of CLK). 4.2. SerialDataOutput(DO)/ IO1 The SPI Serial Data Output (DO)pin is used to transfer data serially out of the device. Data is shiftedout onthefallingedgeoftheSerialClock(CLK)input pin.DObecomesIO1-aninputandoutputduringDualand Quad commands forreceiving instructions, addresses,and data to be programmed (values latched on rising edge of serial CLK clock signal) as well as shifting out data (on the falling edge of CLK). 4.3. SerialClock(CLK) TheSPI SerialClockInput (CLK) pin providesthe timingforserial input and output operations. ("SeeSPI Mode") 4.4. ChipSelect(CS#) The SPI Chip Select (CS#) pin enables and disables device operation. WhenCS# is high the device is deselected and the Serial Data Output pins areat highimpedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or status register cycleis in progress. WhenCS# is brought low the device will beselected, power consumption will increase toactive levels and instructions canbe writtento and data readfrom the device. After power-up, CS# must transition from high to low beforea new instruction will be accepted. HM25Q128A

4.5. WriteProtect(WP#)/ IO2 The Write Protect (WP#) pin can be used toprevent the Status Register from being written. Used in conjunction with the Status Register’s Block Protect (BP0, BP1 and BP2, TB, SEC, CMP) bits and Status Register Protect (SRP0) bits, a portionor the entirememory arraycan be hardware protected. TheWP#function is not available whenthe Quadmodeis enabled.TheWP#function isreplacedbyIO2 forinput and output duringQuad mode forreceiving addresses and data to be programmed (values are latched on rising edge of the CLK signal) as well as shifting out data (onthe falling edge of CLK). 4.6. HOLD(HOLD#)/ IO3 TheHOLD#pinallowsthedevicetobepausedwhileitisactivelyselected.WhenHRSWbit is‘0’(factory default is ‘0’), the HOLD# pin is enabled. When HOLD# is brought low,while CS#is low,the DO pin will be at highimpedanceandsignalsontheDIandCLKpinswillbeignored(don’tcare). WhenHOLD#isbrought high, deviceoperationcanresume.TheHOLD#functioncanbeusefulwhenmultipledevices aresharingthesame SPI signals.The HOLD# pin is active low.When the QEbit of Status Register-2 is set for Quad I/O, the HOLD# pin function is not available since thispin is used for IO3. 4.7. RESET (RESET#)/ IO3 The RESET# pin allows the device to be reset by the controller.WhenHRSW bit is ‘1’(factory default is ‘0’),theRESET#pin isenabled. DriveRESET#low foraminimumperiodof~1us(tRESET*)willinterrupt any on-going external/internal operations, regardless thestatus of other SPI signals (CS#, CLK, DI, DO, WP# and/or HOLD#).The Hardware Reset function is only available for standardSPI and Dual SPI operation, when QE=0, the IO3 pin can beconfigured either as aHOLD# pin or as aRESET# pin depending on Status Register setting, when QE=1, this pin is the Serial Data IO(IO3) for Quad I/O operation. HM25Q128A

1. MEMORYORGANIZATION 5.1. FlashMemoryArray The memoryis organized as: - 16,777,216bytes - Uniform SectorArchitecture 256 blocks of 64-Kbyte - 4096 sectorsof 4-Kbyte - 65, 536 pages (256 bytes each) Each pagecan be individually programmed (bits are programmed from 1to 0).Thedevice is Sector, Block or Chip Erasable but not Page Erasable. Table5.1(1) MemoryOrganization Block/Security Register/SFDP Sector Address range SecurityRegister3 - 003000H 0030FFH SecurityRegister2 - 002000H 0020FFH SecurityRegister1 - 001000H 0010FFH SecurityRegister0 (SFDP) - 000000H 0000FFH Block255

4095 FFF000H FFFFFFH

4080 FF0000H FF0FFFH

4079 FEF000H FEFFFFH

4064 FE0000H FE0FFFH

Notes: (1)Thesearecondensedtablesthatusea coupleofsectorsasreferences.There are addressranges thatare not explicitly listed.All4-kBsectorshave thepatternXXX000h-XXXFFFh. 5.2. Se curityRegisters The HM25Q128A provi des four 256-byte Security Registers. Each register can be used tostore inform ation that canbe permanently protected by programming OneTimeProgrammable (OTP) lock bits in Status Register-2. Register 0 is used byFSRKto storeand protect theSerial Flash Discoverable Parameters (SFDP) information that is also accessed bythe Read SFDPcommand. SeeTable 5.1. The three additional Security Registers canbe erased, programmed, and protected individually.These HM25Q128A

registers maybe used by system manufacturers to storeand permanently protect security or other important information separate from the main memoryarray.

5.2.1 Security Register 0

Serial Flash Discoverable Parameters (SFDP— JEDEC JESD216B): This document defines the Serial FlashDiscoverable Parameters (SFDP) revision B data structure for HM25Q128A famil y. The Rea d SFDP(RSFDP) command(5Ah) reads information from aseparate flashmemoryaddress space fordevice identification, feature, and configuration information, in accordwith the JEDEC JESD216B standard for Serial Flash Discoverable Parameters. The SFDPdata structure consists of a header table that identifies the revision of the JESD216 header format that is supported and provides a revision number and pointer for each of the SFDPparameter tables that areprovided.The parameter tables follow the SFDPheader.However,the parameter tables may be placed in any physical location and order within the SFDPaddress space.The tables are not necessarily adjacent nor in the sameorder as their header table entries. The SFDPheader points to the following parameter tables:  Basic Flash –This is the original SFDPtable. The physical order of the tables in the SFDPaddress space is: SFDPHeader,and Basic Flash. The SFDPaddress spaceis programmed byFSRKand read-only for the host system.

5.2.2 Serial Flash Discoverable Parameters (SFDP)Address Map

The SFDPaddress space has a header starting at address zero that identifies the SFDPdata structure andprovidesapointertoeachparameter.OneBasicFlashparameteris mandatedbytheJEDECJESD216B standard. Table5.2 SFDPOverview Map — Security Register 0 ByteAddress Description 0000h Locationzero withinJEDECJESD216BSFDPspace –startof SFDPheader 0010h Undefinedspacereserved for future SFDPheader 0030h Startof SFDPparameter ... RemainderofSFDPJEDEC parameterfollowed b yundefinedspace 006Fh EndofSFDPspace 0070h to00FFh Reserved space HM25Q128A

5.2.3 SFDPHeader Field Definitions

Table 5.3 SFDPHeader SFDP Byte Address SFDPDword Name Data Description 00h SFDPHeader 1stDWORD 53h This is the entry point for Read SFDP (5Ah) command i.e. location zero within SFDPspace ASCII“S” 01h 46h ASCII“F” 02h 44h ASCII“D” 03h 50h ASCII“P” 04h SFDPHeader 2ndDWORD 06h SFDPMinor Revision(06h = JEDECJESD216RevisionB) – This revision is backward compatible with all prior minor revisions. Minor revisions are changes that define previously reserved fields, add fields to the end, or that clarify definitions of existing fields. Increments of the minor revision value indicate that previously reserved parameter fields may have been assigned a new definition or entire Dwords may have been added to the parameter table. However, the definition of previously existing fields is unchanged and therefore remains backward compatible with earlier SFDP parameter table revisions. Software can safely ignore increments of the minor revision number, as long as only those parameters the software was designed to support are used i.e. Previously reserved fields and additional Dwords must be masked or ignored. Do not do a simple compare on the minor revision number, looking only for a match with the revision number that the software is designed to handle. There is no problem with using a higher number minor revision. 05h 01h SFDPMajor Revision – This is the original major revision. This major revision is compatible with all SFDPreading andparsing software. 06h 00h Numberof ParameterHeaders (zero based,00h =1 parameters 07h FFh Un used 08h Parameter Header 01stDWORD 00h Parameter IDLSB(00h = JEDECSFDPBasicSPIFlash Parameter) 09h 06h Parameter Minor Revision(00h =JESD216) –Thisolder revision parameter header is provided for any legacy SFDPreading and parsing software that requires seeing a minor revision 6 parameter header. SFDP software designed to handle later minor revisions should continue reading parameter headers looking for a higher numbered minor revision that containsadditionalparametersforthatsoftware revision. 0Ah 01h Parameter Major Revision (01h = The original major revision - all SFDP software iscompatiblewiththisma jorrevision. 0Bh 10h Par ameter Table Length (in double words = Dwords = 4-byte units) 10h = 16 Dwords 0Ch Parameter Header 02nd DWORD 30h Parameter Table Pointer Byte 0 (Dword = 4-byte aligned) JEDEC Basic SPI Flashparameter byteoffset=30h 0Dh 00h ParameterTablePointer Byte1 0Eh 00h Pa rameterTablePointer Byte2 0Fh FFh Pa rameter IDMSB(FFh= JEDEC definedlegacyParameter ID) HM25Q128A

5.2.4 JEDEC SFDPBasic SPI Flash Parameter

Table5.4 Basic SPI Flash Parameter,JEDEC SFDPRev B (Sheet 1 of 5) SFDP Parameter Relative Byte Address SFDPDword Name Data Description 30h JEDEC BasicFlash Parameter Dword-1 E5h StartofSFDPJEDECparameter Bits7:5=unused= 111b Bit 4:3 = 05h is volatile status register write instruction and status register is defaultnon-volatile= 00b Bit2 =ProgramBuffer> 64 bytes=1 Bits1:0=Uniform4-kBerase issupportedthrou ghout thedevice= 01b 31h 20h Bit s15:8=Uniform4-kBerase instruction= 20h 32h F1h Bit23 =Unused =1b Bit22 =SupportsQORRead (1-1-4),Yes=1b Bit21 =SupportsQIORead (1-4-4),Yes=1b Bit20 =SupportsDIORead (1-2-2),Yes=1b Bit19= SupportsDDR, No=0 b Bit18:17 =Number ofAddressBytes3 only=00b Bit16 =SupportsSIOand DIOYes=1b BinaryField:1-1-1-1-0-00-1 NibbleFormat:1111_0001 HexFormat:F1 33h FFh Bits31:24=Unused= FFh 34h JEDEC BasicFlash Parameter Dword-2 FFh Densityin bits,zero based, 32Mb =01FFFFFFh 64Mb =03FFFFFFh

128 Mb =07FFFFFFh

Bits7:5=numberof QIO(1-4-4)Mode cycles=010b Bits 4:0 = number of Fast Read QIO Dummy cycles = 00100b for default latencycode 39h EBh Fas tRead QIO(1-4-4)instructioncode 3Ah 08h Bit s23:21=number ofQuadOut(1-1-4) Mode cycles= 000b Bits 20:16 = number of Quad Out Dummy cycles = 01000b for default latency code 3Bh 6Bh QuadOut (1-1-4)instruction code 3Ch JEDEC B asicFlash Parameter Dword-4 08h Bits7:5=numberof DualOut(1-1-2)Mode cycles= 000b Bits4:0=numberofDual OutDummycycles=01000bfordefaultlatencycode 3Dh 3Bh DualOut(1-1-2) instructioncode 3Eh 80h Bits23:21=number ofDual I/OMode cycles=100b Bits 20:16 = number of Dual I/O Dummy cycles = 00000b for default latency code 3Fh BBh DualI/Oinstructioncode 40h JEDEC BasicFlash Parameter Dword-5 FEh Bits7:5RFU= 111b Bit4 =QPI(4-4-4) fastread commandssupported=1b Bits3:1RFU= 111b Bit0 =DualAllnotsupported=0b 41h FFh Bits15:8=RFU =FFh 42h FFh Bits23:16=RFU =FFh 43h FFh Bits31:24=RFU =FFh 44h JEDEC BasicFlash Parameter Dword-6 FFh Bits7:0=RFU =FFh 45h FFh Bits15:8=RFU =FFh 46h FFh Bits23:21=number ofDualAllMode cycles=111b Bits20:16=number ofDualAllDummycycles= 11111b 47h FFh DualAllinstruction code HM25Q128A

Table5.4 Basic SPI Flash Parameter,JEDEC SFDPRev B (Sheet 2 of 5) SFDP Parameter Relative Byte Address SFDPDword Name Data Description 48h JEDEC BasicFlash Parameter Dword-7 FFh Bits7:0=RFU =FFh 49h FFh Bits15:8=RFU =FFh 4Ah FFh Bits23:21=number ofQPIMode cycles= 010b Bits20:16=number ofQPIDummycycles= 00010b fordefaultlatencycode 4Bh EBh QPIinstructioncode 4Ch JEDEC BasicFlash Parameter Dword-8 0Ch EraseType1 size2 N Bytes=4 kB= 0Ch (forUniform4kB) 4Dh 20h EraseType1 instruction 4Eh 0Fh Era seType2 size2N Bytes=32 kB= 0Fh(for Uniform32kB) 4Fh 52h Erase Type2 instruction 50h JEDEC B asicFlash Parameter Dword-9 10h EraseType3 size2 N Bytes=64kB =10h(for Uniform64 kB) 51h D8h Erase Type3 instruction 52h 00h Era seType4 size2 N Bytes=notsupported= 00h 53h FFh EraseType4 instruction= notsupported=FFh 54h JEDEC BasicFlash Parameter Dword-4 13h Bits 31:30 = Erase Type 4 Erase, Typical time units (00b: 1 ms, 01b: 16 ms, 10b:128 ms,11b:1s)= RFU= 11b Bits29:25 = EraseType 4 Erase,Typical time count = RFU = 11111b (typ erase time= (count+1) *units) =RFU =11111 Bits 24:23 = Erase Type 3 Erase, Typical time units (00b: 1 ms, 01b: 16 ms, 10b:128 ms,11b:1s)= RFU= 01b Bits 22:18 = EraseType 3 Erase,Typical time count = 01111b (typ erase time = (count+1)*units) =16*16 ms=250ms Bits 17:16 = Erase Type 2 Erase, Typical time units (00b: 1 ms, 01b: 16 ms, 10b:128 ms,11b:1s)= 16ms=01b Bits 15:11= Erase Type 2 Erase,Typical time count = 01011b (typ erase time = (count+1)*units) =12*16 ms= 180ms Bits10:9 = EraseType 1 Erase,Typicaltime units(00b: 1 ms, 01b: 16 ms,10b: 128 ms,11b:1s)=16ms=01b Bits 8:4 = Erase Type 1 Erase, Typical time count = 00001b (typ erase time = (count+1)*units) =2*16 ms= 35ms Bits3:0=Count =(Max Erasetime/(2 *TypicalErasetime))- 1= 0011b Multiplierfromtypicalerasetimetomaximumerasetime= 8xmultiplier MaxErasetime= 2*(Count+1)*Typ Erasetime BinaryFields:1111111_0101111_0101011_0100001_0011 NibbleFormat:1111_1110_1011_1101_0101_1010_0001_0011 HexFormat:FE_BD_5A_13 55h 5Ah 56h BDh 57h FEh HM25Q128A

Table5.4 Basic SPI Flash Parameter,JEDEC SFDPRev B (Sheet 3 of 5) SFDP Parameter Relative Byte Address SFDP Dword Name Data Description 58h JEDEC Basic Flash Parameter Dword-11 81h Bits 23 = Byte Program Typical time, additional byte units (0b:1 μs, 1b:8 μs) = 1 μs =0b Bits 22:19 = Byte Program Typical time, additional byte count, (count+1)*units, count= 0010b,(typ Programtime=(count +1)*units) = 3*1μs=3 μs Bits18= ByteProgramTypicaltime,firstbyte units(0b:1 μs,1b:8μs)= 8μs=1b Bits 17:14 = Byte Program Typical time, first byte count, (count+1)*units, count = 0001b,(typ Programtime=(count+1)* units) =2*8 μs=16 μs Bits13= PageProgramTypicaltimeunits(0b:8μs,1b:64μs)=64 μs= 1b Bits 12:8 = Page Program Typical time count, (count+1)*units, count = 00111b, (typ Programtime= (count+1)* units) =8*64 μs=500 μs Bits7:4=N =1000b, Pagesize=2N =256B page Bits 3:0 = Count = 0001b = (Max Page Program time / (2 * Typ Page Program time))- 1 Multiplier from typical Page Program time to maximum Page Program time = 4x multiplier MaxPageProgram time= 2*(Count+1)*TypPage Programtime BinaryFields:0-0010-1-0001-1-00111-1000-0001 Nibble Format:0001_0100_0110_0111_1000_0001 HexFormat:14_67_81 59h 67h 5Ah 14h 5Bh CCh

128 Mb =1100_1100b =CCh

Bit31 Reserved =1b Bits30:29 = Chip Erase,Typicaltimeunits (00b: 16 ms, 01b: 256 ms, 10b: 4 s, 11b: 64 s) =4s=10b Bits 28:24 = Chip Erase, Typical time count, (count+1)*units, count = 01100b, (typ Programtime= (count+1)* units) =13*4s=50s 5Ch JEDEC Basic Flash Parameter Dword-12 EDh Bit31 =Suspend and Resumesupported=0b Bits 30:29 = Suspend in-progress erase max latency units (00b: 128ns, 01b: 1us, 10b:8 μs,11b:64 μs) =1 μs=01b Bits 28:24 = Suspend in-progress erase max latency count = 10011b, max erase suspend latency= (count+1) * units= 20*1μs =20 μs Bits 23:20 = Erase resume to suspend interval count = 0001b, interval = (count +1) *64 μs= 2*64 μs= 128μs Bits19:18 = Suspend in-progressprogram maxlatencyunits(00b:128ns, 01b:1us, 10b:8 μs,11b:64 μs) =1 μs=01b Bits 17:13 = Suspend in-progress program max latency count = 10011b, max erase suspend latency= (count+1) * units= 20*1μs =20 μs Bits 12:9 = Program resume to suspend interval count = 0001b, interval = (count +1) *64 μs=2* 64 μs=128 μs Bit8 =RFU =1b Bits7:4=Prohibitedoperationsduring erasesuspend =xxx0b:May notinitiate anew eraseanywhere (erasenesting notpermitted) +xx1xb:May notinitiate apage program intheerasesuspended sectorsize +x1xxb:May notinitiate aread inthe erasesuspended sectorsize +1xxxb:The eraseand program restrictionsin bits5:4are sufficient =1110b Bits3:0=ProhibitedOperationsDuring Program Suspend =xxx1b:May notinitiate anew erasein theprogram suspendedpage size + xx0xb: May not initiate a new page program anywhere (program nesting not permitted) +x1xxb:May notinitiate aread inthe programsuspended page size +1xxxb:The eraseand program restrictionsin bits1:0are sufficient =1101b BinaryFields:0-01-10011-0001-01-10011-0001-1-1110-1101 Nibble Format:0011_0011_0001_0110_0110_0011_1110_1101 HexFormat:33_16_63_ED 5Dh 63h 5Eh 16h 5Fh 33h HM25Q128A

Table5.4 Basic SPI Flash Parameter,JEDEC SFDPRev B (Sheet 4 of 5) SFDP Parameter Relative Byte Address SFDP Dword Name Data Description 60h JEDEC Basic Flash Parameter Dword-13 7Ah Bits31:24=EraseSuspend Instruction=75h Bits23:16=EraseResumeInstruction= 7Ah Bits15:8=ProgramSuspend Instruction= 75h Bits7:0=ProgramResumeInstruction= 7Ah 61h 75h 62h 7Ah 63h 75h 64h JEDEC Basic Flash Parameter Dword-14 F7h Bit31 =Deep Power-Down Supported =0 Bits30:23=EnterDeep Power-Down Instruction= B9h Bits22:15=Exit Deep Power-Down Instruction=ABh Bits 14:13 = Exit Deep Power-Down to next operation delay units = (00b: 128 ns, 01b:1 μs, 10b:8 μs,11b:64μs)=1 μs= 01b Bits 12:8 = Exit Deep Power-Down to next operation delay count = 00010b, Exit Deep Power-Down tonext operationdelay=(count+1)*units= 3*1μs=3μs Bits7:4=RFU =1111b Bit3:2 =StatusRegister Polling DeviceBusy = 01b: Legacy status polling supported = Use legacy polling by reading the Status Register with 05hinstruction and checkingWIPbit[0](0=ready; 1=busy). Bits1:0=RFU =11b BinaryFields:0-10111001-10101011-01-00010-1111-01-11 Nibble Format:0101_1100_1101_0101_1010_0010_1111_0111 HexFormat:5C_D5_A2_F7 65h A2h 66h D5h 67h 5Ch 68h JEDEC Basic Flash Parameter Dword-15 19h Bits31:24=RFU = FFh Bit23 =Hold and WPDisable= setQE(bit1ofSR2) high= 1b Bits22:20=Quad EnableRequirements = 101b: QE is bit 1 of the status register 2. Status register 1 is read using Read Status instruction 05h. Status register 2 is read using instruction 35h. QE is set via Write Status instruction 01h with two data bytes where bit 1 of the second byte is one.It iscleared via WriteStatuswith two databyteswhere bit1 of thesecond byte iszero. Bits19:160-4-4 Mode EntryMethod =xxx1b:Mode Bits[7:0]=A5hNote:QEmustbe setprior tousingthismode +x1xxb:Mode Bits[7:0]=Axh +1xxxb:RFU =1101b Bits15:100-4-4 Mode Exit Method = xx_xxx1b: Mode Bits[7:0] = 00h will terminate this mode at the end of the current read operation + xx_1xxxb: Input Fh (mode bit reset) on DQ0-DQ3 for 8 clocks.This will terminate themodeprior tothenext read operation. +11_x1xx: RFU =111101b Bit9 =0-4-4 mode supported=1 Bits 8:4 = 4-4-4 mode enable sequences = 0_0001b: set QE per QER description above,then issueinstruction38h Bits3:0=4-4-4 mode disable sequences =xxx1b:issue FFhinstruction +1xxxb:issue theSoftReset66/99sequence =1001b BinaryFields:11111111-1-101-1101-111101-1-00001-1001 Nibble Format:1111_1111-1101-1101-1111_0110_0001-1001 HexFormat:FF_DD_F6_19 69h F6h 6Ah DDh 6Bh FFh HM25Q128A

Table5.4 Basic SPI Flash Parameter,JEDEC SFDPRev B (Sheet 5 of 5) SFDP Parameter Relative Byte Address SFDP Dword Name Data Description 6Ch JEDEC Basic Flash Parameter Dword-16 E8h Bits31:24=Enter4-ByteAddressing =xxxx_xxx1b:issue instructionB7(preceding write enablenot required + xx1x_xxxxb: Supports dedicated 4-byte address instruction set. Consult vendor datasheet forthe instructionsetdefinition or lookfor 4-byteAddressParameterTable. +1xxx_xxxxb: Reserved =10000000b notsupported Bits23:14=Exit 4-byteAddressing = xx_xxxx_xxx1b:issue instruction E9h to exit 4-byte address mode (Write enable instruction 06h isnot required) +xx_xx1x_xxxxb: Hardware reset +xx_x1xx_xxxxb: Software reset(seebits13:8 inthisDWORD) +xx_1xxx_xxxxb: Power cycle +x1_xxxx_xxxxb: Reserved +1x_xxxx_xxxxb: Reserved =11_0000_0000b notsupported Bits13:8=SoftResetand RescueSequenceSupport = x1_xxxxb: issue reset enable instruction 66h, then issue reset instruction 99h. The reset enable, reset sequence may be issued on 1,2, or 4 wires depending on thedeviceoperating mode + 1x_xxxxb: exit 0-4-4 mode is required prior to other reset sequences above if the devicemaybeoperating inthismode. =11_0000b Bit7 =RFU =1 Bits 6:0 = Volatile or Non-Volatile Register and Write Enable Instruction for Status Register 1 = xxx_1xxxb: Non-Volatile/Volatile status register 1 powers-up to last written value in the nonvolatile status register, use instruction 06h to enable write to non-volatile status register. Volatile status register may be activated after power-up to override the non-volatile status register, use instruction 50h to enable write and activate the volatilestatusregister. +x1x_xxxxb: Reserved +1xx_xxxxb: Reserved =1101000b BinaryFields:10000000-1100000000-110000-1-1101000 Nibble Format:1000_0000_1100_0000_0011_0000_1110_1000 HexFormat:80_C0_30_E8 6Dh 30h 6Eh C0h 6Fh 80h HM25Q128A

1. FUNCTION DESCRIPTION 6.1SPI Operations

6.1.1 SPI Modes

The HM25Q128A can be driven by an embedded microcontroller (bus master)in either of the two follow ing clocking modes. Mode0 with Clock Polarity (CPOL) = 0 and, ClockPhase (CPHA) = 0 Mode3 with CPOL= 1and, CPHA= 1 For these two modes, input data is always latched in on therising edge of the CLK signal and the output data is always available on the falling edge of the CLK clock signal. The differencebetween thetwo modes is the clock polarity when the bus master is in standby modeand not transferring any data. CLK will stay at logic low state with CPOL= 0, CPHA= 0 CLKwill stay at logic high state with CPOL= 1, CPHA= 1 Figure 6.1 SPI Modes Timingdiagramsthroughout therestof the document are generally shown as both mode0 and 3 by showing CLKas both high and low at the fall of CS#. In somecases atiming diagram may show only mode 0 with CLK low at the fall of CS#. Insuchcase, mode3 timing simply means clock is high at the fall of CS# so no CLK rising edge set up or hold timetothe falling edge of CS# is needed for mode3. CLK cycles aremeasured (counted) from one falling edge of CLK tothe next falling edgeof CLK. In mode0thebeginningofthefirstCLKcycleinacommandismeasuredfromthefallingedgeofCS#tothefirst falling edge of CLK because CLK is already low at the beginning of a command.

6.1.2 Dual SPI Modes

The HM25Q128A suppo rts Dual SPI Operation when using the Fast Read Dual Output (3Bh) and Fast Dual I/O ( BBh) instruction. These features allow data to be transferred from the device at twicethe rate possible with the standard SPI.These instructions are ideal for quickly downloading code toRAM upon Power-up (code-shadowing) or forexecuting non-speed-critical code directly from the SPI bus (XIP). When using Dual SPI commands, the DI and DO pins becomebidirectional I/O pins: IO0 and IO1.

6.1.3 Quad SPI Modes

The HM25Q128A suppo rtsQuadSPI operationwhenusingtheFastReadQuadOutput(6Bh),FastRead Quad I/O ( EBh) instruction, WordRead Quad I/O(E7h), and Octal WordRead Quad I/O(E3h).These instructions allow data to be transferred toor from the devicefour times the rateof ordinary Serial Flash. The Quad Read instructions offer asignificant improvement in continuous and random accesstransfer rates HM25Q128A

allowing fast code-shadowing to RAM or execution directly from the SPI bus (XIP). When using Quad SPI instructions, the DI and DO pins becomebidirectional IO0and IO1, and the WP#and HOLD# / RESET#pins becomeIO2 and IO3respectively.Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set.

6.1.4 QPI Function

The HM25Q128A suppor ts Quad Peripheral Interface (QPI) operations when the device is switched from Standar d/Dual/Quad SPI mode to QPI mode using the “Enter QPI (38h)” instruction. The typical SPI protocol requires that the byte-long instruction code being shifted into the device only via DI pin in eight serial clocks. The QPI mode utilizes all four IO pins to input the instruction code, thus only two serial clocks are required. This can significantly reduce the SPI instruction overhead and improve system performance in an XIP environment. Standard/Dual/Quad SPI mode and QPI mode are exclusive. Only one mode can be active at any given time. “Enter QPI (38h)” and “Exit QPI (FFh)” instructions are used to switch between these two modes. Upon power-uporafter asoftwarereset using “Reset (99h)” instruction, thedefault stateof the device is Standard/Dual/Quad SPI mode. To enable QPI mode, the non-volatile Quad Enable bit (QE) in Status Register-2 is required to be set. When using QPI instructions, the DI and DO pins become bidirectional IO0 and IO1, and the WP# and HOLD# / RESET#pins becomeIO2 and IO3 respectively.

6.1.5 Hold Function

ForStandardSPIandDualSPIoperations,theHOLD#/RESET#(IO3)signalallowsthedeviceinterface operation tobe paused while it is actively selected (when CS# is low). The Hold function may be usefulin cases where the SPI data and clock signals areshared with other devices. For example, if the page bufferis only partiallywritten whena priorityinterrupt requires useof the SPI bus, the Hold functioncansave thestate of theinterfaceandthedatainthebuffersoprogrammingcommandcanresumewhereit left offoncethebus is available again.The Holdfunction is only available for standard SPI and Dual SPI operation, not during Quad SPI. Toinitiate a Hold condition, the device must be selected with CS# low.AHold condition will activate on the falling edge of the HOLD# signal if the CLK signal is already low.If the CLK is not already low theHold conditionwillactivateafterthenextfallingedgeofCLK.TheHoldconditionwillterminate ontherising edgeof the HOLD# signal if the CLKsignal is already low.If the CLKis not already low the Hold condition will terminate after the next falling edge of CLK. During aHold condition, the Serial Data Output, (DO) or IO0 and IO1, are high impedance and Serial Data Input, (DI) or IO0and IO1, and Serial Clock (CLK) are ignored. The Chip Select (CS#) signal should be kept active (low) forthe full duration of the Hold operation to avoid resetting the internal logic state of thedevice.

6.1.6 Software Reset & Hardware RESET# pin

The HM25Q128A can be reset to the initial power-on stateby asoftware Reset sequence, either in SPI mode or QPI mode.This sequencemust include two consecutive commands: Enable Reset (66h) & Reset (99h). If the command sequenceis successfully accepted, the devicewill takeapproximately 10us (tRST) to reset. Nocommandwill be accepted duringthe reset period. HM25Q128A canal so be configured to utilize a hardwareRESET# pin. TheHRSW bit in the Status Registe r-3 is the configuration bit for HOLD# pin function or RESET#pin function. WhenHRSW=0 (factory default), thepin acts as a HOLD#pin as described above; when HRSW =1, the pin acts as aRESET# pin. Drive the RESET#pin low for a minimum period of ~1us (tRESET*) will reset the device to its initial power-on state.Any on-going Program/Erase operation will be interrupted and data corruption may happen. While RESET# is low,the device will not accept any command input. If QE bit is set to1, the HOLD#or RESET# function will bedisabled, the pin will becomeone of the four data I/O pins. HardwareRESET# pin has the highest priority among all the input signals. Drive RESET# low fora minimumperiod of~1us (tRESET*) will interrupt any on-goingexternal/internaloperations, regardlessthe status of other SPI signals (CS#, CLK, DI, DO, WP#and/or HOLD#). Note: HM25Q128A

1.WhileafasterRESET# pulse(asshortasafewhundred nanoseconds)will oftenresetthedevice,a 1usminimumisrecommendedto ensure reliableoperation. 6.2. StatusRegister The Read and WriteStatus Registers commands canbe used toprovide status and control of theflash memorydevice. Status Register-1 (SR1) and Status Register-2 (SR2) canbe used toprovide status on the availability of the flashmemory array,whether the device is write enabled or disabled, the state of write protection, Quad SPI setting, Security Register lock status, and Erase / Program Suspend status. SR1 and SR2 contain non-volatile bits in locations SR1[7:2] and SR2[6:3], SR2[1] that control sector protection, OTPRegister Protection, Status Register Protection, and Quad mode. Bits located in SR2[7], SR1[1], and SR1[0] are read only volatile bits for suspend, write enable, and busy status.These areupdated by the memory control logic.The SR1[1] write enable bit is set only by the WriteEnable (06h) command and cleared by the memorycontrol logic when an embedded operation is completed. Writeaccessto the non-volatile Status Register bits is controlled by the state of thenon-volatile Status Register Protect bits SR1[7] and SR2[0] (SRP0, SRP1), the WriteEnable command(06h) preceding aWrite Status Registers command, and while Quad mode is not enabled, the WP#pin. Avolatile versionof bits SR2[6], SR2[1], and SR1[7:2] that control sector protection and QuadMode is used to control the behavior of these features after power up. During power up or software reset, these volatile bitsare loaded from thenon-volatile version of the Status Register bits.TheWriteEnable for Volatile Status Register (50h) commandcan beused to write these volatile bits when the command is followed by a WriteStatusRegisters(01h/31h/11h)command.Thisgivesmoreflexibilitytochangethesystemconfiguration and memoryprotection schemesquickly without waitingforthe typicalnon-volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. Writeaccessto the volatile SR1, SR2 and SR3 Status Register bits is controlled by the stateof the non-volatile Status Register Protect bits SR1[7] and SR2[0] (SRP0, SRP1), the WriteEnable for Volatile Status Register command(50h) preceding aWrite Status Registers command, and the WP#pin while Quad mode is not enabled. Status Register-3 (SR3) is used to configure and provide status onthe variableHOLD#or RESET# function, Output Driver Strength, High Frequency Enable Bit, WriteProtect Selection and read latency. Writeaccessto the volatile SR3 Status Register bitsis controlled by Write Enablefor VolatileStatus Register command(50h) preceding aWriteStatus Register command. HM25Q128A

Table6.1Status Register-1 (SR1) Bits Field Function Type Default State Description

7 SRP0 StatusRegister

0 = WP# input has no effect or Power Supply LockDownmode 1 = WP# input can protect the Status Register or OTPLockDown.

6 SEC Sector/Block

Protect 0 0 =BP2-BP0protect64-kBblocks 1 =BP2-BP0protect4-kBsectors

5 TB Top/Bottom

protect 0 0 =BP2-BP0protectfromtheTopdown 1 =BP2-BP0protectfromtheBottomup

4 BP2 BlockProtect

000b = Noprotection3 BP1 0

2 BP0 0

1 WEL WriteEnable

Volatile, Readonly 0 0 = Not Write Enabled, no embedded operation canstart 1 = Write Enabled, embedded operation can start

0 BUSY

Volatile, Readonly 0 0 = Not Busy, no embedded operation in progress 1 =Busy,embeddedoperation inprogress Table6.2Status Register-2 (SR2) Bits Field Function Type Default State Description

7 SUS SuspendStatus Volatile,Read

Only 0 0 =Erase/Programnotsuspended 1 =Erase/Programsuspended

6 CMP Complement

Volatileversions 0 0 =NormalProtectionMap 1 =ComplementaryProtectionMap

5 LB3

0 OTP Lock Bits 3:0 for Security Registers

3:0 0 =SecurityRegister notprotected 1 =SecurityRegister protected

4 LB2 0

3 LB1 0

2 Reserv

1 QE QuadEnable

0 = Quad Mode Not Enabled, the WP# pin and HOLD# /RESET#areenabled 1 = Quad Mode Enabled, the IO2 and IO3 pins are enabled, and WP# and HOLD# / RESET#functionsare disabled

0 SRP1 StatusRegister

0 = SRP1 selects whether WP# input has effecton protectionof thestatusregister 1 = SRP1 selectsPower SupplyLockDown or OTPLockDown mode Note: 1. Reserved bit should beconsidered don'tcarefor read. HM25Q128A

Table6.3 Status Register-3 (SR3) Bits Field Function Ty pe Default State Descript ion

7 HRSW

HOLD#or RESET# function Non-volatile andVolatile versions WhenHRSW=0,thepin actsasHOLD#;when HRSW=1, the pin acts as RESET#. HRSW functionsare onlyavailablewhen QE=0.

6 DRV1

The DRV1 & DRV0 bits are used to determine the output driver strength for the Read operations.

5 DRV0 0

4 HFQ

0 0=High FrequencyMode Disabled 1= HighFrequencyMode Enabled

3 Reserve 0

2 WPS WriteProtect

When WPS=0, the device will use the combination of CMP, SEC, TB, BP[2:0] bits to protect a specific area of the memory array. When WPS=1, the device will utilize the Individual Block Locks to protect any individual sectororblocks.

1 Latency

(LC) VariableSPI Read Latency Control

0 Defines the number of read latency cycles in

Fast Read, Dual Out, Quad Out, Dual IO, and QuadIOcommands.SeedetailsinTable6.5.0 0 Note: 1.LC[1:0]onlycontrolsSPIread latencyandwillbe resettodefaultwhile switchingfromQPItoSPI.QPIread latencyissetbyC0 instruction.

6.2.1 BUSY

BUSYis aread only bit in the status register (SR1[0]) which is set toa “1” state when the device is executing a Page Program,Sector Erase, Block Erase, Chip Erase or Write Status Register instruction. During this timethe device will ignore further instructions except for the Read Status Register instruction (see tW, tPP, tSE, tBE, andtCE inAC Characteristics). When theprogram, eraseor writestatus register instruction has completed, the BUSYbit will be cleared to a“0” state indicating the device is ready forfurther instructions.

6.2.2 WriteEnable Latch (WEL)

WriteEnableLatch (WEL) is a read only bit in the status register (SR1[1])which is set to a1 after executing aWrite Enable Instruction.The WELstatus bit is cleared toa0when the deviceis written disabled. Awrite disable state occursupon power-up or afterany of thefollowing instructions: Write Disable, Page Program, Sector Erase, Block Erase, Chip Eraseand Write Status Register.

6.2.3 Block Protect Bits (BP2, BP1, BP0)

TheBlock Protect Bits(BP2, BP1, BP0) arenon-volatile read/ writebits inthe StatusRegister (SR1[4:2])that provide Write Protection control and status. Block Protect bits can beset using the WriteStatus Registers Command (seetWin Section 8.5).All, none or aportion of the memoryarray can beprotected from Program and Erasecommands (seeSection 6.4.2, Block Protection Maps).Thefactory default settingfor the Block Protection Bits is 0(none of thearray is protected.)

6.2.4 Top/ Bottom Block Protect (TB)

The non-volatile Top/ Bottom bit (TBSR1[5]) controls whether the Block Protect Bits (BP2, BP1, BP0) protect from theTop(TB=0) or the Bottom (TB=1) of the array as shown in Section 6.4.2, Block Protection Maps.Thefactory default setting isTB=0.TheTB bit can beset with the WriteStatus Registers Command depending onthe stateof the SRP0, SRP1 and WELbits. HM25Q128A

6.2.5 Sector/ Block Protect (SEC)

Thenon-volatile Sector/ Block Protectbit (SEC SR1[6]) controlsif theBlockProtect Bits (BP2, BP1, BP0) protect either 4-kBSectors (SEC=1) or 64-kBBlocks (SEC=0) of the array as shown in Section6.4.2, Block Protection Maps.The default setting is SEC=0.

6.2.6 Complement Protect (CMP)

TheComplementProtect bit(CMPSR2[6])isanon-volatile read/writebitintheStatusRegister(SR2[6]). It is used in conjunction with SEC,TB, BP2, BP1 and BP0 bits to provide moreflexibility for the array protection. OnceCMPis set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP0 will be reversed. For instance, when CMP=0, atop 4-kB sector canbe protected while therest of the array is not; when CMP=1, the top 4-kB sector will becomeunprotected while therest of the array becomeread-only. Refer to Section 6.3.2, Block Protection Maps for details.The default setting is CMP=0.

6.2.7 TheStatus Register Protect (SRP1, SRP0)

TheStatusRegisterProtectbits(SRP1andSRP0)arenon-volatile read/writebitsintheStatusRegister (SR2[0] and SR1[7]).The SRPbits control the method of write protection: software protection, hardware protection, power supply lock-down, or one timeprogrammable (OTP)protection. Table 6.4 Status Register Protect SRP1 SRP0 WP# StatusRe gister Descript ion 0 0 X Software Protection WP# pin has no control. SR1 ,SR2 and SR3 can be written to aftera WriteEnablecommand,WEL=1.[FactoryDefault] 0 1 0 Hardware Protected When WP# pin is low the SR1, SR2 and SR3 are locked and cannotbe written. 0 1 1 Hardware Unprotected When WP# pin is high SR1 ,SR2 and SR3 are unlocked and canbewrittentoaftera WriteEnablecommand,WEL=1. 1 0 X Power SupplyLock Down SR1,SR2and SR3are protectedand cannotbe writtento again untilthenext power-down,power-up cycle. (1) 1 1 X OneTimeProgram (2) SR1 ,SR2 and SR3 are permanently protected and cannot be written. Notes: 1.When SRP1,SRP0=(1,0), apower-down,power-up, or Software ResetcyclewillchangeSRP1,SRP0to(0, 0)state. 2.TheOne-TimeProgramfeature isavailableupon specialorder.ContactZbitfor details. 3. Busy, WEL, and SUS (SR1[1:0] and SR2[7]) are volatile read only status bits that are never affected by the Write Status Registerscommand. 4. The non-volatile version of CMP, QE, SRP1, SRP0, SEC, TB, and BP2-BP0 (SR2[6,1,0] and SR1[6:2]) bits and the OTP LB3-LB1 bits are not writable when protected by the SRP bits and WP# as shown in the table. The non-volatile version of theseStatusRegister bitsisselectedfor writingwhen theWriteEnable (06h) command precedesthe WriteStatusRegisters (01h) command. 5. The volatile version of HRSW, DRV1, DRV0, HFQ, WPS, CMP, QE, SRP1, SRP0, SEC, TB, and BP2-BP0 (SR3[7:4,2], SR2[6,1,0] and SR1[6:2]) bits are not writable when protected by the SRP bits and WP# as shown in the table. The volatile version of these Status Register bits is selected for writing when the Write Enable for volatile Status Register (50h) command precedes the Write Status Registers (01h) command. There is no volatile version of the LB3-LB1 bits and these bitsare not affectedbyavolatile WriteStatusRegisterscommand.

6.2.8 Erase / Program Suspend Status (SUS)

The Suspend Status bit is aread only bit in the status register (SR2[7]) that is set to 1after executing an Erase / Program Suspend (75h) command.The SUS status bit is cleared to 0by Erase / Program Resume (7Ah) commandas well as a power-down, power-upcycle.

6.2.9 Security Register LockBits(LB3, LB2, LB1)

The Security Register Lock Bits (LB3, LB2, LB1) arenon-volatile OneTimeProgram (OTP) bits in Status Register (SR2[5:3]) that provide the write protect control and status to the Security Registers.The default stateofLB[3:1]is0,SecurityRegisters1to3areunlocked.LB[3:1] canbesetto1individuallyusingtheWrite HM25Q128A

Status Registerscommand. LB[3:1] are OneTimeProgrammable (OTP), once it’s set to 1, the corresponding 256-byte Security Register will becomeread-only permanently.

6.2.10 Quad Enable (QE)

The Quad Enable(QE) bit is anon-volatile read/ write bit in the Status Register (SR2[1]) that allows Quad SPI operation. When the QE bit is set toa 0 state(factory default), the WP#pin and HOLD# / RESET# are enabled. When the QEbit is set to a1, the Quad IO2and IO3pins are enabled, and WP#and HOLD#/ RESET# functions are disabled. Note:IftheWP#orHOLD#/RESET#pinsaretieddirectlytothepowersupplyorground duringstandardSPIorDualSPIoperation,the QEbitshouldnever be settoa 1. 6.2.11HOLD#or RESET# Pin Function (HRSW) The HRSW bit is used to determine whether HOLD# or RESET#function should be implemented on the hardware pin for8-pin packages. When HRSW=0, the pin acts as #HOLD; when HRSW=1, the pin acts as RESET#. However,HOLD#orRESET#functionsareonlyavailable when QE=0. IfQEisset to1, theHOLD# and RESET#functions are disabled, the pin acts as a dedicated data I/O pin.

6.2.12 OutputDriver Strength (DRV1, DRV0)

The DRV1 &DRV0 bits are usedto determine the output driver strength for the Read operations. DRV1,DRV0 DriverStrength 0,0 50% 0,1 25% 1,0 75%(default) 1,1 100%

6.2.13 High Frequency Enable Bit (HFQ)

The HFQ bit is used to determine whether the device is in Quad High Frequency Mode. WhenHFQ bit sets to 1, it means the device is in Quad High Frequency Mode, when HFQ bit sets 0(default), it means the device is not in Quad High Frequency Mode.This Mode allows pre-charge of internal charge pump, so the voltages required for accessing the flashmemoryarray are readily available for Quad read.After the HFQ is executed, the device will maintain aslightly higher standby current (ICC8) than standard SPI operation.

6.2.14 WriteProtect Selection (WPS)

TheWPSbit isusedtoselect whichWriteProtectschemeshouldbeused. WhenWPS=0, thedevicewill use the combination of CMP,SEC, TB, BP[2:0] bits toprotect a specific area of thememory array.When WPS=1, thedevicewillutilize theIndividualBlockLockstoprotect anyindividualsectororblocks.Thedefault value for all Individual Block Lock bits is 1 upon device power on or afterreset.

6.2.15 Latency Control (LC)

Status Register-3 provides bits (SR3[1:0]) to select the number of read latency cycles used in each Fast Read command(only in SPI mode). The Read Data command is not affected by the latency code. The binary value of this field selects from 2,4,6 latency cycles. The default is 0 to provide backward compatibility to legacy devices. The Latency Control bits may be set to select a number of read cycles optimized for the frequency in use. If the number of latency cycles is not sufficient for the operating frequency, invalid data will be read. HM25Q128A

Table 6.5 Latency Cycles Versus Frequency for-40°C to 85°C/105°C at 2.3Vto 3.6V LatencyControl ReadCommandMaximumFrequency ( MHz) FastRead Dual Output D ualI/O Quad Output QuadI/O WordRead QuadI/O (legacyread latency) 104 (8 dummy) 104 (8 dummy) 104 (4 mode,0 dummy) 104 (8 dummy) 104 (2 mode,4 dummy) 104 (2 mode,2 dummy) 01(2 dummy) 104 104 104 90 75 104 10(4 dummy) 104 104 104 104 104 1 04 11(6dummy) 104 104 104 104 104 104 Notes: 1.The defaultdummyreferred in thisdocumentisthedummyconfigurationwhen LC[1:0]=0. 2.Valueguaranteed bydesign and/orcharacterization,not100%testedin production. 6.3. WriteProtection Applications that use non-volatile memory must take into consideration the possibility of noise andother adverse system conditions that may compromise data integrity. To address this concern the ZB25VQ128 provides the following data protectionmechanisms:

6.3.1 WriteProtect Features

 Deviceresets when VCC is below threshold  Timedelay write disable after Power-Up  Writeenable / disable commands and automatic write disable after erase or program  Commandlength protection - Allcommandsthat Write, Program orErasemustcompleteonabyteboundary(CS#drivenhighafter afull 8bits have been clocked) otherwise thecommand will be ignored.  Software and Hardwarewrite protection using Status Register control - WP#input protection - Lock Down write protection until next power-up or Software Reset - One-TimeProgram (OTP) write protection  Additional Individual Block/Sector Locks for array protection  WriteProtection using the Deep Power-Down command Upon power-up or at power-down, the HM25Q128Awill m aintain areset condition whileVCC is below the thresho ld value of VWI, (seeFigure 8.1). While reset, all operations are disabledand no commands are recognized. During power-upand after the VCC voltage exceeds VWI, all program and erase related commands are further disabled for atimedelay of tPUW.This includes the Write Enable, PageProgram, Sector Erase, Block Erase, Chip Erase and the WriteStatus Registers commands. Note that thechip select pin (CS#) must track the VCC supply level at power-up until the VCC-minlevel and tVSLtimedelay is reached. If needed apull-up resistor on CS# can be usedto accomplish this. After power-up thedevice is automatically placed in a write-disabled state with the Status Register Write Enable Latch (WEL) set to a0.AWriteEnable commandmust be issued before aPage Program, Sector Erase, Block Erase, Chip Eraseor WriteStatus Registers command will be accepted.After completing a program, eraseor write command the WriteEnable Latch(WEL) is automatically cleared to awrite-disabled state of 0. Software controlled main flasharray write protection is facilitated using the WriteStatus Registers commandto write the Status Register (SR1,SR2) and Block Protect (SEC,TB, BP2, BP1and BP0) bits. HM25Q128A

The BPmethod allows a portion as smallas 4-kBsector or theentire memoryarray to be configured as read only.Used in conjunction with the Write Protect (WP#) pin, changes to the Status Register canbe enabled or disabled under hardware control. See theTable6.4for further information. The HM25Q128A also p rovides another WriteProtect method using the Individual Block Locks. Each 64KBbl ock(except thetopand bottom blocks,total of 126blocks)andeach 4KB sectorwithinthetop/bottom blocks (total of 32 sectors)are equipped with an Individual Block Lock bit. When the lock bit is 0, the corresponding sector or block canbe erased or programmed; when the lock bit is set to 1, Erase or Program commands issued to the corresponding sector or block will be ignored. When the device is powered on, all Individual Block Lock bits will be 1, sothe entirememory array is protected from Erase/Program.An “Individual Block Unlock (39h)” instruction must be issued to unlockany specific sector or block. Additionally,theDeepPower-Down (DPD)commandoffersanalternative means ofdata protection as all commands are ignored duringthe DPD state, except for the Release from Deep-Power-Down (RESABh) command.Thus, preventing any program or erase during theDPD state. HM25Q128A

6.3.2 Block Protection Maps

Table 6.6 HM25Q128A Block Protection (WPS = 0,CMP= 0) Status Register(1) ZB25VQ128(128 Mbit)BlockProtection(CMP=0) (2) SEC TB BP2 BP1 BP0 ProtectedBlock(s) ProtectedAddresses Protected Density Protected Portion X X 0 0 0 None None None None 0 0 0 0 1 252thru 255 FC0000h– FFFFFFh 256KB Upper 1/64 0 0 0 1 0 248thru 255 F80000h –FFFFFFh 512kB Upper 1/32 0 0 0 1 1 240thru 255 F00000h –FFFFFFh 1MB Upper 1/16 0 0 1 0 0 224thru 255 E00000h–FFFFFFh 2MB Upper 1/8 0 0 1 0 1 192thru 255 C00000h– FFFFFFh 4MB Upper 1/4 0 0 1 1 0 128thru 255 800000h – FFFFFFh 8MB Upper 1/2 0 1 0 0 1 0 thru3 000000h –03FFFFh 256kB Lower 1/64 0 1 0 1 0 0 thru7 000000h –07FFFFh 512kB Lower 1/32 0 1 0 1 1 0thru 15 000000h –0FFFFFh 1MB Lower 1/16 0 1 1 0 0 0thru 31 000000h –1FFFFFh 2MB Lower 1/8 0 1 1 0 1 0thru 63 000000h –3FFFFFh 4MB Lower 1/4 0 1 1 1 0 0 thru127 000000h –7FFFFFh 8MB Lower 1/2 X X 1 1 1 0 thru255 000000h – FFFFFFh 16 MB All 1 0 0 0 1 255 FFF000h– FFFFFFh 4 kB Upper 1 0 0 1 0 255 FFE000h– FFFFFFh 8 kB Upper 1 0 0 1 1 255 FFC000h–FFFFFFh 16 kB Upper 1 0 1 0 X 255 FF8000h–FFFFFFh 32 kB Upper 1 1 0 0 1 0 000000h –000FFFh 4 kB Lower 1 1 0 1 0 0 000000h –001FFFh 8 kB Lower 1 1 0 1 1 0 000000h –003FFFh 16 kB Lower 1 1 1 0 X 0 000000h –007FFFh 32 kB Lower Notes: 1.X=don’tcare. 2.IfanyEraseorProgramcommandspecifiesamemoryregionthatcontainsprotecteddataportion,thiscommandwillbeignored. HM25Q128A

Table6.7 HM25Q128A Block Protection (WPS= 0,CMP= 1) Status Register(1) ZB25VQ1 28(128 Mbit)BlockProtection(CMP=1) (2) SEC TB BP2 B P1 BP0 ProtectedBlock(s) ProtectedAddresses Protected Density Protected Portion X X 0 0 0 0 thru255 000000h – FFFFFFh 16 MB All 0 0 0 0 1 0 thru251 000000h – FBFFFFh 16,128kB Lower 0 0 0 1 0 0 thru247 000000h –F7FFFFh 15,872kB Lower 0 0 0 1 1 0 thru239 000000h – EFFFFFh 15 MB Lower 0 0 1 0 0 0 thru233 000000h –DFFFFFh 14 MB Lower 7/8 0 0 1 0 1 0 thru191 000000h – BFFFFFh 12 MB Lower 3/4 0 0 1 1 0 0 thru127 000000h –7FFFFFh 8MB Lower 1/2 0 1 0 0 1 4 thru255 040000h – FFFFFFh 16,128kB Upper 0 1 0 1 0 8 thru255 080000h – FFFFFFh 15,872kB Upper 0 1 0 1 1 16 thru255 100000h – FFFFFFh 15 MB Upper 0 1 1 0 0 32 thru255 200000h – FFFFFFh 14 MB Upper 7/8 0 1 1 0 1 64 thru255 400000h – FFFFFFh 12 MB Upper 3/4 0 1 1 1 0 128thru 255 800000h – FFFFFFh 8MB Upper 1/2 X X 1 1 1 None None None None 1 0 0 0 1 0 thru255 000000h – FFEFFFh 16,380 KB Lower 1 0 0 1 0 0 thru255 000000h –FFDFFFh 16,376kB Lower 1 0 0 1 1 0 thru255 000000h – FFBFFFh 16,368kB Lower 1 0 1 0 X 0 thru255 000000h –FF7FFFh 16,352kB Lower 1 1 0 0 1 0 thru255 001000h –1FFFFFh 16,380 KB Upper 1 1 0 1 0 0 thru255 002000h –1FFFFFh 16,376kB Upper 1 1 0 1 1 0 thru255 004000h –1FFFFFh 16,368kB Upper 1 1 1 0 X 0 thru255 008000h –1FFFFFh 16,352kB Upper Notes: 1.X=don’tcare. 2.IfanyErase orProgramcommandspecifiesa memoryregion thatcontainsprotecteddataportion,thiscommandwillbe ignored. HM25Q128A

6.3.3 Individual Block Memory Protection (WPS=1)

Figure 6.2 Individual Block/Sector Locks Notes: 1.IndividualBlock/Sector protection isonlyvalidwhen WPS=1. 2.Allindividualblock/sector lockbitsare setto1 bydefaultafter power up,allmemoryarrayisprotected. HM25Q128A

6.4. PageProgram Toprogram one data byte, two instructions are required: WriteEnable (WREN), whichis one byte, and a PageProgram (PP)sequence,whichconsistsoffourbytesplusdata.ThisisfollowedbytheinternalProgram cycle (of duration tPP).Tospread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time(changing bits from 1 to0), provided that they lie in consecutive addresses onthe samepage of memory. 6.5. SectorErase, BlockEraseand ChipErase The PageProgram (PP) instruction allows bits tobe reset from 1 to0. Before this canbe applied, the bytes of memoryneed tobe erased to all 1s (FFh).This canbe achieved asector at atime, using theSector Erase (SE) instruction, a block at atimeusing the Block Erase (BE) instruction or throughout the entire memory,using the Chip Erase (CE) instruction.This starts aninternal Erase cycle (of duration tSE tBE or tCE). The Erase instruction must bepreceded by a Write Enable(WREN) instruction. 6.6. Pollingduringa Write,ProgramorEraseCycle Afurther improvement in the time toWriteStatus Register (WRSR), Program (PP) or Erase (SE, BE or CE)canbeachievedbynotwaitingfortheworstcasedelay(t W,tPP,tSE,tBE ortCE).TheWriteInProgress(WIP) bit is provided inthe Status Register sothat the application program canmonitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete. 6.7.Active Power,Stand-byPowerandDeep Power-DownModes When Chip Select (CS#) is Low,the device is enabled, andin theActive Power mode. WhenChip Select (CS#) is High, the device is disabled, but could remainin theActive Power mode until all internal cycles have completed(Program,Erase, WriteStatus Register).Thedevice thengoes into theStandbyPower mode.The device consumption drops toICC1. TheDeepPower-downmodeisenteredwhenthespecificinstruction (theEnter DeepPower-downMode (DP)instruction)isexecuted.Thedeviceconsumption dropsfurthertoICC2.Thedeviceremainsinthismode until another specific instruction (the Release from Deep Power-down Mode and Read Device ID (RDI) instruction) is executed. All other instructions areignored while the device is in the Deep Power-down mode.This can beused as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent Program or Erase instructions. HM25Q128A

1. INSTRUCTIONS The instruction set of the HM25Q128A consis ts of forty basic instructions that are fully controlled through the SPI b us. Instructions areinitiated with the falling edge of Chip Select (CS#).Thefirst byte of data clocked intotheDIinput provides theinstructioncode. DataontheDIinput issampledontherising edgeofclockwith most significant bit (MSB) first. The QPI instruction set of the HM25Q128A consis ts of 32 basic instructions that are fully controlled through the SPI bus (seeInstruction Set Table 7.5). Instructions are initiated with the falling edge of Chip Select (CS#).Thefirstbyte ofdataclockedthroughIO[3:0] pinsprovides theinstruction code. Dataonall four IO pins aresampled on the rising edge of clockwith mostsignificant bit (MSB) first.All QPI instructions, addresses,dataanddummybytesareusingallfourIOpinstotransfereverybyteofdatawitheverytwoserial clocks (CLK). Instructionsvaryinlengthfromasinglebytetoseveralbytesandmaybefollowedbyaddressbytes,data bytes,dummybytes(don’tcare),andinsomecases,acombination.Instructionsarecompletedwiththerising edgeof edgeCS#. Clockrelativetimingdiagramsforeach instruction areincludedin figures7.1through7.47 All read instructions can be completed afterany clocked bit. However,all instructions that Write, Program or Erase must complete on abyte boundary (CS driven high after a full 8-bits have been clocked) otherwise the instruction will be ignored. This feature further protects thedevice from inadvertent writes.Additionally,while the memoryis being programmed or erased, or when the Status Register is being written, all instructions except forRead Status Register andErase/Program Suspend will beignored untilthe program or erasecycle completes. HM25Q128A

Table7.1Command Set (Configuration, Status, Erase, Program Instructions(1), SPI Mode) CommandName BYTE 1 (Instruction) BYTE2 BYTE3 BYTE4 BYTE5 BYTE 6 ReadStatusRegister-1 05h SR1[7:0] (2) ReadStatusRegister-2 35h SR2[7:0] (2) ReadStatusRegister-3 15h/33h SR3[7:0] (2) WriteEnable 06h Write Enable for Volatile StatusRegister 50h WriteDisable 04h WriteStatusRegisters-1 01h SR1[7:0] (5) WriteStatusRegisters-2 31h SR2[7:0] WriteStatusRegisters-3 11h SR3[7:0] SetBurstwithWrap 77h xxh xxh xxh W[7:0] (3) GlobalBlockLock 7Eh GlobalBlockUnlock 98h ReadBlockLock 3Dh A23—A16 A15—A8 A7—A0 L7—L0 IndividualBlockLock 36h A23—A16 A15—A8 A7—A0 IndividualBlockUnlock 39h A23—A16 A15—A8 A7—A0 PageProgram 02h A23—A16 A15—A8 A7—A0 D7—D0 QuadPageProgram 32h A23—A16 A15—A8 A7—A0 D7—D0 (4) SectorErase (4KB) 20h A23—A16 A15—A8 A7—A0 BlockErase(32 KB) 52h A23—A16 A15—A8 A7—A0 BlockErase(64 KB) D8h A23—A16 A15—A8 A7—A0 ChipErase C7h/60h Erase/Program Suspend 75h Erase/ProgramResume 7Ah EnterQPIMode 38h EnableReset 66h ResetDevice 99h Notes: 1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “()” indicate data being read fromthedeviceon theDOpin. 2.StatusRegister contentswillrepeat continuouslyuntilCS#terminatesthecommand. 3.SetBurstwithWrap Inputformat. IO0= x,x, x, x, x,x, W4,x] IO1= x,x, x, x, x,x, W5,x] IO2= x,x, x, x, x,x, W6x] IO3= x,x, x, x, x,x, x,x 4.Quad PageProgramInputData: IO0=(D4,D0,...) IO1= (D5,D1,...) IO2= (D6,D2,...) IO3=( D7,D3,...) 5.The 01hcommand couldcontinuouslywriteup tothree bytestoregistersSR1,SR2,SR3. HM25Q128A

Table 7.2 Command Set (Read Instructions(1), SPI Mode) CommandName BYTE1 (Instruction) BYTE 2 BYTE 3 BYTE4 BYTE5 BYTE 6 ReadData 03h A23—A16 A15—A8 A7—A0 (D7—D0,…) FastRead 0Bh A23—A16 A15—A8 A7—A0 dummy (D7—D0,…) FastReadDual Output 3Bh A23—A16 A15—A8 A7—A0 dummy (D7—D0,…) (1) FastReadQuad Output 6Bh A23—A16 A15—A8 A7—A0 dummy (D7—D0,…) (3) FastReadDualI/O BBh A23—A8 (2) A7—A0,M7 FastReadQuad I/O EBh A23—A0,M7 —M0(4) (x,x,x,x,D7— QUADI/OWORD FASTREAD(5) E7H A23—A0,M7 —M0(4) (x,x,D7—D0, ...) (D7—D0,…)(3) OctalWord Read QuadI/O(5) E3h A23—A0,M7 —M0(4) (D7—D0,…)( 3) (D7—D0,…)(3) Notes: 1.Dual Outputdata IO0= (D6,D4,D2, D0) IO1= (D7,D5,D3, D1) 2.Dual InputAddress IO0=A22,A20,A18,A16,A14,A12,A10,A8A6,A4,A2,A0,M6,M4, M2, M0 IO1=A23,A21,A19,A17,A15,A13,A11,A9A7,A5,A3,A1,M7,M5, M3, M1 3.Quad OutputData IO0= (D4,D0,…..) IO1= (D5,D1,…..) IO2= (D6,D2,…..) IO3= (D7,D3,…..) 4.Quad InputAddress IO0=A20,A16,A12,A8,A4,A0,M4, M0 IO1=A21,A17,A13,A9,A5,A1,M5, M1 IO2=A22,A18,A14,A10,A6,A2,M6, M2 IO3=A23,A19,A15,A11,A7,A3,M7, M3 5. For Word Read Quad I/O, the lowest address bit must be 0. (A0 = 0),and for Octal Word Read Quad I/O, the lowest four addressbitsmustbe 0.(A3,A2,A1,A0= 0) HM25Q128A

Table7.3 CommandSet (Read ID, OTPInstructions(1), SPI Mode) Command Name BYTE 1 (Instruction) BYTE 2 BYTE 3 BYTE4 BYTE 5 BYTE 6 Deep Power-down B9h Release Power down / DeviceID ABh dummy dummy dummy DeviceID (1) Manufacturer/ DeviceID(2) 90h dummy dummy 00h Manufacturer DeviceID Manufacturer/ DeviceIDby DualI/O Manufacturer/ DeviceIDby QuadI/O 94h A23—A0,M[7:0] XXXX,(MF[7:0],ID[7:0]) (MF[7:0],ID[7:0]...) JEDECID 9Fh Manufacturer MemoryType Capacity ReadSFDP Register 5Ah 00h 00h A7—A0 dummy (D7—D0,…) Read Security Registers(3) 48h A23—A16 A15—A8 A7—A0 dummy (D7—D0,…) Erase Security Registers(3) 44h A23—A16 A15—A8 A7—A0 Program Security Registers(3) 42h A23—A16 A15—A8 A7—A0 D7—D0,… ReadUnique ID 4Bh dummy dummy dummy dummy (ID63-ID0) Notes: 1.TheDevice IDwillrepeatcontinuouslyuntilCS# terminatesthecommand. 2. See Section 7.5.3, Legacy Device Identification Commands on page 56 for Device ID information. The 90h instruction is followed byanaddress.Address=0 selectsManufacturer IDasthefirstreturned dataasshown inthetable.Address=1 selectsDeviceIDas thefirstreturned datafollowed byManufacturer ID. 3.SecurityRegisterAddress: SecurityRegister 0:A23-16 =00h;A15-8= 00h;A7-0= byte address SecurityRegister 1:A23-16 =00h;A15-8= 10h;A7-0= byte address SecurityRegister 2:A23-16 =00h;A15-8= 20h;A7-0= byte address SecurityRegister 3:A23-16 =00h;A15-8= 30h;A7-0= byte address Table7.4(1) Manufacturer and DeviceIdentification(SPI and QPI Mode) OPCode Data1 Data2 Data3 ABh DeviceID= 17h - - 90h/92h/94h Manufacturer ID=5E Device ID=17h - 9Fh(SPI) ManufacturerID= 5E MemoryType=40h Capacity= 18h 9Fh(QPI) ManufacturerID= 5E MemoryType=60h Capacity= 18h Notes: (1)Please contactsalesfor moreinformation HM25Q128A

Table7.5Command Set (QPI Instructions(1), QPI Mode) CommandName BYTE 1 (Instruction) BYTE2 BYTE 3 BYTE4 BYTE5 BYTE 6 WriteEnable 06h WriteEnableforVolatile StatusRegister 50h WriteDisable 04h ReadStatusRegister-1 05h (S7-S0) (1) WriteStatusRegister-1 (3) 01h (S7-S0) (3) ReadStatusRegister-2 35h (S15-S8) (1) WriteStatusRegister-2 31h (S15-S8) ReadStatusRegister-3 15h/33h (S23-S16) (1) WriteStatusRegister-3 11h (S23-S16) GlobalBlockLock 7Eh GlobalBlockUnlock 98h ReadBlockLock 3Dh A23—A16 A15—A8 A7—A0 L7—L0 IndividualBlockLock 36h A23—A16 A15—A8 A7—A0 IndividualBlockUnlock 39h A23—A16 A15—A8 A7—A0 ChipErase C7h/60h Erase/ ProgramSuspend 75h Erase/ ProgramResume 7Ah DeepPower-down B9h SetRead Parameters C0h P7-P0 ReleasePower down /ID ABh Dummy Dummy Dummy (ID7-ID0) (1) Manufacturer/DeviceID 90h Dummy Dummy 00h (MF7-MF0) (ID7-ID0) JEDECID 9Fh (MF7-MF0) (ID15-ID8) (ID7-ID0) Exit QPIMode FFh EnableReset 66h ResetDevice 99h PageProgram 02h A23-A16 A15-A8 A7-A0 D7-D0 (4) D7-D0(2) SectorErase (4KB) 20h A23-A16 A15-A8 A7-A0 BlockErase(32KB) 52h A23-A16 A15-A8 A7-A0 BlockErase(64KB) D8h A23-A16 A15-A8 A7-A0 FastRead 0Bh A23-A16 A15-A8 A7-A0 Dummy (5) D7-D0 BurstRead with Wrap(6) 0Ch A23-A16 A15-A8 A7-A0 Dummy (5) D7-D0 FastRead QuadI/O EBh A23-A16 A15-A8 A7-A0 M7-M0 (5) D7-D0 Notes: 1.TheStatusRegister contentsand DeviceID willrepeat continuouslyuntilCS#terminatestheinstruction. 2.Atleastone byteofdatainput isrequired forPage Program,QuadPage ProgramandProgramSecurityRegisters,up to256 bytes of data input. If more than 256 bytes of data are sent to the device, the addressing will wrap to the beginning of the page and overwritepreviouslysentdata. 3.WriteStatusRegister-1 (01h) canalsobe usedtoprogram StatusRegister-1&2&3,seesection7.1.5. HM25Q128A

4.Quad SPIdatainput/outputformat: IO0= (D4,D0, …..) IO1= (D5,D1, …..) IO2= (D6,D2, …..) IO3= (D7,D3, …..) 5. The number of dummy clocks for QPI Fast Read, QPI Fast Read Quad I/O & QPI Burst Read with Wrap is controlled by read parameterP7– P4. 6.Thewrap around lengthforQPIBurstRead withWrap iscontrolledbyread parameter P3–P0. HM25Q128A

7.1Configuration andStatusCommands

7.1.1 Read StatusRegister (05h/35h/15h)

The Read Status Register commands allow the 8-bit Status Registers to be read. Thecommandis entered by driving CS# low and shifting the instruction code “05h” for Status Register-1, “35h”for Status Register-2, “15h” for Status Register-3into the DI pin on the rising edge of CLK. TheStatus Register bits are then shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shownin Figure 7.1.The Status Register bits areshown in Section 6.2, Status Registers. The Read Status Register-1 (05h) commandmaybe used at any time, even during aProgram, Erase, or WriteStatus Registers cycle.This allows the BUSYstatus bit to bechecked to determine when the operation is complete and if the device can accept another command. Figure 7.1a Read Status Register Instruction(SPI Mode) Figure7.1b Read Status Register Instruction(QPI Mode)

7.1.2 WriteEnable (06h)

The Write Enable instruction (Figure 7.2) sets the WriteEnable Latch (WEL) bit in the Status Register to a 1.The WELbit mustbe set prior to every PageProgram, Sector Erase, Block Erase, Chip Erase and Write Status Register instruction. The WriteEnable instruction is entered by driving CS# low,shifting the instruction code “06h” into the Data Input (DI) pin on the rising edge of CLK, and then driving CS# high. HM25Q128A

Figure7.2 WriteEnable Instruction(SPI or QPI Mode)

7.1.3 WriteEnable forVolatile StatusRegister (50h)

The non-volatile Status Register bits described in section 6.2 canalso be written to as volatile bits.This gives moreflexibility to change the system configuration and memoryprotection schemes quickly without waiting forthe typical non-volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits.Towrite the volatile values into theStatus Register bits, the WriteEnable forVolatile Status Register (50h) instruction must be issued prior toa WriteStatus Register (01h) instruction. Write Enable for Volatile Status Register instruction (Figure 7.3) will not set the WriteEnable Latch (WEL)bit, it is only valid for the WriteStatus Register instruction to change the volatile Status Register bit values. Figure 7.3 WriteEnablefor Volatile Status Register Instruction(SPI or QPI Mode)

7.1.4 WriteDisable (04h)

The Write Disable instruction (Figure 7.4) resets the Write EnableLatch (WEL) bit in the Status Register to a 0.The WriteDisable instruction is entered bydriving CS# low,shifting the instruction code “04h” into the DI pin and then driving CS# high. Note that the WELbit is automatically reset after Power-up and upon completion of the WriteStatus Register,Page Program, Sector Erase, Block Erase and Chip Erase instructions. Figure7.4 WriteDisable Instruction(SPI or QPI Mode)

7.1.5 WriteStatus Register (01h/31h/11h)

The Write Status Registers command allows the Status Registers to be written. Only non-volatile Status Register bits SRP0, SEC, TB, BP2, BP1, BP0 (SR1[7:2]) CMP, LB3, LB2, LB1, QE, SRP1 (SR2[6:0]), and HRSW, DRV1, DRV0, HFQ, WPS, LC[1:0] (SR3[7:4,2:0])can be written.All other Status Register bit locations are read-only and will not be affected by the Write Status Registers command. LB[3:0] are non-volatile OTP bits; once each is set to 1, it cannot be cleared to0. TheStatus Register bits are shown in Section 6.2, Status Registers.Any reserved bits should only be written to their default value. To write non-volatile Status Register bits, a standard Write Enable (06h) command must previously have HM25Q128A

been executed for the device to accept the Write Status Registers Command (Status Register bit WEL must equal 1). Oncewrite enabled, the commandis enteredby driving CS# low,sending theinstruction code“01h”, and then writing the Status Register data bytes as illustrated in Figure 7.5. To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) command must have been executed prior to the Write Status Registers command (Status Register bit WEL remains 0). However, SRP1 and LB3, LB2, LB1 cannot be changed because of the OTP protection for these bits. Upon power-off,thevolatileStatus Registerbit valueswill belost, andthenon-volatile Status Register bit values will be restored when power onagain. Tocomplete the Write Status Registers command, the CS# pin must be driven high after the eighth bit of a data value is clocked in (CS# must be driven high on an 8-bit boundary). If this is not done the Write Status Registers commandwill not be executed. The Write Status Register instruction allows the Status Register to bewritten.AWrite Enableinstruction must previously have been executed forthe device toaccept the Write Status Register Instruction (Status Register bit WELmust equal to 1). Once write enabled, the instruction is entered by driving CS# low,sending the instruction code “01h”, and then writingthe status register data byte as illustrated in Figure 7.5. Duringnon-volatile StatusRegister writeoperation (06hcombined with01h/31h), afterCS#isdrivenhigh, the self-timed Write Status Register cyclewill commencefora timeduration of tW (SeeAC Characteristics). While the WriteStatus Register cycle is in progress, theRead Status Register instruction may still be accessedto check the status of the BUSYbit.The BUSYbit is a 1during the WriteStatus Register cycle and a 0when thecycle is finished and ready to accept other instructions again.After the Write Status Register cycle has finished, the WriteEnable Latch (WEL) bit in theStatus Register will be cleared to 0. DuringvolatileStatusRegisterwriteoperation (50hcombinedwith01h/31h/11h),afterCS#isdrivenhigh, the Status Register bits will be refreshed to the new values within the time period of tSHSL2 (SeeAC Characteristics). BUSYbit will remain 0during the Status Register bit refresh period. If CS#is driven high after theeighth clock, theWriteStatus Register-1 (01h) instruction will only program the Status Register-1, the Status Register-2 will not be affected. gure7.5a WriteStatus Register Instruction(SPI Mode) Figure 7.5b WriteStatus Register Instruction(QPI Mode) 7.2Programand EraseCommands HM25Q128A

7.2.1 Page Program (PP) (02h)

The PageProgram instruction allows up to256 bytes of data tobe programmed at previously erased to all 1s (FFh) memory locations.AWrite Enable instruction must be executed beforethe device will accept the Page Program Instruction (Status Register bit WELmust equal 1).The instruction is initiated by driving the CS# pin low then shifting the instruction code“02h” followed by a 24-bit address (A23-A0) and at least one data byte, into the DI pin.The CS# pin mustbe held low for the entire length of the instruction while data is being sent tothe device.The Page Program instruction sequence is shown inFigure 7.6. Ifanentire256bytepageistobeprogrammed,thelast addressbyte(the8leastsignificantaddressbits) should be set to 0. If the last addressbyte is not zero, and the number of clocks exceeds theremaining page length, the addressing will wrap to the beginning of the page. Insomecases, less than 256 bytes (a partial page) canbe programmedwithout having any effect on other bytes within the samepage. Onecondition to performapartialpageprogramisthat thenumberofclockscannotexceedtheremainingpagelength.Ifmore than 256 bytes are sent to the device the addressing will wrap tothe beginning of the page and overwrite previously sent data. As with the write and eraseinstructions, the CS# pin must be driven high afterthe eighth bit of the last byte has been latched. If this is not done the Page Program instruction will not be executed.After CS# is driven high, the self-timed Page Program instruction will commencefor atimeduration of tpp (SeeAC Characteristics). While the Page Program cycle is in progress, the Read Status Register instruction may still be accessedfor checking the status of the BUSYbit.The BUSYbit is a1 during the PageProgram cycle and becomes a0when the cycle is finished and the device is ready toaccept other instructions again.After the Page Program cycle has finished theWrite Enable Latch (WEL) bit in the Status Register is cleared to 0.The Page Program instruction will not be executed if the addressed pageis protected bythe Block Protect (TB, SEC, BP2, BP1, and BP0) bits (seeStatus Register MemoryProtection table). Figure7.6a Page Program Instruction (SPI Mode) Figure 7.6b Page Program Instruction(QPI Mode)

7.2.2 Quad Input Page Program (32h)

The Quad Input Page Program instruction allows up to 256 byte of data tobe programmedat previously erased (FFh) memorylocations using four pins: IO0, IO1, IO2and IO3.TheQuad Input Page Program can improvedperformanceforPROM Programmerandapplicationsthat haveslow clockspeeds<5MHz. Systems with faster clock speed will not realize muchbenefit forthe Quad Input Page Program instruction since the inherent page program timeis much greater than the time it taketo clock-inthe data. TouseQuad Page Program the Quad Enable in Status Register-2 mustbe set (QE=1).AWriteEnable HM25Q128A

instruction must be executed before the device will accept the Quad Page Program instruction (Status Register-1, WEL=1).The instruction is initiated by driving the CS# pin low then shifting theinstruction code "32h" followedby a24-bit address (A23-0) and at least one data byte, into the IO pins.The CS# pin must be held low for entirelength of the instruction while data is being sent to the device.All other functions of Quad Page Program areidentical to standard Page Program.The Quad Page Program instructions sequence is shown in Figure 7.7. Figure7.7 QuadPage Program Instruction

7.2.3 SectorErase (SE) (20h)

TheSectorEraseinstructionsetsallmemorywithinaspecifiedsector(4K-bytes)totheerasedstateofall 1s (FFh).AWriteEnable instruction mustbe executed before the device will accept the Sector Erase Instruction (Status Register bit WELmust equal 1).The instruction is initiated by driving the CS# pin low and shifting theinstruction code “20h” followed a24-bit sector address(A23-A0). TheSector Eraseinstruction sequence is shown in Figure 7.8. The CS# pin must be driven high after the eighth bit of thelast byte has been latched. If this is not done the Sector Erase instruction will not be executed.After CS# is driven high, theself-timed Sector Erase instruction will commencefora timeduration of tSE (SeeAC Characteristics). While the Sector Erase cycle is inprogress,theReadStatusRegisterinstructionmaystillbeaccessedforcheckingthestatusoftheBUSYbit. TheBUSYbit is a1duringthe Sector Erasecycleandbecomesa0when thecycleis finished and thedevice is ready to accept other instructions again.After the Sector Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0.The Sector Erase instruction will not be executed if the addressed page is protected by the Block Protect (TB, SEC, BP2, BP1, and BP0) bits (see Status Register MemoryProtection table). Figure7.8a Sector EraseInstruction(SPI Mode) HM25Q128A

Figure 7.8b Sector Erase Instruction(QPI Mode)

7.2.4 Block Erase (BE) (D8h) and Half Block Erase (52h)

TheBlockEraseinstruction setsallmemorywithinaspecifiedblock(64K-bytes)orhalfblock(32K-bytes) to the erased state of all 1s (FFh).AWrite Enable instruction must be executed beforethe device will accept the Block Erase Instruction (Status Register bit WELmust equal 1). The instruction is initiated by driving the CS# pin low and shifting theinstruction code “D8h” or “52h” followed a24-bit block address (A23-A0).The Block Erase instruction sequenceis shown in Figure 7.9. The CS# pin must be driven high after the eighth bit of thelast byte has been latched. If this is not done the Block Erase instruction will not be executed.After CS# is driven high, the self-timed BlockErase instruction willcommenceforatimedurationoft BE (SeeACCharacteristics).WhiletheBlockErasecycleisin progress, the Read Status Register instruction maystill be accessedforchecking the status of the BUSYbit. The BUSYbit is a 1during the Block Erasecycle and becomesa 0when the cycleis finished and the device is ready to accept other instructions again.After the Block Erase cycle has finished theWrite Enable Latch (WEL) bit in the Status Register is cleared to 0.The Block Erase instruction will not beexecuted if the addressed page is protected by the Block Protect (TB, SEC, BP2, BP1, and BP0) bits (see Status Register MemoryProtection table). Figure 7.9a Block Erase Instruction(SPI Mode) Figure7.9b BlockErase Instruction(QPI Mode)

7.2.5 Chip Erase (CE) (C7h or60h)

The Chip Erase instruction sets all memory within the device tothe erased stateof all 1s (FFh).AWrite Enable instruction must beexecuted beforethe device will accept the Chip Erase Instruction (Status Register bit WELmust equal 1).Theinstruction is initiated by driving the CS# pin low and shifting the instruction code “C7h” or “60h”.The Chip Eraseinstruction sequence is shown in Figure 7.10. The CS# pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase instruction will not be executed.After CS# is driven high, the self-timed Chip Erase instruction will commence foratimeduration of tCE (SeeAC Characteristics). While theChipErase cycleis in progress, theRead Status Register instruction maystill be accessedto checkthe status of theBUSYbit.The BUSYbit is a1 duringthe Chip Erasecycle and becomesa 0when finished and the device is ready to accept other instructions again. AftertheChipErasecyclehasfinishedtheWriteEnableLatch(WEL)bit intheStatusRegisterisclearedto0. The Chip Erase instruction will not be executed if any pageis protected by the Block Protect (SEC,TB, BP2, BP1, and BP0) bits (seeStatus Register Memory Protection table). Figure 7.10 Chip Erase Instruction(SPI or QPI Mode)

7.2.6 Erase / Program Suspend (75h)

TheErase/Program SuspendcommandallowsthesystemtointerruptaSectororBlockEraseoperation, then read from or program data to any other sector.TheErase / Program Suspend command alsoallows the system tointerruptaPageProgramoperation andthenreadfromany otherpageoreraseanyothersectoror block.TheErase / Program Suspend command sequence is shown in Figure 7.11. The Write Status Registers command(01h, 31h, 11h), and Erase commands (20h, 52h, D8h, C7h, 60h, 44h) are not allowedduring Erase Suspend. EraseSuspend is valid only during the Sector or Block erase operation. If written during the Chip Erase operation, the Erase Suspend commandis ignored.The Write Status Registers command (01h, 31h), and Program commands(02h, 32h, 42h) are not allowed during Program Suspend. Program Suspend is valid during the Page Program or Quad Page Program operation. The Erase / Program Suspend command 75h will be accepted by the device only if the SUS bit in the Status Register equals to 0and the BUSYbit equals to1 while aSector or BlockErase or aPage Program operation is on-going. If the SUS bit equals to1 or the BUSYbit equals to0, the Suspend commandwill be ignored by the device. Program or Erase commandfor the sector that is being suspended will be ignored. Amaximum of timeof tSUS (Section8.5,AC Electrical Characteristics)is required tosuspend theeraseor program operation.The BUSYbit in the Status Register willbe cleared from 1to0 within tSUS and the SUS bit in the Status Register will be set from 0to 1immediately after Erase/Program Suspend. For a previously resumed Erase/Program operation, it is also required that the Suspend command75h is not issued earlier than a minimum of time of tSUS following the preceding Resumecommand7Ah. Unexpected power offduring the Erase / Program suspend state will reset the device and release the suspendstate.SUSbit intheStatusRegisterwillalsoresetto0.Thedatawithinthepage,sectororblockthat was being suspended maybecomecorrupted. It is recommended for the user to implement system design techniques to prevent accidental power interruption, provide non-volatile tracking of in process program or erase commands, and preserve data integrity by evaluating the non-volatile program or erasetracking information during each system power up in order to identifyand repair (re-erase and re-program) any improperly terminated program or erase operations. HM25Q128A

Figure7.11a Erase / Program Suspend Instruction(SPI Mode) Figure 7.11bErase / Program Suspend Instruction(QPI Mode)

7.2.7 Erase / Program Resume (7Ah)

The Erase / Program Resume command“7Ah” must be written to resumethe Sector or Block Erase operation or the Page Program operation after an Erase / Program Suspend. TheResume command“7Ah” willbeacceptedbythedeviceonlyiftheSUSbitintheStatusRegisterequalsto1andtheBUSYbitequalsto 0.After theResume commandis issued the SUS bit will be cleared from 1to 0 immediately,the BUSYbit will be set from 0 to 1within 200 ns and the Sector or Block will complete the erase operation or thepage will completetheprogramoperation.IftheSUSbitequalsto0ortheBUSYbitequalsto1,theResumecommand “7Ah” will be ignored by the device. TheErase / Program Resume commandsequence is shown in Figure 7.12. It is requiredthat asubsequent Erase / Program Suspend commandnot to be issued within aminimum of timeof “tSUS”following aResume command. Figure 7.12 Erase/Program Resume Instruction(SPI or QPI Mode) 7.3Read Commands

7.3.1 Read Data (03h)

The Read Data instruction allows one moredata bytes tobe sequentially read from the memory.The instruction is initiated by driving the CS# pin low and then shifting the instruction code “03h” followedby a HM25Q128A

24-bit address (A23-A0) intothe DI pin.The code and address bits arelatched on the rising edgeof the CLK pin.After the address is received, the data byteof the addressed memory location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first.The address is automatically incremented to the next higher address after each byte of data is shiftedout allowing for acontinuous stream of data.This means that the entire memorycan be accessedwith a single instruction as long as the clock continues.Theinstruction is completed by driving CS# high. The Read Data instruction sequence is shown in Figure 7.13. If a Read Data instruction is issued while an Erase, Program or Writecycle is inprocess (BUSY=1) the instruction is ignored and will not have any effects onthe current cycle.The Read Data instruction allows clock rates from D.C. to amaximum of fR (see Figure 7.13 Read Data Instruction

7.3.2 Fast Read (0Bh)

The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest possible frequency of FR (seeAC Electrical Characteristics).This is accomplished by adding eight “dummy” clocks after the 24-bit address as shown in Figure 7.14.Thedummyclocks allow the devices internal circuits additional timeforsetting up the initial address. During the dummyclocksthe data value on the DI pin is a “don’t care”. Figure7.14a Fast Read Instruction (SPI Mode) Fast Read (0Bh) in QPI Mode The Fast Read instruction is alsosupported inQPI mode. When QPI mode is enabled, the number of dummyclocks is configured by the“Set Read Parameters (C0h)” instruction to accommodate awiderange of applications with different needs foreither maximum Fast Read frequency or minimum data accesslatency. Depending on theRead Parameter Bits P[5:4] setting, the number of dummyclocks can be configured as either 2, 4, 6 or 8.The default number of dummyclocks upon power up or after a Reset instruction is 2. HM25Q128A

Figure 7.14b Fast Read Instruction (QPI Mode)

7.3.3 Fast Read Dual Output(3Bh)

TheFastReadDualOutput(3Bh)instructionissimilartothestandardFastRead(0Bh)instructionexcept that data is output on two pins, DO and DI, insteadof just DO.This allows data tobe transferred from the ZB25VQ128 at twice the rateof standard SPI devices.The Fast Read Dual Output instruction is ideal for quickly downloading codefrom FlashtoRAM upon power-up or for applications that cachecode-segments to RAM for execution. Similar to theFast Read instruction, the Fast Read Dual Output instruction canoperate at the highest possible frequency of FR (seeAC Electrical Characteristics).This is accomplished by adding eight “dummy” clocks after the 24-bit address as shown in Figure 7.15.Thedummyclocks allow the device's internal circuits additional timeforsetting up the initial address.The input data during the dummyclocks is “don’t care”. However,the DI pin should be high-impedance prior to the falling edge of the first data out clock. Figure7.15 Fast Read Dual Output Instruction Sequence Diagram

7.3.4 Fast Read Quad Output (6Bh)

The Fast Read Quad Output (6Bh) instruction is similar tothe Fast Dual Output (3Bh) instruction except that data is output on four pins, IO0, IO1, IO2and IO3.AQuad enable of status Register-2 must be executed before the device will accept the Fast Read Quad Output Instruction (Status Register bit QEmust equal 1). The Fast Read Quad Output Instruction allows data tobe transferred from HM25Q128A at four timesthe rate of standa rdSPI devices. The Fast Read Quad Output instruction canoperate at the highest possible frequency of FR (seeAC Electrical Characteristics).This is accomplished by adding "dummy" clocksafter the 24-bit address as shown in Figure 7.16. Theinput data during the dummyclocksis "don't care". However,the IO pins should be high-impedance prior to the falling edge of the first data out clock. HM25Q128A

Figure7.16 Fast Read Quad Output Instruction

7.3.5 Fast Read Dual I/O (BBh)

The Fast Read Dual I/O (BBh) instruction allows for improved random accesswhile maintaining two IO pins, IO0and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input theAddressbits (A23-0) two bits per dock.This reduced instruction overhead may allow for code execution (XIP) directly from the Dual SPI in someapplications. Fast Read Dual I/O with "Continuous Read Mode" The Fast Read Dual I/O instruction canfurther reduce instruction overhead through setting the "Continuous Read Mode" bits(M7-0) aftertheinputAddress bits(A23-0), as shownin Figure7.17.Theupper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction through the inclusion or exclusion of the first byteinstruction code. The lower nibblebits of the (M3-0) aredon't care ("X"). However, the IO pins shouldbe high-impedance prior tothe fallingedgeof the first data out clock.It is recommended to input FFFFhon IO0for the next instruction (16 clocks), toensure M4 = 1and return thedevice tonormal operation. Figure7.17 Fast Read Dual I/O Instruction (Initial commandor previous M5-4≠10) Note: 1.Leastsignificant4bitsofMode aredon’tcareand itisoptionalforthehosttodrive thesebits.The hostmayturnoffdriveduring these cyclestoincrease busturnaroundtimebetween Mode bitsfromhostandreturning datafromthememory Figure7.18Fast Read Dual I/O Instruction (Initial command or previous M5-4=10)

7.3.6 Fast Read Quad I/O (EBh)

The Fast Read Quad I/O (EBh) commandis similar to the Fast Read Dual I/O (BBh) commandexcept that addressanddatabitsareinput andoutputthroughfourpinsIO0, IO1,IO2and IO3andDummyclockare required prior to thedata output. TheQuad I/O dramatically reduces instruction overheadallowing faster random accessfor code execution (XIP) directly from the QuadSPI. TheQuad Enable bit (QE) of Status Register-2 must be set toenable the Fast Read Quad I/O Command. HM25Q128A

Fast Read Quad I/O with “Continuous Read Mode” The Fast Read Quad I/O command canfurther reduce instruction overhead through setting the “Continuous Read Mode”bits(M7-0) after theinputAddressbits(A23-0), as showninFigure7.19, Fast Read Quad I/O CommandSequence (Initial commandor previous M5-4≠10).The upper nibble of the (M7-4) controls the length of the next Fast Read Quad I/O command through the inclusion or exclusion of the first byte instruction code.The lower nibble bits of the(M3-0) aredon’t care(“X”). However,the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the“Continuous Read Mode”bits M5-4=(1,0), then thenext Fast ReadQuad I/Ocommand(afterCS# is raised and then lowered) does not requirethe EBh instruction code, as shown in Figure 7.20, Fast Read Quad I/O Command Sequence (Previous commandset M5-4 =10).This reduces the commandsequence by eight clocks and allows the Read address tobe immediately entered after CS# is asserted low.If the “Continuous Read Mode” bits M5-4 do not equal to (1, 0), the next command(after CS# is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. It is recommended to input FFhonIO0forthenext instruction(8clocks),toensureM4=1andreturnthedevicetonormaloperation. Figure7.19a Fast Read Quad I/O Instruction(Initial command or previous M5-4 ≠10) Figure7.20 Fast Read Quad I/O Instruction(Previous commandset M5-4 = 10) Fast Read Quad I/O with “8/16/32/64-Byte WrapAround” TheFastReadQuadI/Ocommandcanalsobeusedtoaccessaspecificportionwithinapagebyissuing a “Set Burst with Wrap” command prior to EBh. The “Set Burst with Wrap” command can either enable or disablethe “WrapAround”feature forthefollowingEBhcommands.When“WrapAround”is enabled,thedata being accessed can be limited to 8/16/32/64-byte section of data. The output data starts at the initial address specified in the command, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around tothe beginning boundaryautomatically until CS# is pulled high to terminate the command. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-bytes) of data without issuing multiple read commands. The “Set Burst with Wrap” command allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-5 is used to specify the length of the wrap around section within apage. See Section 7.3.9, Set Burst with Wrap(77h). HM25Q128A

Fast Read Quad I/O (EBh) in QPI Mode The Fast Read Quad I/O instruction is also supported in QPI mode, as shown in Figure 7.19b When QPI mode is enabled, the number of dummy clocks is configured by the “Set Read Parameters (C0h)” instruction toaccommodateawiderange of applicationswith different needs foreither maximumFastRead frequencyor minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either 2, 4, 6 or 8. The default number of dummyclocks upon power up or after a Reset instruction is 2. In QPI mode, the “Continuous Read Mode” bits M7-0 are also considered as dummy clocks. In the default setting, the data output will follow the Continuous Read Mode bits immediately. “Continuous Read Mode” feature is also available in QPI mode for Fast Read Quad I/O instruction. Please refer tothe description on previous pages. “Wrap Around” feature is not available in QPI mode for Fast Read Quad I/O instruction. To perform a read operation with fixed data length wrap around in QPI mode, a dedicated “Burst Read with Wrap” (0Ch) instruction must be used. Please refer to 7.5.13 for details. Figure 7.19bFast Read Quad I/O Instruction(Initial commandor previous M5-4 ≠10,QPI Mode)

7.3.7 Word Read Quad I/O (E7h)

The WordRead Quad I/O (E7h) instruction is similar to the Fast Quad I/O (EBh) instruction except that the lowestAddress bit (A0) mustequal to 0 and only two Dummyclocksare required prior tothe data output. The Quad I/O dramatically reduces instruction overhead allowing faster random accessfor code execution (XIP) directly from the Quad SPI.The Quad Enable bit (QE) of Status Register-2must be set to enable the WordRead Quad I/O instruction. Word Read Quad I/O with "Continuous Read Mode" The WordRead Quad I/O instruction canfurther reduceinstruction overhead through settingthe "Continuous Read Mode" bits(M7-0) aftertheinputAddress bits(A23-0), as shownin Figure7.21.Theupper nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the inclusion or exclusion of the first byteinstruction code. The lower nibblebits of the (M3-0) aredon't care ("X"). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the"Continuous Read Mode"bits M5-4=(1,0), then thenext Fast Read QuadI/O instruction (afterCS# is raised and then lowered) does not require the E7h instruction code, as shown in Figure 7.22. This reduces the instruction sequence by eight clocks and allows the read address to be immediately entered after CS# is asserted low.The"Continuous Read Mode Reset” instruction is also able to reset M7-0 before issuing normal instructions. HM25Q128A

Figure 7.21 WordRead Quad I/O Instruction(Initial commandor previous M5-4 ≠10) Figure 7.22 WordRead Quad I/O Instruction(Initial command or previous M5-4 =10) Word Read Quad I/O with “8/16/32/64-Byte WrapAround” in Standard SPI mode The WordRead Quad I/O instruction canalso beused to access aspecific portion within a page by issuing a“Set Burst with Wrap” (77h) command prior toE7h.The “Set Burst with Wrap”(77h) commandcan either enable or disable the “WrapAround” feature forthe following E7h commands. When “WrapAround” is enabled, the data being accessedcanbe limited to either an 8, 16, 32 or 64-byte section of a 256-byte page. Theoutput datastartsattheinitialaddressspecifiedintheinstruction, onceitreachestheendingboundaryof the 8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until CS# is pulled high toterminate the command. The Burst with Wrapfeature allows applications that use cacheto quickly fetcha critical address and then fill thecache afterwards within a fixedlength (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst with Wrap” instruction allows three “WrapBits”, W6-4 tobe set.The W4bit is used to enable or disable the “WrapAround”operation while W6-5 areused to specifythe length of the wrap around section within apage. See 7.3.9 for detail descriptions.

7.3.8 Octal Word Read Quad I/O (E3h)

The OctalWordRead QuadI/O (E3h) instruction is similar tothe Fast Read Quad I/O (EBh) instruction except that the lower fourAddressbits (A0,A1 ,A2,A3) must equal 0.As a result, the dummyclocks arenot required, whichfurther reduces the instruction overhead allowing even fasterrandom access for code execution (XIP).The QuadEnable bit (QE) of Status Register-2 must beset to enable the Octal WordRead Quad I/O Instruction. Octal Word Read Quad I/O with“ContinuousRead Mode” The OctalWordRead QuadI/O instruction canfurther reduce instruction overhead through setting the “Continuous Read Mode” bits (M7-0) after theinputAddress bits (A23-0), as shown inFigure 7.23.The upper nibbleofthe(M7-4)controlsthelengthofthenextOctalWordReadQuadI/Oinstructionthroughtheinclusion or exclusionof thefirstbyte instruction code.Thelowernibblebitsof the(M3-0)aredon’tcare(“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits M5-4 =(1,0), then the next Fast Read Quad I/O instruction (after CS# is HM25Q128A

raisedandthenlowered)doesnotrequiretheE3hinstruction code,asshowninFigure7.24.Thisreducesthe instruction sequence by eight clocks and allows the Read addressto be immediately entered afterCS# is asserted low.If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (afterCS# is raised and then lowered) requires the first byte instruction code, thus returning tonormal operation. It is recommended toinputFFhonIO0forthenextinstruction(8clocks),toensureM4=1andreturnthedeviceto normal operation. Figure7.23 OctalWordRead Quad I/O Instruction(Initial commandor previous M5-4 ≠10) Figure 7.24 OctalWordRead QuadI/O Instruction(Initial command or previous M5-4 =10)

7.3.9 Set Burst withWrap (77h)

The Set Burst with Wrap (77h) command is used in conjunction with “Fast Read Quad I/O” commands to access a fixed length and alignment of 8/16/32/64-bytes of data. Certain applications can benefit from this feature and improve the overall system code execution performance. This command loads the W4,W5,W6 bits. Similar to aQuad I/O command, the Set Burst with Wrapcommandis initiated by driving the CS# pin low and then shifting the instruction code “77h” followed by 24-dummy bits and 8 “Wrap Bits”, W7-0. The command sequence is shown in Figure 7.25, Set Burst with Wrap Command Sequence. Wrap bit W7and the lower nibble W3-0are not used. W6,W5 W4=0 W4=1(DEFAULT) WrapAround WrapLength WrapAround WrapLength 0,0 Yes 8-byte No N/A 0,1 Yes 16-byte No N/A 1,0 Yes 32-byte No N/A 1,1 Yes 64-byte No N/A OnceW6-4is set by a Set Burst with Wrapcommand, all thefollowing “Fast Read Quad I/O” commands will use theW6-4 setting toaccess the 8/16/32/64-byte section of data. Note, Status Register-2 QE bit (SR2[1]) mustbe setto 1inorder tousetheFast Read Quad I/Oand Set Burst with Wrapcommands.Toexit the “WrapAround” function and return tonormal read operation, another Set Burst with Wrapcommand should be issued to set W4= 1.The default value of W4upon power on is 1. InQPImode,the“BurstReadwithWrap(0Ch)”instruction shouldbeusedtoperformtheReadoperation HM25Q128A

with“WrapAround”feature.TheWrapLengthsetbyW6-5inStandardSPImodeisstillvalidinQPImodeand Figure7.25 Set Burst with WrapInstruction 7.4ResetCommands Software controlled Reset commands restore thedevice to its initial power up state, by reloading volatile registers from non-volatile default values. If a software reset is initiated during aErase, Program or Writing Register operation the data in that Sector,Page or Register is not stable, the operation that was interrupted needs to be initiated again.Oncethe Reset instruction is accepted, any on-going internal operations will be terminated and the device will return to its default power-on state and lose all the current volatile settings, suchas VolatileStatusRegister bits, WriteEnableLatch(WEL) status,Program/Erase Suspendstatus, Read parameter setting (P7-P0), Continuous Read Mode bit setting (M7-M0) and Wrap Bit setting (W6-W4). When the device is in Deep Power-Down mode, thesoftware reset commandis ignored and has no effect.Toreset the device send the Release Power down command (ABh) and after timeduration of tRES1 the device will resumenormal operation and the software reset command will be accepted. A software reset is initiated by the Software Reset Enable command (66h) followed by Software Reset command (99h) and then executed when CS# is brought high after tRCH time at the end of the Software Reset instruction and requires tRST time before executing the next Instruction after the Software Reset. See Figure 8.7, Software Reset Input Timing. Note that CS# must be brought high after tRCH time, or the Software Reset will not be executed. Figure 7.26Software Reset Instruction(SPI and QPI Mode)

7.4.1 Software Reset Enable (66h)

The Reset Enable (66h) commandis required immediately beforea software reset command(99h) such that asoftware reset is asequenceof the two commands.Any commandother than Reset (99h) following the Reset Enable (66h) command, will clear the reset enable condition and prevent alater Reset (99h) command from being recognized. HM25Q128A

7.4.2 Software Reset (99h)

The Reset (99h) command immediately following a Reset Enable (66h) command, initiates the software resetprocess.AnycommandotherthanReset(99h) followingtheResetEnable(66h) command,willclear the reset enable condition and prevent a later Reset (99h) command from being recognized. 7.5IDand SecurityCommands

7.5.1 Deep Power-down(DP) (B9h)

Although the standby current during normal operation is relatively low,standby current can be further reduced with the Power-down instruction. The lower power consumption makes the Power- down instruction especially useful for batterypowered applications (See ICC1 and ICC2 inAC Characteristics).Theinstruction is initiated by driving the CS# pin low and shifting the instruction code “B9h” as shown in Figure 7.27. The CS# pin must be driven high after the eighth bit has been latched. If this is not done, the Power- down instruction will not be executed.After CS# isdriven high, the power-downstatewill enter withinthe time duration of tDP (SeeAC Characteristics). While in the power-down stateonly the Release from Power-down / Device ID instruction, which restores the device to normal operation, will berecognized.All other instructions are ignored. This includes the Read Status Register instruction, which is always available during normal operation. Ignoring all but one instruction makes the Power Down state auseful condition for securing maximum write protection.The device always powers-upin the normal operation with the standby current of ICC1. Figure 7.27 Deep Power-down Instruction(SPI and QPI Mode)

7.5.2 Release Power-down/ Device ID (ABh)

The Release from Power-down / Device ID instruction is a multi-purpose instruction. It canbe used to releasethedevicefromthepower-downstate,obtainthedeviceselectronicidentification(ID)numberorboth. Torelease thedevice from thepower-down state, the instruction is issued by driving the CS# pin low, shifting theinstruction code “ABh” and driving CS# high as shownin Figure 7.28.After the timeduration of tRES1 (SeeACCharacteristics)thedevicewillresumenormaloperationandotherinstructionswillbeaccepted. The CS# pin mustremain high during the tRES1 timeduration. When used only toobtain the Device ID during the non-power-down state, the instruction is initiated by drivingtheCS#pinlowandshiftingtheinstructioncode“ABh”followedby3-dummybytes.TheDeviceIDbits willthen beshiftedout onthe fallingedgeof CLKwith mostsignificant bit (MSB)firstasshowninFigure7.29. The Device ID value for the HM25Q128A is liste d in Manufacturer and Device Identification table. TheDevice ID canbe read continuously.The instruction is completed by driving CS# high. When used torelease the device from the power-down stateand obtain the Device ID, theinstruction is the sameas previouslydescribed, and shown in Figure 7.29, except that after CS# is driven high it must remain high for a timeduration of tRES2 (SeeAC Characteristics).After this time duration the device will resumenormal operation andother instructions will beaccepted. If theReleasefrom Power-down/ DeviceID instruction is issuedwithin Erase, Program or Writecycle (when BUSYequals 1), the instruction is ignored and will not have any effects on the current cycle. HM25Q128A

Figure 7.28 Release Power-down Instruction(SPI and QPI Mode) Figure 7.29aRelease Power-down / Device ID(SPI Mode) Figure7.29b Release Power-down / DeviceID(QPI Mode)

7.5.3 Read Manufacturer / Device ID (90h)

The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. TheReadManufacturer/Device ID instruction isverysimilar totheReleasefrom Power-down/ DeviceID instruction. The instruction is initiated by driving the CS# pin low and shifting the instruction code “90h” followed by a 24-bit address (A23-A0) of 000000h.After which, the Manufacturer ID and the Device ID are shiftedout onthefallingedgeof CLKwithmostsignificant bit (MSB) firstas showninFigure7.30. If the24-bit address is initially set to000001h the Device ID will be read firstand then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously,alternating from one to the other.The command is completed by driving CS# high. HM25Q128A

Figure7.30a Read Manufacturer/Device ID(SPI Mode) Figure 7.30b Read Manufacturer/Device ID(QPI Mode)

7.5.4 Read Identification (RDID) (9Fh)

For compatibility reasons, the HM25Q128A provi des several instructions to electronically determine the identi ty of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI compatible serial memories that was adopted in 2003. The instruction is initiated by driving the CS# pin low and shifting the instruction code “9Fh”.The JEDEC assignedManufacturerIDbyteandtwoDeviceIDbytes,MemoryType(ID15-ID8)andCapacity(ID7-ID0)are then shifted out on the falling edge of CLK with mostsignificant bit (MSB) first as shown in Figure 7.31. For memorytype and capacity values, refer toManufacturer and Device Identification table. Figure 7.31a Read JEDEC ID(SPI Mode) Figure7.31b Read JEDEC ID(QPI Mode)

7.5.5 Read SFDPRegister (5Ah)

The Read SFDPcommandis initiated by driving theCS# pin low and shifting the instruction code “5Ah” followed by a 24-bit address (A23-A0) into the DI pin. Eight “dummy” clocks arealso required before the SFDPregister contents are shiftedout onthe fallingedge of the40th CLK with mostsignificant bit (MSB) first as shown in Figure 7.32. HM25Q128A

Note:A23-A8= 0;A7-A0are usedtodefinethestarting byteaddressforthe256-byte SFDPRegister. Figure7.32 Read SFDPRegister Instruction

7.5.6 Erase Security Registers (44h)

The HM25Q128A offer sthree 256-byte Security Registers which canbe erased and programmed indi vidually.These registers may beused by system manufacturersto storesecurity and other important information separately from the main memoryarray. The Erase Security Register commandis similar to the Sector Erase command.AWrite Enable commandmust be executed before the device will accept the Erase Security Register Command(Status Register bit WELmust equal to 1).The command is initiated bydriving the CS# pin low and shifting the instruction code “44h” followed by a24-bit address(A23-A0) to eraseone of the security registers. Address A23-16 A15-8 A7-0 SecurityRegister-1 00h 10 h xxh SecurityRegister-2 00h 20 h xxh SecurityRegister-3 00h 30h xxh Note: 1.Addressesoutsidetheranges inthe tablehave undefinedresults. The Erase Security Register command sequence is shown in Figure 7.33. The CS# pin must be driven highaftertheeighthbit of thelast bytehasbeenlatched. Ifthisisnot donethecommandwillnot beexecuted. AfterCS# isdrivenhigh, theself-timedEraseSecurityRegister operation willcommenceforatimedurationof tSE (see Section 8.5,AC Electrical Characteristics). While the Erase Security Register cycle is in progress, the Read Status Register command may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other commands again.After the Erase Security Register cycle has finished the Write Enable Latch (WEL) bit intheStatusRegisteriscleared to0.TheSecurityRegister LockBits(LB[3:1])intheStatus Register-2canbe used to OTP protect the security registers. Once a lock bit is set to 1, the corresponding security register will be permanently locked, and an Erase Security Register commandto that register will be ignored. Figure7.33 Erase Security Registers Instruction

7.5.7 Program Security Registers (42h)

The Program Security Register command is similar to the Page Program command. It allows from one byte to 256 bytes of security register data to be programmed at previously erased (FFh) memory locations.A Write Enable command must be executed before the device will accept the Program Security Register Command (Status Register bit WEL= 1).The commandis initiated by drivingthe CS# pin low then shifting the instruction code “42h” followed by a 24-bit address (A23-A0) and at least one data byte, into the DI pin. The CS# pin must be held low for the entire length of the commandwhile data is being sent to thedevice. HM25Q128A

Address A23-16 A15 -8 A7-0 SecurityRegister-1 00h 10h ByteAddress SecurityRegister-2 00h 20h ByteAddress SecurityRegister-3 00h 30h ByteAddress Note: 1.Addressesoutsidetheranges inthe tablehave undefinedresults. The Program Security Register command sequence is shown in Figure 7.34. The Security Register Lock Bits (LB3:1) in the Status Register-2 can be used to OTP protect the security registers. Once a lock bit is set to 1, the corresponding security register will be permanently locked, and a Program Security Register commandto that register will be ignored. Figure7.34 Program Security Registers Instruction

7.5.8 Read Security Registers (48h)

The Read Security Register commandis similar to the Fast Read commandand allows one or moredata bytes to be sequentially read from one of the three security registers. The command is initiated by driving the CS# pin low and then shifting the instruction code “48h” followed by a 24-bit address (A23-A0) and eight “dummy” clocksinto theDI pin.Thecode andaddressbits arelatchedon therising edgeof the CLK pin.After the address is received, and following the eight dummy cycles, the data byte of the addressed memory location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. Locations with address bits A23-A16 not equal to zero, have undefined data. The byte address is automatically incremented to the next byte address after each byte of data is shifted out. Once the byte address reaches the last byte of the register (FFh), it will reset to the first byte of the register (00h) and continue to increase. The command is completed by driving CS# high. The Read Security Register command sequence is shown in Figure 7.35. If a Read Security Register command is issued while an Erase, Program, or Write cycle is in process (BUSY=1), the command is ignored and will not have any effects on the current cycle.TheReadSecurityRegister commandallows clockratesfrom DC toamaximumof F R (seeSection8.5, Address A23-16 A15-8 A7-0 SecurityRegister-1 00h 10h ByteAddress SecurityRegister-2 00h 20h ByteAddress SecurityRegister-3 00h 30h ByteAddress Note: 1.Addressesoutside therangesin thetablehave undefinedresults. Figure7.35 Read Security Registers Instruction

7.5.9 Individual Block/SectorLock (36h)

The Individual Block/Sector Lock provides an alternative way to protect the memory array from adverse Erase/Program. In order to use the Individual Block/Sector Locks, the WPS bit in Status Register-3 must be setto1.IfWPS=0, thewriteprotectionwillbedeterminedbythecombinationofCMP,SEC,TB,BP[2:0]bitsin HM25Q128A

the Status Registers. The Individual Block/Sector Lock bits are volatile bits. The default values after device power up o r after a Reset are1, sothe entire memoryarray is being protected. To lock a specific block or sector as illustrated in Figure 6.2, an Individual Block/Sector Lock command must be issued by driving CS# low,shifting the instruction code “36h” into the Data Input (DI) pin on the rising edge of CLK, followed by a 24-bit address and then driving CS# high. A Write Enable instruction must be executed before the device will accept the Individual Block/Sector Lock Instruction (Status Register bit WEL= 1). Figure 7.36a Individual Block/Sector Lock Instruction(SPI Mode) Figure7.36b Individual Block/Sector Lock Instruction(QPI Mode)

7.5.10 Individual Block/Sector Unlock (39h)

The Individual Block/Sector Lock provides an alternative way to protect the memoryarray from adverse Erase/Program. In order to use theIndividual Block/Sector Locks, theWPSbit in Status Register-3 mustbe setto1.IfWPS=0,thewriteprotectionwillbedeterminedbythecombinationofCMP,SEC,TB,BP[2:0]bitsin the Status Registers.The Individual Block/Sector Lock bits are volatile bits.The default values after device power up or after a Reset are1, sothe entire memoryarray is being protected. Tounlock a specific block or sector as illustrated in Figure 6.2, an Individual Block/Sector Unlock commandmustbeissuedbydrivingCS#low,shiftingtheinstructioncode“39h”intotheDataInput(DI)pinon the rising edge of CLK, followed by a 24-bit address and then driving CS#high.AWrite Enableinstruction must be executed beforethe device will accept the Individual Block/Sector Unlock Instruction(Status Register bit WEL= 1). Figure 7.37aIndividual Block/Sector Unlock Instruction(SPI Mode) HM25Q128A

Figure7.37b Individual Block/Sector Unlock Instruction(QPI Mode) 7.5.11Read Block/Sector Lock (3Dh) The Individual Block/Sector Lock provides an alternative way to protect the memoryarray from adverse Erase/Program. In order to use theIndividual Block/Sector Locks, theWPSbit in Status Register-3 mustbe setto1.IfWPS=0,thewriteprotectionwillbedeterminedbythecombinationofCMP,SEC,TB,BP[2:0]bitsin the Status Registers.The Individual Block/Sector Lock bits are volatile bits.The default values after device power up or after a Reset are1, sothe entire memoryarray is being protected. Toreadoutthelock bit valueofaspecificblockorsectorasillustrated inFigure6.2,aReadBlock/Sector Lock commandmust be issued by driving CS#low,shifting the instruction code “3Dh”into the Data Input (DI) pin ontherisingedgeof CLK, followedby a24-bit address.TheBlock/SectorLock bit value will beshiftedout on the DO pin at the falling edge of CLK with most significant bit (MSB) firstas shown in Figure7.38. If the least significant bit (LSB) is 1, the corresponding block/sector is locked; if LSB=0, the corresponding block/sector is unlocked, Erase/Program operation can be performed. Figure7.38a Read BlockLock Instruction(SPI Mode) Figure 7.38bRead Block Lock Instruction(QPI Mode)

7.5.12 Global Block/Sector Lock (7Eh)

All Block/Sector Lock bitscan be set to 1by theGlobal Block/Sector Lock instruction.The command mustbeissued bydrivingCS#low,shifting theinstruction code“7Eh”intotheData Input(DI) pinon therising edge of CLK, and then driving CS#high.AWrite Enableinstruction must be executed before the device will accept the Global Block/Sector Lock Instruction (Status Register bit WEL=1). HM25Q128A

Figure 7.39 Global Block Lock Instruction(SPI or QPI Mode)

7.5.13 Global Block/Sector Unlock (98h)

All Block/Sector Lock bitscan be set to 0by theGlobal Block/Sector Unlock instruction. The command must beissued by driving CS# low,shifting the instruction code“98h”into the DataInput (DI)pin onthe rising edge of CLK, and then driving CS#high.AWrite Enableinstruction must be executed before the device will accept the Global Block/Sector Unlock Instruction (Status Register bit WEL= 1). Figure 7.40 Global Block Lock Instruction(SPI or QPI Mode)

7.5.14 Read Manufacturer / Device ID Dual I/O (92h)

The Read Manufacturer / Device ID Dual I/O instruction is an alternative to the Read Manufacturer / DeviceIDinstructionthat providesboththeJEDEC assignedmanufacturerIDandthespecificdeviceIDat2x speed. The Read Manufacturer / Device ID Dual I/O instruction is similar to theFast Read Dual I/O instruction. The instruction is initiated by drivingthe CS# pin low and shifting the instruction code“92h” followed by a 24-bit address (A23-A0) of 000000h, but with the capability to input theAddress bits two bits per clock.After which, the Manufacturer ID and the Device ID areshifted out 2bits per clock on the falling edge of CLK with most significant bits (MSB) first as shown inFigure 7.41. TheDevice ID values for the ZB25VQ128 are listed in Manufacturer and Device Identification table. The Manufacturer and Device IDs canbe read continuously, alternating from one tothe other.The instruction is completed by driving CS#high. HM25Q128A

Figure 7.41 Read Manufacturer/Device ID Dual I/O Instruction Note: 1.The "ContinuousRead Mode" bitsM7-0 mustbe settoFxh tobecompatiblewithFastRead Dual I/Oinstruction .

7.5.15 Read Manufacturer / Device ID Quad I/O (94h)

The Read Manufacturer / Device ID Quad I/O instruction is an alternative to Read Manufacturer / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID at 4 x speeds. The Read Manufacturer / Device ID Quad I/O instruction is similar to the Fast Read QuadI/O instruction. The instruction is initiated by drivingthe CS# pin low and shifting the instruction code"94h" followed by a 24-bitaddress(A23-A0)of000000h,8-bitContinuousReadModeBitsandthenfourclockdummycycles,with the capability to input theAddress bits four bits per clock.After that, theManufacturer ID and the DeviceID are shifted out four bits per clock onthe falling edge of CLK with most significant bit (MSB) firstas shown in Figure 7.42. TheDevice ID values for HM25Q128A are listed in Manufacturer and Device Identification table. The M anufacturer and Device IDs can be read continuously,alternating from one to the other.The instruction is completed by driving CS# high. Figure7.42 Read Manufacturer/Device ID Quad I/O Instruction Note: 1. The "Continuous Read Mode" bits M7-0 mustbe set to Fxhto be compatible with Fast Read Quad I/O instruction. 7.5.16 Read Unique ID Number (4Bh) The Read Unique ID Number instruction accesses afactory-set read-only 64-bit number whichis unique to each HM25Q128A dev ice. The ID number canbe usedin conjunction with user software methods to help prev ent copying or cloning of asystem.The Read Unique ID instruction is initiated by drivingthe CS# pin low and shifting the instruction code"4Bh" followed by four bytes dummyclocks.After that, the 64-bit ID is shifted out on the falling edgeof CLK as shown in Figure 7.43. Figure7.43 Read unique ID Number Instruction

7.5.17 Set Read Parameters (C0h)

InQPI mode, toaccommodate awide range of applications with different needs foreither maximum read frequencyorminimumdataaccesslatency,“SetReadParameters(C0h)”instructioncanbeusedtoconfigure HM25Q128A

the number of dummyclocks for “Fast Read (0Bh)”, “Fast Read Quad I/O (EBh)” &“Burst Read with Wrap (0Ch)” in structions, and toconfigure the number of bytes of “WrapLength” for the “Burst Read with Wrap (0Ch)” instruction. In Standard SPI mode, the “Set Read Parameters (C0h)” instruction is not accepted. The dummy clocks forvarious Fast Readinstructions in Standard/Dual/Quad SPImode areindependentlycontrolled bySR3[3:0], see details in Table 6.5. The “Wrap Length” is set by W6-5 bit in the “Set Burst with Wrap (77h)” instruction. This setting will remain unchanged when the device is switched between Standard SPI mode and QPI mode. The default “WrapLength” after a power up or aReset instruction is 8 bytes, the default number of dummyclocksis 2.The number of dummyclocks is only programmable for “Fast Read (0Bh)”, “Fast Read Quad I/O (EBh)”& “Burst Read with Wrap(0Ch)”instructions in the QPI mode. Whenever the device is switched from SPI mode toQPI mode, the number of dummyclocks should beset again, prior toany 0Bh, EBh or 0Ch instructions. P5-P4 DUMMY CLOCKS MAXIMUM READ FREQ. MAXIMUMREAD FREQ.(A[1:0]=0,0) 00 2 50MHz 50MHz 01 4 80MHz 104MHz 10 6 104MHz 104MHz 11 8 104MHz 104MHz P1-P0 WRAP LENGTH 00 8-byte 01 16-byte 10 32-b yte 11 64-byte Figure7.44 Set Read Parameters Instruction (QPI Mode only)

7.5.18 Burst Read with Wrap (0Ch)

The “Burst Read with Wrap(0Ch)” instruction provides an alternative way toperform theread operation with “WrapAround” in QPI mode.The instruction is similar to the “Fast Read (0Bh)” instruction in QPI mode, except the addressing of the read operation will “WrapAround”to the beginning boundary of the “Wrap Length” once the ending boundary is reached.The “Wrap Length”and the number of dummyclocks canbe configured by the “Set Read Parameters(C0h)” instruction. Figure 7.45 Burst Read with WrapInstruction (QPI Mode only) HM25Q128A

7.5.19 Enter QPI Mode(38h)

The HM25Q128A upp ort both Standard/Dual/Quad Serial Peripheral Interface(SPI) and Quad Peri pheral Interface (QPI). However,SPI modeand QPI modecannot beused at the sametime.“Enter QPI (38h)” instruction is the only way to switch the device from SPI mode toQPI mode. Upon power-up, the default state of the device uponis Standard/Dual/Quad SPI mode.This provides full backward compatibility with earlier generations of ZBITserial flash memories. See Instruction SetTable 7.1-7.4 forall supported SPI commands. Inorder toswitch thedevice toQPI mode, theQuad Enable (QE)bit in Status Register-2 must be set to 1first, and an “Enter QPI (38h)” instruction must be issued. If the Quad Enable (QE) bit is 0, the “Enter QPI (38h)” instruction will be ignored and the device will remain in SPI mode. See Instruction SetTable7.5 for all thecommandssupportedinQPI mode. Whenthe deviceis switchedfrom SPI modeto QPI mode, the existing WriteEnable and Program/Erase Suspend status, and the WrapLength setting will remain unchanged. Figure7.46 Enter QPI Instruction (SPI Mode only)

7.5.20 Exit QPI Mode(FFh)

In order to exit the QPI mode and return to the Standard/Dual/Quad SPI mode, an “Exit QPI (FFh)” instruction must be issued. When the device is switched from QPI mode toSPI mode, the existing Write Enable Latch (WEL) and Program/Erase Suspend status, and the Wrap Lengthsetting will remain unchanged. Figure 7.47 Exit QPI Instruction (QPI Mode only) HM25Q128A

1. ELECTRICALCHARACTERISTIC Figure 8.1 Power-upTiming Table8.1 Power-upTiming PARAMETER SYMBOL TYPE UNITMIN MAX Vcc(minimumoperation voltage) Vcc(min) 2.3 - V Vcc(cutoffwhere re-initialization isneeded) Vcc(cutoff) 2.1 - V Vcc(lowvoltagefor initializationto occur) Vcc(low) 1.0 - V Vcc(min) toCS# Low tVSL(1) 10 - μs TimeDelayBeforeWriteInstruction tPUW(1) 1 10 ms Vcc(low) time tPD 10 - μs WriteInhibitThresholdVoltage VWI(1) 1 2 V Notes: (1)Theparametersare characterizedonly. Figure8.2Power-Down and Voltage Drop HM25Q128A

8.1.AbsoluteMaximumRatings Stresses ab ove thevalues mentioned as following may cause permanent damageto the device. These values are fora stressrating only and do not imply that the deviceshould be operated at conditions up to or above these values. Table 8.2(1) Absolute Maximum Rating PARAMETERS(2) SYMBOL CONDITIONS RANGE UNIT SupplyVoltage VCC -0.6to+4.0 V Voltage appliedon anypin VIO Relativeto Ground -0.6toV CC+0.4 V TransientVoltage onanyPin VIOT <20ns TransientRelativeto Ground -2.0toV CC+2.0 V StorageTemperature TSTG -65to +150 ℃ LeadTemperature TLEAD SeeNote(3) ℃ ElectrostaticDischargeVoltage VESD Human BodyModel(4) -2000to +2000 V Notes: (1)Specificationfor HM25Q128A isp reliminary.Seepreliminarydesignationattheend ofthisdocument. (2)T hisdevicehas beendesignedand testedfor thespecified operationranges.Properoperation outsidetheselevelsisnot guaranteed.Exposuretoabsolutemaximumratingsmayaffectdevicereliability.Exposure beyondabsolutemaximumratings maycausepermanentdamage. (3)Compatible to JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assemblyand the European directive on restrictionsonhazardous substances(RoHS) 2002/95/EU. (4)JEDECStd.JESD22-A114A(C1=100 pF,R1=1500 ohms,R2=500 ohms). 8.2. Recommended Operating Ranges Table8.3 Recommended OperatingRanges PARAMETER SYMBOL CONDITIONS SPEC UNIT MIN MAX SupplyVoltage VCC(1) FR=104MHz,fR=80MHz 2.7 3.6 V FR=80MHz,fR=50MHz 2.3 2.7 V AmbientTemperature, Operating TA Industrial -40 +85 ℃ Notes: (1)RecommendedOperating Rangesdefinethoselimitsbetween which thefunctionalityofthe deviceisguaranteed. HM25Q128A

8.3. DCCharacteristics Table8.4 D C Characteristics SYMBOL PARAMETER CONDITIONS SPEC UNITMIN TYP MAX CIN(1) InputCapacitance VIN=0V (2) 6 pF COUT(1) OutputCapacitance VOUT=0V (2) 8 pF ILI InputLeakage ±2 uA ILO I/OLeakage ±2 uA ICC1 StandbyCurrent CS#= VCC,VIN= GND orVCC 15 25 uA ICC2 Power-downCurrent CS#= VCC,VIN= GND orVCC 2 5 uA ICC3 CurrentRead Data/ Dual/Quad Output Read50MHz(2) C=0.1 VCC /0.9 VCC DO=Open 15 mA ICC3 CurrentRead Data/ Dual/Quad Output Read80MHz(2) C=0.1 VCC /0.9 VCC DO=Open 18 mA ICC3 CurrentRead Data/ Dual/Quad Output Read104MHz(2) C=0.1 VCC /0.9 VCC DO=Open 20 mA ICC4 CurrentPage Program CS#=V CC 20 25 mA ICC5 CurrentWriteStatus Register CS#=V CC 20 25 mA ICC6 CurrentSector/Block Erase CS#= VCC 20 25 mA ICC7 Current ChipErase CS#=V CC 20 25 mA ICC8 HighPerformance Current 50 uA VIL InputLowVoltage -0.5 VCC×0.3 V VIH InputHighVoltage VCC×0.7 V VOL OutputLowVoltage IOL=100 uA 0.2 V VOH OutputHighVoltage IOH= －100uA V CC－0.2 V Notes: (1)Testedonsample basisand specifiedthrough designand characterizationdata.T A=25°C,V CC=3V. (2)Checker BoardPattern. 8.4.AC MeasurementConditions Table 8.5AC Measurement Conditions Symbol PARAMETER Min. Max. Unit CL LoadCapacitance 30 pF TR,TF InputRiseand FallTimes 5 ns VIN InputPulseVoltages 0.2VCC to0.8VCC V VtIN InputTimingReferenceVoltages 0.3VCC to0.7VCC V VtON OutputTiming ReferenceVoltages 0.5VCC to0.5V CC V Figure 8.3AC Measurement I/O Waveform HM25Q128A

8.5.AC ElectricalCharacteristics Table8.6 A C Electrical Characteristics SYMBOL ALT Parameter SPEC UNITMIN TYP MAX FR fC Clockfrequencyforall QPI/Quad IOinstructionswith HFQ,Vcc=2.7V-3.6V D.C. 104 MHz FR fC Clockfrequencyforall SPIinstructions(except 03h/EBh) Vcc=2.7V-3.6V D.C. 104 MHz FR fC Clockfrequencyforall SPIinstructions(except 03h/EBh) Vcc=2.3V-2.7V(1) D.C. 80 MHz fR ClockfrequencyforRead Datainstruction(03h) D.C. 60 MHz tCLH,tCLL(2) ClockHigh,Low Timefor allinstructionsexceptRead Data(03h) 4 ns tCRLH,tCRLL(2) ClockHigh,Low Timefor Read Data(03h)instruction 6 ns tCLCH(3) ClockRise Timepeaktopeak 0.1 V/ns tCHCL(3) ClockFallTimepeaktopeak 0.1 V/ns tSLCH tCSS CS#ActiveSetupTimerelative toCLK 5 ns tCHSL CS#Not ActiveHoldTime relativetoCLK 5 ns tDVCH tDSU DataInSetupTime 2 ns tCHDX tDH DataInHoldTime 5 ns tCHSH CS#ActiveHold TimerelativetoCLK 5 ns tSHCH CS#Not ActiveSetup Timerelative toCLK 5 ns tSHSL1 tCSH1 CS#DeselectTimeSPI( ArrayReadArrayRead) 10 ns tSHSL2 tCSH2 CS#DeselectTimeforErase/Program Read SR VolatileStatusRegister WriteTime 50 ns tSHSL3 tCSH3 CS#DeselectTimefornon ArrayRead →Array Read(Dual IO,QuadIO andQPIRead) 100 ns tSHQZ(3) tDIS OutputDisableTime 7 ns tCLQV tV ClockLowto OutputValid 2.7V-3.6V 7 ns tCLQV tV ClockLowto OutputValid 2.3V- 2.7V 9 ns tCLQX tHO OutputHoldTime 2 ns tHLCH HOLD#ActiveSetupTimerelativetoCLK 5 ns tCHHH HOLD#ActiveHold Timerelative toCLK 5 ns tHHCH HOLD#NotActiveSetupTimerelativeto CLK 5 ns tCHHL HOLD#NotActiveHold TimerelativetoCLK 5 ns tHHQX tLZ(3) HOLD#toOutputLow-Z 7 ns tHLQZ tHZ(3) HOLD#toOutputHigh-Z 12 ns tWHSL(4) WriteProtectSetupTime BeforeCS#Low 20 ns tSHWL(4) WriteProtectHold TimeAfter CS#High 100 ns tDP(3) CS#High toPower-downMode 3 μs tRES1(3) CS#HightoStandby Mode withoutElectronicSignature Read 8 μs tRES2(3) CS#High toStandbyMode withElectronicSignature Read 6 μs tsus(3) CS#High tonext CommandafterSuspend 20 μs tW WriteStatusRegisterTime 10 100 ms tPP PageProgramTime 0.5 1.5 ms tSE SectorEraseTime(4KB) 35 200 ms tBE1 BlockErase Time(32KB) 0.15 0.8 s tBE2 BlockErase Time(64KB) 0.25 2 s tCE ChipEraseTime 50 200 s tRCH(3) EndofResetInstruction toCE# High 40 ns tRST(3)(5) CE#High tonext InstructionafterReset 10 μs Notes: (1)WithHFQ,theclockfrequencyofallSPIinstructions(except 03h/EBh)canreach104MHz. (2)Clockhigh+ Clocklow mustbe lessthanor equal to1/f C. (3)Valueguaranteed bydesignand/or characterization,not 100%testedinproduction. (4)Only applicable as a constraint for a Write Status Register instruction when Sector Protect Bit is set to 1.4. For multiple bytes after first byte within a page, tBPN = tBP1 + tBP2 * N (typical) and tBPN = tBP1 + tBP2 * N (max), where N = number of bytes programmed. (5)It’spossible toresetthedevice with shortertRESET(as shortasa fewhundred ns), a1us minimumisrecommended to ensurereliable operation. HM25Q128A

Figure8.4 SerialOutputTiming Figure8.5 InputTiming Figure8.6 HoldTiming Figure 8.7Software Reset Input Timing HM25Q128A

1. PACKAGE MECHANICAL 9.1. 8-PinSOIC 150-mil 9.2. 8-PinSOIC 208-mil

9.3. 8-ContactWSON (6x5mm) 9.4. 8-PinPDIP300-mil HM25Q128A

9.5. FAB02424-BallBGA 9.6. FAC02424-BallBGAPackage HM25Q128A

No. Description Date A InitialRelease 2017/11/01 HM25Q128A