24C64 SYC | Alldatasheet

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Technical content

Figure 1. Packages

has a push-pull (rather than open drain) output. the value of the pull-up resistor can be calculated). Write operations are allowed. Data bytes are not acknowledged. Figure 4. Maximum RL Value versus Bus Capacitance (CBUS ) for an I2C Bus

Figure 5. I2C Bus Protocol Table 3. Device Select Code Note: 1. The most significant bit, b7, is sent first.

  1. E0, E1 and E2 are compared against the respective external pins on the memory device.

Table 4. Most Significant Byte Table 5. Least Significant Byte

The memory is organized as shown in Figure 6.. Figure 6. Block Diagram

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any device that reads the data to be a receiver. a slave in all communication. and will not respond unless one is given. (SDA) on the rising edge of Serial Clock (SCL). sends the Device Select Code, shown in Table 3. (on Serial Data (SDA), most significant bit first). bit Device Type Identifier is 1010b. code on the Chip Enable (E0, E1, E2) inputs. set to 1 for Read and 0 for Write operations. Table 6. Operating Modes

1 X reSTART, Device Select, RW = 1

Figure 7. Write Mode Sequences with WC=1 (data write inhibited) not acknowledged, as shown in Figure 7.. address of the byte in memory. ter the last one that was modified. dition, as shown in Figure 8..

Figure 8. Write Mode Sequences with WC=0 (data write enabled)

Figure 9. Write Cycle Polling Flowchart using ACK data from its internal latches to the memory cells.

  1. and Table 17., but the typical time is shorter.

– Initial condition: a Write cycle is in progress. byte of the new instruction). having been sent during Step 1).

Figure 10. Read Mode Sequences Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 4th bytes) must be identical. the state of the Write Control (WC) signal. mented by one, to point to the next byte address. ure 10.) but without sending a Stop condition.

M24C64, M24C32 Sequential Read This operation can be used after a Current Ad- dress Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the de- vice continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 10.. The output data comes from consecutive address- es, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter ‘rolls-over’, and the device continues to output data from memory address 00h. Acknowledge in Read Mode For all Read commands, the device waits, after each byte read, for an acknowledgment during the 9th bit time. If the bus master does not drive Serial Data (SDA) Low during this time, the device termi- nates the data transfer and switches to its Stand- by mode. INITIAL DELIVERY STATE The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).

Table 7. may cause permanent damage to the de- Table 7. Absolute Maximum Ratings

  1. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500Ω, R2=500Ω)

Table 8. Operating Conditions (M24Cxx-6) Note: 1. This range is Not for New Design, and will soon be replaced by the M24Cxx-W range. Table 9. Operating Conditions (M24Cxx-W) Table 10. Operating Conditions (M24Cxx-R)

Table 11. AC Measurement Conditions Figure 11. AC Measurement I/O Waveform Table 12. Input Parameters

  1. Sampled only, not 100% tested.

Table 13. DC Characteristics (M24Cxx(1), M24Cxx-W6 and M24Cxx-W3) Note: 1. This range is Not for New Design, and will soon be replaced by the M24Cxx-W range.

Table 14. DC Characteristics (M24Cxx-W6 and M24Cxx-W3) Table 15. DC Characteristics (M24Cxx-R)

Table 16. AC Characteristics (M24Cxx-6, M24Cxx-W6 and M24Cxx-W3) Note: 1. For a reSTART condition, or following a Write cycle.

  1. Sampled only, not 100% tested.
  2. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
  3. The Write Time of 5 ms only applies to devices bearing the process letter “B” in the package marking (on the top side of the pack-

ST sales office, and ask for a copy of the Product Change Notice PCEE0036. Table 17. AC Characteristics (M24Cxx-R) Note: 1. For a reSTART condition, or following a Write cycle.

  1. Sampled only, not 100% tested.
  2. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.

Test conditions specified in Table 11. and Table 8. or Table 9. Test conditions specified in Table 11. and Table 10.

Figure 12. AC Waveforms

Figure 13. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline Note: Drawing is not to scale. Table 18. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data

Figure 14. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline Note: Drawing is not to scale. Table 19. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width,

Figure 15. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline Note: Drawing is not to scale. Table 20. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data

Figure 16. UFDFPN8 (MLP8) – 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm Note: Drawing is not to scale. Table 21. UFDFPN8 (MLP8) – 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm,

Table 22. Ordering Information Scheme tified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy.

  1. This range is Not for New Design, and will soon be replaced by the M24Cxx-W range.
  2. The UFDFPN8 package is available in M24C32 devices only. It is not available in M24C64 devices.

3 = Automotive: device tested with High Reliability Certified Flow(1) over –40 to 125 °C.

M24C64, M24C32

REVISION HISTORY

Table 23. Document Revision History 22-Dec-1999 2.3 TSSOP8 package in place of TSSOP14 (pp 1, 2, OrderingInfo, PackageMechData). Voltage range -S added, and range -R removed from text and tables throughout. Document reformatted using new template. TSSOP8 (3x3mm² body size) package (MSOP8) added. Description, Power-On Reset, Memory Addressing, Write Operations, Read Operations. Design. Some minor wording changes. AEC-Q100-002 compliance. tNS (max) changed. VIL(min) is the same on all input pins of the device. ZWCL changed. 05-Jan-2005 6.0 UFDFPN8 package added. Small text changes.

M24C64, M24C32