22V10

GAL22V10 LATTICE | Alldatasheet

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Features

HIGH PERFORMANCE E 2CMOS ® TECHNOLOGY — 4 ns Maximum Propagation Delay — Fmax = 250 MHz — 3.5 ns Maximum from Clock Input to Data Output — UltraMOS ® Advanced CMOS Technology
ACTIVE PULL-UPS ON ALL PINS
COMPATIBLE WITH STANDARD 22V10 DEVICES — Fully Function/Fuse-Map/Parametric Compatible with Bipolar and UVCMOS 22V10 Devices
50% to 75% REDUCTION IN POWER VERSUS BIPOLAR — 90mA Typical Icc on Low Power Device — 45mA Typical Icc on Quarter Power Device

2 CELL TECHNOLOGY

— Reconfigurable Logic — Reprogrammable Cells — 100% Tested/100% Yields — High Speed Electrical Erasure (<100ms) — 20 Year Data Retention

TEN OUTPUT LOGIC MACROCELLS — Maximum Flexibility for Complex Logic Designs
PRELOAD AND POWER-ON RESET OF REGISTERS — 100% Functional Testability
APPLICATIONS INCLUDE: — DMA Control — State Machine Control — High Speed Graphics Processing — Standard Logic Speed Upgrade
ELECTRONIC SIGNATURE FOR IDENTIFICATION ESCRIPTION

Description

The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E floating gate technology to provide the highest performance avail- able of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much less power when compared to bipolar 22V10 devices. E2 technology offers high speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. The GAL22V10 is fully function/fuse map/parametric com- patible with standard bipolar and CMOS 22V10 devices. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lat- tice Semiconductor delivers 100% field programmability and func- tionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. GAL22V10 High Performance E2CMOS PLD Generic Array Logic™ PROGRAMMABLE AND-ARRAY (132X44) I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I I/CLK I I I I I I I I I I RESET PRESET OLMC OLMC OLMC OLMC OLMC OLMC OLMC OLMC OLMC OLMC Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com GAL22V10 Top View PLCC 1 12 13 24I/CLK I I I I I I I I I I GND Vcc I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I GAL 22V10 22 8 NC I/CLK I I I I I I I I NC NC NC GND I I I I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q Vcc I/O/Q I/O/Q I/O/Q 42 6 161412 DIP 22v10_06 Functional Block Diagram Pin Configuration

)sn(dpT) sn(usT) sn(ocT) Am(ccI# gniredrOe gakcaP 45 .25 .30 41J L4-D01V22LAG CCLPdaeL-82 534 0 41J L5-D01V22LAG CCLPdaeL-82 051J L5-C01V22LAG CCLPdaeL-82 5.75 .45 .40 41P L7-D01V22LAG PIDcitsalPniP-42 55 .40 41P L7-C01V22LAG PIDcitsalPniP-42 5.45 .40 41J L7-C01V22LAGroJL7-D01V22LAG CCLPdaeL-82 5.65 0 41P L7-B01V22LAG PIDcitsalPniP-42 041J L7-B01V22LAG CCLPdaeL-82 017 75 5P Q01-D01V22LAG PIDcitsalPniP-42 55J Q01-D01V22LAG CCLPdaeL-82 031P L01-B01V22LAGroPL01-C01V22LAG,PL01-D01V22LAG PIDcitsalPniP-42 031J L01-B01V22LAGroJL01-C01V22LAG,JL01-D01V22LAG CCLPdaeL-82 510 185 5P Q51-B01V22LAGroPQ51-D01V22LAG PIDcitsalPniP-42 55J Q51-B01V22LAGroJQ51-D01V22LAG CCLPdaeL-82 031P L51-B01V22LAGroPL51-D01V22LAG PIDcitsalPniP-42 031J L51-B01V22LAGroJL51-D01V22LAG CCLPdaeL-82 525 15 15 5P Q52-B01V22LAGroPQ52-D01V22LAG PIDcitsalPniP-42 55J Q52-B01V22LAGroJQ52-D01V22LAG CCLPdaeL-82 09P L52-B01V22LAGroPL52-D01V22LAG piDcitsalPniP-42 09J L52-B01V22LAGroJL52-D01V22LAG CCLPniP-82 )sn(dpT) sn(usT) sn(ocT) Am(ccI# gniredrOe gakcaP 5.755 .40 61 01V22LAGD I PL7-r oI PL7-C01V22LAG PIDcitsalPniP-42 5.45 .40 61 01V22LAGD I JL7-r oI JL7-C01V22LAG CCLPdaeL-82 017 7 0 61 01V22LAGD I PL01-r oI PL01-C01V22LAG PIDcitsalPniP-42 061 01V22LAGD I JL01-r oI JL01-C01V22LAG CCLPdaeL-82 510 18 0 51r oIPL51-D01V22LAGI PL51-B01V22LAGP IDcitsalPniP-42 051r oIJL51-D01V22LAGI JL51-B01V22LAGC CLPdaeL-82 024 10 10 51r oIPL02-D01V22LAGI PL02-B01V22LAGP IDcitsalPniP-42 051r oIJL02-D01V22LAGI JL02-B01V22LAGC CLPdaeL-82 525 15 10 51r oIPL52-D01V22LAGI PL52-B01V22LAGP IDcitsalPniP-42 051r oIJL52-D01V22LAGI JL52-B01V22LAGC CLPdaeL-82 Commercial Grade Specifications Industrial Grade Specifications Blank = Commercial I = Industrial Grade PackagePowerL = Low Power Q = Quarter Power Speed (ns) XXXXXXXX XX X X X Device Name P = Plastic DIP J = PLCC GAL22V10D GAL22V10C GAL22V10B Part Number Description

GAL22V10 OUTPUT LOGIC MACROCELL (OLMC) Each of the Macrocells of the GAL22V10 has two primary functional modes: registered, and combinatorial I/O. The modes and the output polarity are set by two bits (SO and S1), which are normally controlled by the logic compiler. Each of these two primary modes, and the bit settings required to enable them, are described below and on the following page. REGISTERED In registered mode the output pin associated with an individual OLMC is driven by the Q output of that OLMC’s D-type flip-flop. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an in- dividual product-term for each OLMC, and can therefore be defined by a logic equation. The D flip-flop’s /Q output is fed back into the AND array, with both the true and complement of the feedback available as inputs to the AND array. NOTE: In registered mode, the feedback is from the /Q output of the register, and not from the pin; therefore, a pin defined as reg- istered is an output only, and cannot be used for dynamic I/O, as can the combinatorial pins. COMBINATORIAL I/O In combinatorial mode the pin associated with an individual OLMC is driven by the output of the sum term gate. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Out- put tri-state control is available as an individual product-term for each output, and may be individually set by the compiler as either “on” (dedicated output), “off” (dedicated input), or “product-term driven” (dynamic I/O). Feedback into the AND array is from the pin side of the output enable buffer. Both polarities (true and inverted) of the pin are fed back into the AND array. The GAL22V10 has a variable number of product terms per OLMC. Of the ten available OLMCs, two OLMCs have access to eight product terms (pins 14 and 23, DIP pinout), two have ten product terms (pins 15 and 22), two have twelve product terms (pins 16 and 21), two have fourteen product terms (pins 17 and 20), and two OLMCs have sixteen product terms (pins 18 and 19). In addition to the product terms available for logic, each OLMC has an addi- tional product-term dedicated to output enable control. The output polarity of each OLMC can be individually programmed to be true or inverting, in either combinatorial or registered mode. This allows each output to be individually configured as either active high or active low. The GAL22V10 has a product term for Asynchronous Reset (AR) and a product term for Synchronous Preset (SP). These two prod- uct terms are common to all registered OLMCs. The Asynchronous Reset sets all registers to zero any time this dedicated product term is asserted. The Synchronous Preset sets all registers to a logic one on the rising edge of the next clock pulse after this product term is asserted. NOTE: The AR and SP product terms will force the Q output of the flip-flop into the same state regardless of the polarity of the output. Therefore, a reset operation, which sets the register output to a zero, may result in either a high or low at the output pin, depending on the pin polarity chosen. AR SP D Q QCLK

4 TO 1

2 TO 1

Output Logic Macrocell (OLMC) Output Logic Macrocell Configurations

S0 = 1 S1 = 1 S0 = 0 S1 = 1 S0 = 0 S1 = 0 S0 = 1 S1 = 0 AR SP D Q QCLK AR SP D Q QCLK Registered Mode Combinatorial Mode

DIP (PLCC) Package Pinouts 1 (2) 22 (26)OLMC 5810 5811 0440 0880 2 (3) ASYNCHRONOUS RESET (TO ALL REGISTERS) 0 4 8 1 21 62 02 42 83 23 64 0 SYNCHRONOUS PRESET (TO ALL REGISTERS) 10 (12) 0000 5764 0044 0396 23 (27)S0 5808 5809 21 (25)OLMC 5812 5813 0924 1452 3 (4) 4 (5) 5 (6) 20 (24)OLMC 5814 5815 1496 2112 19 (23)OLMC 5816 5817 2156 2860 18 (21)OLMC 5818 5819 2904 3608 17 (20)OLMC 5820 5821 3652 4268 OLMC 5822 5823 4312 4840 8 (10) 16 (19) 15 (18)OLMC 5824 5825 4884 5324 9 (11) 5368 5720 14 (17)OLMC 5826 5827 7 (9) 6 (7) 11 (13) 13 (16)

8 OLMC

L S B M S B Byte 7 Byte 6 Byte 5 Byte 4 Byte 2 Byte 1 Byte 0Byte 3 GAL22V10 Logic Diagram / JEDEC Fuse Map

Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). Commercial Devices: Supply voltage (VCC ) Industrial Devices: Supply voltage (VCC ) Specifications GAL22V10D COMMERCIAL ICC Operating Power VIL = 0.5V VIH = 3.0V L-4/-5/-7 — 90 140 mA Supply Current ftoggle = 15MHz Outputs Open L-10 — 90 130 mA L-15/-25 — 75 90 mA VIL Input Low Voltage Vss – 0.5 — 0.8 V VIH Input High Voltage 2.0 — Vcc+1 V IIL1 Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) —— – 100 µA IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC —— 10 µA VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH —— 0.4 V VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 —— V IOL Low Level Output Current —— 16 mA IOH High Level Output Current —— – 3.2 mA IOS 2 Output Short Circuit Current VCC = 5V VOUT = 0.5V TA = 25°C –30 —– 130 mA Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER CONDITION MIN. TYP . 3 MAX. UNITS INDUSTRIAL ICC Operating Power VIL = 0.5V VIH = 3.0V L-7/-10 — 90 160 mA Supply Current ftoggle = 15MHz Outputs Open L-15/-20/-25 — 75 130 mA 1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 5V and T A = 25 °C Absolute Maximum Ratings1 Recommended Operating Conditions

tpd A Input or I/O to Combinatorial Output 1 4 1 5 1 7.5 ns tco A Clock to Output Delay 1 3.5 1 4 1 4.5 ns tcf2 — Clock to Feedback Delay — 2.5 — 3 — 3n s tsu — Setup Time, Input or Fdbk before Clk↑ 2.5 — 3 — 4.5 — ns th — Hold Time, Input or Fdbk after Clk↑ 0 — 0 — 0 — ns A Maximum Clock Frequency with 167 — 142.8 — 111 — MHz External Feedback, 1/(tsu + tco) fmax 3 A Maximum Clock Frequency with 200 — 166 — 133 — MHz Internal Feedback, 1/(tsu + tcf) A Maximum Clock Frequency with 250 — 200 — 166 — MHz No Feedback twh — Clock Pulse Duration, High 2 — 2.5 — 3 — ns twl — Clock Pulse Duration, Low 2 — 2.5 — 3 — ns ten B Input or I/O to Output Enabled 1 5 1 6 1 7.5 ns tdis C Input or I/O to Output Disabled 1 5 1 5.5 1 7.5 ns tar A Input or I/O to Asynch. Reset of Reg. 1 4.5 1 5.5 1 9 ns tarw — Asynch. Reset Pulse Duration 4.5 — 4.5 — 7 — ns tarr — Asynch. Reset to Clk↑ Recovery Time 3 — 4 — 5 — ns tspr — Synch. Preset to Clk↑ Recovery Time 3 — 4 — 5 — ns Over Recommended Operating Conditions UNITS 1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Description section. 3) Refer to fmax Description section. Characterized initially and after any design or process changes that may affect these parameters. PARAM TEST COND. 1 SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS C I Input Capacitance 8 pF V CC = 5.0V, VI = 2.0V C I/O I/O Capacitance 8 pF V CC = 5.0V, VI/O = 2.0V *Characterized but not 100% tested. MIN. MAX. COM/INDCOM MIN. MAX. AC Switching Characteristics Capacitance (TA = 25°C, f = 1.0 MHz) Specifications GAL22V10D COM MIN. MAX.

tpd A Input or I/O to Comb. Output 1 10 3 15 3 20 3 25 ns tco A Clock to Output Delay 1 7 2 8 2 10 2 15 ns tcf2 — Clock to Feedback Delay — 2.5 — 2.5 — 8 — 13 ns tsu — Setup Time, Input or Fdbk before Clk↑ 6 — 10 — 12 — 15 — ns th — Hold Time, Input or Fdbk after Clk↑ 0 — 0 — 0 — 0 — ns A Maximum Clock Frequency with 83.3 — 55.5 — 41.6 — 33.3 — MHz External Feedback, 1/(tsu + tco) fmax 3 A Maximum Clock Frequency with 110 — 80 — 45.4 — 35.7 — MHz Internal Feedback, 1/(tsu + tcf) A Maximum Clock Frequency with 125 — 83.3 — 50 — 38.5 — MHz No Feedback twh — Clock Pulse Duration, High 4 — 6 — 10 — 13 — ns twl — Clock Pulse Duration, Low 4 — 6 — 10 — 13 — ns ten B Input or I/O to Output Enabled 1 10 3 15 3 20 3 25 ns tdis C Input or I/O to Output Disabled 1 9 3 15 3 20 3 25 ns tar A Input or I/O to Asynch. Reset of Reg. 1 13 3 20 3 25 3 25 ns tarw — Asynch. Reset Pulse Duration 8 — 15 — 20 — 25 — ns tarr — Asynch. Reset to Clk↑ Recovery Time 8 — 10 — 20 — 25 — ns tspr — Synch. Preset to Clk↑ Recovery Time 8 — 10 — 14 — 15 — ns Specifications GAL22V10D -10 MIN. MAX. -25 MIN. MAX. -20 MIN. MAX. -15 MIN. MAX. Over Recommended Operating Conditions UNITS 1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Description section. 3) Refer to fmax Description section. SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS C I Input Capacitance 8 pF V CC = 5.0V, VI = 2.0V C I/O I/O Capacitance 8 pF V CC = 5.0V, VI/O = 2.0V *Characterized but not 100% tested. PARAM. TEST COND. 1 DESCRIPTION COM / IND IND COM / INDCOM / IND Capacitance (TA = 25°C, f = 1.0 MHz) AC Switching Characteristics

Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). COMMERCIAL ICC Operating Power Supply Current VIL = 0.5V VIH = 3.0V L-5 — 90 150 mA ftoggle = 15MHz Outputs Open L-7 — 90 140 mA L-10 — 90 130 mA VIL Input Low Voltage Vss – 0.5 — 0.8 V VIH Input High Voltage 2.0 — Vcc+1 V IIL1 Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) —— – 100 µA IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC —— 10 µA VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH —— 0.5 V VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 —— V IOL Low Level Output Current —— 16 mA IOH High Level Output Current —— – 3.2 mA IOS 2 Output Short Circuit Current VCC = 5V VOUT = 0.5V TA = 25°C –30 —– 130 mA Commercial Devices: Supply voltage (VCC ) Industrial Devices: Supply voltage (VCC ) Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER CONDITION MIN. TYP . 3 MAX. UNITS INDUSTRIAL ICC Operating Power Supply Current VIL = 0.5V VIH = 3.0V L-7/-10 — 90 160 mA ftoggle = 15MHz Outputs Open 1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 5V and T A = 25 °C Absolute Maximum Ratings1 Recommended Operating Conditions

tpd A Input or I/O to Combinatorial Output 1 5 1 7.5 1 7.5 3 10 1 10 ns tco A Clock to Output Delay 1 4 1 4.5 1 4.5 2 7 1 7 ns tcf2 — Clock to Feedback Delay — 3 — 3 — 3 — 2.5 — 2.5 ns tsu — Setup Time, Input or Fdbk before Clk↑ 3 — 4.5 — 5 — 7 — 7 — ns th — Hold Time, Input or Fdbk after Clk↑ 0 — 0 — 0 — 0 — 0 — ns A Maximum Clock Frequency with 142.8 — 111 — 105 — 71.4 — 71.4 — MHz External Feedback, 1/(tsu + tco) fmax 3 A Maximum Clock Frequency with 166 — 133 — 125 — 105 — 105 — MHz Internal Feedback, 1/(tsu + tcf) A Maximum Clock Frequency with 200 — 166 — 142.8 — 105 — 105 — MHz No Feedback twh — Clock Pulse Duration, High 2.5 — 3 — 3.5 — 4 — 4 — ns twl — Clock Pulse Duration, Low 2.5 — 3 — 3.5 — 4 — 4 — ns ten B Input or I/O to Output Enabled 1 6 1 7.5 1 7.5 3 10 1 10 ns tdis C Input or I/O to Output Disabled 1 6 1 7.5 1 7.5 3 9 1 9 ns tar A Input or I/O to Asynch. Reset of Reg. 1 5.5 1 9 1 9 3 13 1 13 ns tarw — Asynch. Reset Pulse Duration 5.5 — 7 — 7 — 8 — 8 — ns tarr — Asynch. Reset to Clk↑ Recovery Time 4 — 5 — 5 — 8 — 8 — ns tspr — Synch. Preset to Clk↑ Recovery Time 4 — 5 — 5 — 10 — 10 — ns Specifications GAL22V10C Over Recommended Operating Conditions UNITS 1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Description section. 3) Refer to fmax Description section. Characterized initially and after any design or process changes that may affect these parameters. PARAM TEST COND. 1 DESCRIPTION SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS C I Input Capacitance 8 pF V CC = 5.0V, VI = 2.0V C I/O I/O Capacitance 8 pF V CC = 5.0V, VI/O = 2.0V *Characterized but not 100% tested. MIN. MAX. COM/INDCOM -7 (PLCC) MIN. MAX. -10 MIN. MAX. -7 (PDIP) MIN. MAX. COMCOM/IND -10 MIN. MAX. IND AC Switching Characteristics Capacitance (TA = 25°C, f = 1.0 MHz)

Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). Commercial Devices: Supply voltage (VCC ) Industrial Devices: Supply voltage (VCC ) Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER CONDITION MIN. TYP . 3 MAX. UNITS VIL Input Low Voltage Vss – 0.5 — 0.8 V VIH Input High Voltage 2.0 — Vcc+1 V IIL1 Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) —— – 100 µA IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC —— 10 µA VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH —— 0.5 V VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 —— V IOL Low Level Output Current —— 16 mA IOH High Level Output Current —— – 3.2 mA IOS 2 Output Short Circuit Current VCC = 5V VOUT = 0.5V TA = 25°C –30 —– 130 mA COMMERCIAL ICC Operating Power VIL = 0.5V VIH = 3.0V L-7 — 90 140 mA Supply Current ftoggle = 15MHz Outputs Open L-10/-15 — 90 130 mA L-25 — 75 90 mA Q-15/-25 — 45 55 mA INDUSTRIAL ICC Operating Power VIL = 0.5V VIH = 3.0V L-15/-20/-25 — 90 150 mA Supply Current ftoggle = 15MHz Outputs Open 1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 5V and T A = 25 °C Absolute Maximum Ratings1 Recommended Operating Conditions

-10 MIN. MAX. -25 MIN. MAX. -20 MIN. MAX. -15 MIN. MAX. MIN. MAX. AC SWITCHING CHARACTERISTICS Over Recommended Operating Conditions tpd A Input or I/O to Comb. Output 3 7.5 3 10 3 15 3 20 3 25 ns tco A Clock to Output Delay 2 5 2 7 2 8 2 10 2 15 ns tcf2 — Clock to Feedback Delay — 2.5 — 2.5 — 2.5 — 8 — 13 ns tsu1 — Setup Time, Input or Fdbk before Clk↑ 6.5 — 7 — 10 — 14 — 15 — ns tsu2 — Setup Time, SP before Clock↑ 10 — 10 — 10 — 14 — 15 — ns th — Hold Time, Input or Fdbk after Clk↑ 0 — 0 — 0 — 0 — 0 — ns A Maximum Clock Frequency with 87 — 71.4 — 55.5 — 41.6 — 33.3 — MHz External Feedback, 1/(tsu + tco) fmax 3 A Maximum Clock Frequency with 111 — 105 — 80 — 45.4 — 35.7 — MHz Internal Feedback, 1/(tsu + tcf) A Maximum Clock Frequency with 111 — 105 — 83.3 — 50 — 38.5 — MHz No Feedback twh — Clock Pulse Duration, High 4 — 4 — 6 — 10 — 13 — ns twl — Clock Pulse Duration, Low 4 — 4 — 6 — 10 — 13 — ns ten B Input or I/O to Output Enabled 3 8 3 10 3 15 3 20 3 25 ns tdis C Input or I/O to Output Disabled 3 8 3 9 3 15 3 20 3 25 ns tar A Input or I/O to Asynch. Reset of Reg. 3 13 3 13 3 20 3 25 3 25 ns tarw — Asynch. Reset Pulse Duration 8 — 8 — 15 — 20 — 25 — ns tarr — Asynch. Reset to Clk↑ Recovery Time 8 — 8 — 10 — 20 — 25 — ns tspr — Synch. Preset to Clk↑ Recovery Time 10 — 10 — 10 — 14 — 15 — ns UNITS 1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Description section. 3) Refer to fmax Description section. SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS C I Input Capacitance 8 pF V CC = 5.0V, VI = 2.0V C I/O I/O Capacitance 8 pF V CC = 5.0V, VI/O = 2.0V *Characterized but not 100% tested. PARAM. TEST COND. 1 DESCRIPTION COM COM COM / IND IND COM / IND AC Switching Characteristics Capacitance (TA = 25°C, f = 1.0 MHz)

Input or I/O to Output Enable/Disable Registered Output Combinatorial Output VALID INPUTINPUT or I/O FEEDBACK tpd COMBINATORIAL OUTPUT INPUT or I/O FEEDBACK REGISTERED OUTPUT CLK VALID INPUT tsu tco th (external fdbk) 1/ fmax tentdis INPUT or I/O FEEDBACK OUTPUT CLK (w/o fdbk) twh twl 1/ fmax Clock Width REGISTERED OUTPUT CLK INPUT or I/O FEEDBACK DRIVING SP tsu th tco tspr REGISTERED OUTPUT CLK tarw tar tarr INPUT or I/O FEEDBACK DRIVING AR fmax with Feedback Asynchronous ResetSynchronous Preset CLK REGISTERED FEEDBACK tcf tsu 1/ fmax (internal fdbk) Switching Waveforms

fmax with Internal Feedback 1/(tsu+tcf) Note: fmax with external feedback is cal- culated from measured tsu and tco. fmax with External Feedback 1/(tsu+tco) Note: tcf is a calculated value, derived by sub- tracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combi- natorial output is equal to tcf + tpd. fmax with No Feedback Note: fmax with no feedback may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. REGISTERLOGIC ARRAY tcotsu CLK REGISTERLOGIC ARRAY CLK tsu + th CLK REGISTER LOGIC ARRAY tcf tpd fmax Descriptions

GAL22V10D-4 Output Load Conditions (see figure below) Test Condition R 1 C L A5 0 Ω 50pF B Z to Active High at 1.9V 50 Ω 50pF Z to Active Low at 1.0V 50 Ω 50pF C Active High to Z at 1.9V 50 Ω 50pF Active Low to Z at 1.0V 50 Ω 50pF Input Pulse Levels GND to 3.0V Input Rise and D-4/-5/-7, C-5 1.5ns 10% – 90% Fall Times D-10/-15/-20/-25 2.0ns 10% – 90% B & C-7/-10 Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V Output Load See Figure 3-state levels are measured 0.5V from steady-state active level. TEST POINT C *L FROM OUTPUT (O/Q) UNDER TEST +5V *C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE R 2 R 1 Output Load Conditions (except D-4) (see figure below) Test Condition R 1 R 2 C L A 300 Ω 390Ω 50pF B Active High ∞ 390Ω 50pF Active Low 300 Ω 390Ω 50pF C Active High ∞ 390Ω 5pF Active Low 300 Ω 390Ω 5pF TEST POINT Z0 = 50Ω , CL*FROM OUTPUT (O/Q) UNDER TEST +1.45V R 1 Switching Test Conditions

An electronic signature (ES) is provided in every GAL22V10 device. It contains 64 bits of reprogrammable memory that can contain user-defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the se- curity cell. The electronic signature is an additional feature not present in other manufacturers' 22V10 devices. To use the extra feature of the user-programmable electronic signature it is necessary to choose a Lattice Semiconductor 22V10 device type when com- piling a set of logic equations. In addition, many device program- mers have two separate selections for the device, typically a GAL22V10 and a GAL22V10-UES (UES = User Electronic Sig- nature) or GAL22V10-ES. This allows users to maintain compat- ibility with existing 22V10 designs, while still having the option to use the GAL device's extra feature. The JEDEC map for the GAL22V10 contains the 64 extra fuses for the electronic signature, for a total of 5892 fuses. However, the GAL22V10 device can still be programmed with a standard 22V10 JEDEC map (5828 fuses) with any qualified device pro- grammer. Security Cell A security cell is provided in every GAL22V10 device to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. The Electronic Signature is always avail- able to the user, regardless of the state of this control cell. Latch-Up Protection GAL22V10 devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias is of sufficient magnitude to prevent input undershoots from causing the circuitry to latch. Additionally, outputs are designed with n-channel pullups instead of the traditional p-channel pullups to eliminate any pos- sibility of SCR induced latching. Device Programming GAL devices are programmed using a Lattice Semiconductor- approved Logic Programmer, available from a number of manu- facturers (see the the GAL Development Tools section). Com- plete programming of the device takes only a few seconds. Eras- ing of the device is transparent to the user, and is done automati- cally as part of the programming cycle. Typical Input Current -60 -20 -40 Input Voltage (Volts) Input Current (uA) Output Register Preload When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. This is because certain events may occur during system operation that throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. Then the machine can be sequenced and the outputs tested for correct next state condi- tions. The GAL22V10 device includes circuitry that allows each regis- tered output to be synchronously set either high or low. Thus, any present state condition can be forced for test sequencing. If necessary, approved GAL programmers capable of executing test vectors perform output register preload automatically. Input Buffers GAL22V10 devices are designed with TTL level compatible in- put buffers. These buffers have a characteristically high imped- ance, and present a much lighter load to the driving logic than bi- polar TTL devices. The input and I/O pins also have built-in active pull-ups. As a re- sult, floating inputs will float to a TTL high (logic 1). However, Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins be connected to an adjacent active input, Vcc, or ground. Doing so will tend to improve noise immunity and reduce Icc for the device. (See equivalent input and I/O schemat- ics on the following page.)

(Vref Typical = 3.2V) (Vref Typical = 3.2V) Circuitry within the GAL22V10 provides a reset signal to all reg- isters during power-up. All internal registers will have their Q out- puts set low after a specified time (tpr, 1µs MAX). As a result, the state on the registered output pins (if they are enabled) will be either high or low on power-up, depending on the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. The timing diagram for power-up is shown below. Because of the asyn- chronous nature of system power-up, some conditions must be met to guarantee a valid power-up reset of the GAL22V10. First, the Vcc rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time. As in nor- mal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements. Vcc PIN Vcc Vref Active Pull-up Circuit ESD Protection Circuit ESD Protection Circuit Vcc PIN Vcc (min.) tpr Internal Register Reset to Logic "0" Device Pin Reset to Logic "1" twl tsu Device Pin Reset to Logic "0" Vcc CLK INTERNAL REGISTER Q - OUTPUT ACTIVE LOW OUTPUT REGISTER ACTIVE HIGH OUTPUT REGISTER Vcc PIN VrefTri-State Control Active Pull-up Circuit Feedback (To Input Buffer) PIN Feedback Data Output Typical Input Typical Output Power-Up Reset Input/Output Equivalent Schematics

Delta Tpd vs # of Outputs Switching -0.3 -0.2 -0.1 123456789 1 0 Number of Outputs Switching Delta Tpd (ns) RISE FALL Delta Tco vs # of Outputs Switching -0.4 -0.3 -0.2 -0.1 123456789 1 0 Number of Outputs Switching Delta Tco (ns)Delta Tco (ns) RISE FALL Delta Tpd vs Output Loading Output Loading (pF) Delta Tpd (ns) RISE FALL Delta Tco vs Output Loading RISE FALL Normalized Tpd vs Vcc Normalized TpdNormalized Tpd RISE FALL Normalized Tco vs Vcc RISE FALL Normalized Tsu vs Vcc Supply Voltage (V)Supply Voltage (V)Supply Voltage (V) RISE FALL Normalized Tpd vs Temp Normalized Tco vs Temp Normalized Tsu vs Temp 1251007550250-25-55 1251007550250-25-55 300250200150100500 Output Loading (pF) 300250200150100500 Temperature (deg. C) Temperature (deg. C) Temperature (deg. C) 1251007550250-25-55 RISE FALL RISE FALL RISE FALL 5.55.2554.754.5 0.9 1.3 1.2 1.1 0.9 0.8 1.3 1.2 1.1 0.9 0.80.9 1.1 1.2 0.95 1.05 1.1 Normalized TcoNormalized Tco 0.9 0.95 1.05 1.1 Normalized TNormalized T su 0.9 0.95 1.05 1.1 GAL22V10D-4/-5/-7/-10L (PLCC): Typical AC and DC Characteristic Diagrams

0.2 0.4 0.6 0 5 10 15 20 25 30 35 40 Iol (mA) Vol (V) Voh vs Ioh 0 5 10 15 20 25 30 35 40 45 50 55 60 Ioh(mA) Voh (V) Voh vs Ioh 3.15 3.25 3.35 3.45 3.55 3.65 3.75 3.85 3.95 Ioh(mA) Voh (V) Normalized Icc vs Vcc 0.8 0.9 1.1 1.2 4.5 4.75 5 5.25 5.5 Supply Voltage (V) Normalized Icc Normalized Icc vs Temp 0.7 0.8 0.9 1.1 1.2 1.3 - 5 5 - 2 5 0 2 55 08 8 1 0 0 1 2 5 Temperature (deg. C) Normalized Icc Normalized Icc vs Freq 0.95 1.05 1.1 1.15 1.2 1 1 52 55 07 5 1 0 0 Frequency (MHz) Normalized Icc Input Clamp (Vik) Vik (V) Iik (mA) Delta Icc vs Vin (1 input) 100 Vin (V) Delta Icc (mA) GAL22V10D-4/-5/-7/-10L (PLCC): Typical AC and DC Characteristic Diagrams

GAL22V10D-7/10L (PDIP): Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 0.9 0.95 1.05 1.1 4.5 4.75 5 5.25 5.5 Supply Voltage (V) Normalized Tpd RISE FALL Normalized Tco vs Vcc 0.95 1.05 1.1 4.5 4.75 5 5.25 5.5 Supply Voltage (V) Normalized Tco RISE FALL Normalized Tsu vs Vcc 0.8 0.9 1.1 1.2 4.5 4.75 5 5.25 5.5 Supply Voltage (V) Normalized Tsu RISE FALL Normalized Tpd vs Temp 0.8 0.9 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 Temperature (deg. C) Normalized Tpd RISE FALL Normalized Tsu vs Temp 0.8 0.9 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 Temperature (deg. C) Normalized Tsu RISE FALL Normalized Tco vs Temp 0.8 0.9 1.1 1.2 -55 -25 0 25 50 75 100 125 Temperature (deg. C) Normalized Tco RISE FALL Delta Tpd vs # of Outputs Switching -1.1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 123456789 1 0 Number of Outputs Switching Delta Tpd (ns) RISE FALL Delta Tco vs # of Outputs Switching -1.1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 123456789 1 0 Number of Outputs Switching Delta Tco (ns) RISE FALL Delta Tpd vs Output Loading 0 50 100 150 200 250 300 Output Loading (pF) Delta Tpd (ns) RISE FALL Delta Tco vs Output Loading 0 50 100 150 200 250 300 Output Loading (pF) Delta Tco (ns) RISE FALL

GAL22V10D-7/10L (PDIP): Typical AC and DC Characteristic Diagrams Vol vs Iol 0.1 0.2 0.3 0.4 0.5 0 5 10 15 20 25 30 Iol (mA) Vol (V) Voh vs Ioh 0 5 10 15 20 25 30 35 40 Ioh (mA) Voh (V) Voh vs Ioh 2.8 2.9 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 Ioh (mA) Voh (V) Normalized Icc vs Vcc 0.85 0.9 0.95 1.05 1.1 1.15 4.5 4.75 5 5.25 5.5 Supply Voltage (V) Normalized Icc Normalized Icc vs Temp 0.7 0.8 0.9 1.1 1.2 1.3 -55 0 25 100 Temperature (deg. C) Normalized Icc Normalized Icc vs Freq 0.95 1.05 1.1 1.15 1.2 1 1 52 55 07 5 1 0 0 Frequency (MHz) Normalized Icc Input Clamp (Vik) 100 Vik (V) Iik (mA) Delta Isb vs Vin (1 input) Vin (V) Delta Icc (mA)

0.9 0.95 1.05 1.1 4.5 4.75 5 5.25 5.5 Supply Voltage (V) Normalized Tpd RISE FALL Normalized Tco vs Vcc 0.9 0.95 1.05 1.1 1.15 4.5 4.75 5 5.25 5.5 Supply Voltage (V) Normalized Tco RISE FALL Normalized Tsu vs Vcc 0.8 0.9 1.1 1.2 4.5 4.75 5 5.25 5.5 Supply Voltage (V) Normalized Tsu RISE FALL Normalized Tpd vs Temp 0.8 0.9 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 Temperature (deg. C) Normalized Tpd RISE FALL Normalized Tsu vs Temp 0.75 0.85 0.95 1.05 1.15 1.25 1.35 1.45 -55 -25 0 25 50 75 100 125 Temperature (deg. C) Normalized Tsu RISE FALL Normalized Tco vs Temp 0.8 0.9 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 Temperature (deg. C) Normalized Tco RISE FALL Delta Tpd vs # of Outputs Switching -1.2 -0.8 -0.4 123456789 1 0 Number of Outputs Switching Delta Tpd (ns) RISE FALL Delta Tco vs # of Outputs Switching -1.2 -0.8 -0.4 123456789 1 0 Number of Outputs Switching Delta Tco (ns) RISE FALL Delta Tpd vs Output Loading 0 50 100 150 200 250 300 Output Loading (pF) Delta Tpd (ns) RISE FALL Delta Tco vs Output Loading 0 50 100 150 200 250 300 Output Loading (pF) Delta Tco (ns) RISE FALL GAL22V10D-10Q and Slower (L & Q): Typical AC and DC Characteristic Diagrams

0.2 0.4 0.6 0 5 10 15 20 25 30 35 40 Iol (mA) Vol (V) Voh vs Ioh 0.5 1.5 2.5 3.5 4.5 02 0 4 0 6 0 Ioh (mA) Voh (V) Voh vs Ioh 2.5 3.5 4.5 Ioh (mA) Voh (V) Normalized Icc vs Vcc 0.8 0.9 1.1 1.2 4.5 4.75 5 5.25 5.5 Supply Voltage (V) Normalized Icc Normalized Icc vs Temp 0.75 0.85 0.95 1.05 1.15 1.25 1.35 -55 -25 0 25 50 88 100 125 Temperature (deg. C) Normalized Icc Normalized Icc vs Freq 0.9 1.1 1.2 1.3 1.4 1 1 52 55 07 5 1 0 0 Frequency (MHz) Normalized Icc Input Clamp (Vik) Vik (V) Iik (mA) Delta Icc vs Vin (1 input) Vin (V) Delta Icc (mA) GAL22V10DQ-10 and Slower (L & Q): Typical AC and DC Characteristic Diagrams

Supply Voltage (V) Normalized Tpd 0.8 0.9 1.1 1.2 PT H->L PT L->H Normalized Tco vs Vcc Supply Voltage (V) Normalized Tco 0.8 0.9 1.1 1.2 RISE FALL Normalized Tsu vs Vcc Supply Voltage (V) Normalized Tsu 0.8 0.9 1.1 1.2 PT H->L PT L->H Normalized Tpd vs Temp Temperature (deg. C) Normalized Tpd 0.7 0.8 0.9 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 PT H->L PT L->H Normalized Tco vs Temp Temperature (deg. C) Normalized Tco 0.7 0.8 0.9 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 RISE FALL Normalized Tsu vs Temp Temperature (deg. C) Normalized Tsu 0.7 0.8 0.9 1.1 1.2 1.3 1.4 -55 -25 0 25 50 75 100 125 PT H->L PT L->H Delta Tpd vs # of Outputs Switching Number of Outputs Switching Delta Tpd (ns) -1.5 -1.25 -0.75 -0.5 -0.25 123456789 1 0 RISE FALL Delta Tco vs # of Outputs Switching Number of Outputs Switching Delta Tco (ns) -0.75 -0.5 -0.25 123456789 1 0 RISE FALL Delta Tpd vs Output Loading Output Loading (pF) Delta Tpd (ns) 0 50 100 150 200 250 300 RISE FALL Delta Tco vs Output Loading Output Loading (pF) Delta Tco (ns) 0 50 100 150 200 250 300 RISE FALL GAL22V10C-5/-7/-10: Typical AC and DC Characteristic Diagrams

Iol (mA) Vol (V) 0.5 1.5 2.5 Voh vs Ioh Ioh(mA) Voh (V) Voh vs Ioh Ioh(mA) Voh (V) 3.25 3.5 3.75 Normalized Icc vs Vcc Supply Voltage (V) Normalized Icc 0.80 0.90 1.00 1.10 1.20 Normalized Icc vs Temp Temperature (deg. C) Normalized Icc 0.8 0.9 1.1 1.2 -55 -25 0 25 50 75 100 125 Normalized Icc vs Freq. Frequency (MHz) Normalized Icc 0.90 1.00 1.10 1.20 1.30 0 25 50 75 100 Delta Icc vs Vin (1 input) Vin (V) Delta Icc (mA) Input Clamp (Vik) Vik (V) Iik (mA) GAL22V10C-5/-7/-10: Typical AC and DC Characteristic Diagrams

Supply Voltage (V) Normalized Tpd 0.8 0.9 1.1 1.2 PT H->L PT L->H Normalized Tco vs Vcc Supply Voltage (V) Normalized Tco 0.8 0.9 1.1 1.2 RISE FALL Normalized Tsu vs Vcc Supply Voltage (V) Normalized Tsu 0.8 0.9 1.1 1.2 PT H->L PT L->H Normalized Tpd vs Temp Temperature (deg. C) Normalized Tpd 0.7 0.8 0.9 1.1 1.2 1.3 -55 -25 100 125 PT H->L PT L->H Normalized Tco vs Temp Temperature (deg. C) Normalized Tco 0.7 0.8 0.9 1.1 1.2 1.3 -55 -25 100 125 RISE FALL Normalized Tsu vs Temp Temperature (deg. C) Normalized Tsu 0.7 0.8 0.9 1.1 1.2 1.3 1.4 -55 -25 100 125 PT H->L PT L->H Delta Tpd vs # of Outputs Switching Number of Outputs Switching Delta Tpd (ns) -1.5 -0.5 123456789 1 0 RISE FALL Delta Tco vs # of Outputs Switching Number of Outputs Switching Delta Tco (ns) -1.5 -0.5 123456789 1 0 RISE FALL Delta Tpd vs Output Loading Output Loading (pF) Delta Tpd (ns) 0 50 100 150 200 250 300 RISE FALL Delta Tco vs Output Loading Output Loading (pF) Delta Tco (ns) 0 50 100 150 200 250 300 RISE FALL GAL22V10B-7/-10/-15/-25L: Typical AC and DC Characteristic Diagrams

Iol (mA) Vol (V) 0.5 1.5 2.5 Voh vs Ioh Ioh(mA) Voh (V) Voh vs Ioh Ioh(mA) Voh (V) 3.5 3.75 4.25 4.5 Normalized Icc vs Vcc Supply Voltage (V) Normalized Icc 0.80 0.90 1.00 1.10 1.20 Normalized Icc vs Temp Temperature (deg. C) Normalized Icc 0.8 0.9 1.1 1.2 -55 -25 0 25 50 75 100 125 Normalized Icc vs Freq. Frequency (MHz) Normalized Icc 0.80 0.90 1.00 1.10 1.20 0 25 50 75 100 Delta Icc vs Vin (1 input) Vin (V) Delta Icc (mA) Input Clamp (Vik) Vik (V) Iik (mA) 100 GAL22V10B-7/-10/-15/-25L: Typical AC and DC Characteristic Diagrams

Supply Voltage (V) Normalized Tpd 0.8 0.9 1.1 1.2 Normalized Tco vs Vcc Supply Voltage (V) Normalized Tco 0.8 0.9 1.1 1.2 Normalized Tsu vs Vcc Supply Voltage (V) Normalized Tsu 0.8 0.9 1.1 1.2 Normalized Tpd vs Temp Temperature (deg. C) Normalized Tpd 0.7 0.8 0.9 1.1 1.2 1.3 -55 -25 100 125 Normalized Tco vs Temp Temperature (deg. C) Normalized Tco 0.7 0.8 0.9 1.1 1.2 1.3 -55 -25 100 125 Normalized Tsu vs Temp Temperature (deg. C) Normalized Tsu 0.7 0.8 0.9 1.1 1.2 1.3 1.4 -55 -25 100 125 Delta Tpd vs # of Outputs Switching Number of Outputs Switching Delta Tpd (ns) -0.75 -0.5 -0.25 123456789 1 0 Delta Tco vs # of Outputs Switching Number of Outputs Switching Delta Tco (ns) -1.5 -0.5 123456789 1 0 Delta Tpd vs Output Loading Output Loading (pF) Delta Tpd (ns) 0 50 100 150 200 250 300 RISE FALL Delta Tco vs Output Loading Output Loading (pF) Delta Tco (ns) 0 50 100 150 200 250 300 RISE FALL GAL22V10B-15/-25Q: Typical AC and DC Characteristic Diagrams

Iol (mA) Vol (V) 0.2 0.4 0.6 0.8 0.00 20.00 40.00 Voh vs Ioh Ioh(mA) Voh (V) Voh vs Ioh Ioh(mA) Voh (V) 3.25 3.5 3.75 Normalized Icc vs Vcc Supply Voltage (V) Normalized Icc 0.80 0.90 1.00 1.10 1.20 Normalized Icc vs Temp Temperature (deg. C) Normalized Icc 0.7 0.8 0.9 1.1 1.2 1.3 -55 -25 0 25 75 100 125 Normalized Icc vs Freq. Frequency (MHz) Normalized Icc 0.80 1.00 1.20 1.40 1.60 1.80 2.00 0 25 50 75 100 Delta Icc vs Vin (1 input) Vin (V) Delta Icc (mA) Input Clamp (Vik) Vik (V) Iik (mA) GAL22V10B-15/-25Q: Typical AC and DC Characteristic Diagrams

Summary

High Performance E2CMOS PLD Generic Array Logic

Description

The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much less power when compared to bipolar 22V10 devices. E2 technology offers high speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently.

Source title 22V10 Datasheet(PDF) - Lattice Semiconductor

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GAL22V10 LATTICE | Alldatasheet

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22V10 specifications and overview.

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