2096VL LATTICE | Alldatasheet
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Technical content
Features
- SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC — 4000 PLD Gates — 96 I/O Pins, Six Dedicated Inputs — 96 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic — 100% Functional, JEDEC and Pinout Compatible with ispLSI 2096V and 2096VE Devices
- 2.5V LOW VOLTAGE 2096 ARCHITECTURE — Interfaces with Standard 3.3V Devices (Inputs and I/Os are 3.3V Tolerant) — 85 mA Typical Active Current
- HIGH PERFORMANCE E 2CMOS ® TECHNOLOGY — fmax = 165 MHz Maximum Operating Frequency — tpd = 5.5 ns Propagation Delay — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power
- IN-SYSTEM PROGRAMMABLE — 2.5V In-System Programmability (ISP™) Using Boundary Scan Test Access Port (TAP) — Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic — Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality — Reprogram Soldered Devices for Faster Prototyping
- 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
- THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS — Enhanced Pin Locking Capability — Three Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity
- ispDesignEXPERT™ – LOGIC COMPILER AND COM- PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms
Description
The ispLSI 2096VL is a High Density Programmable Logic Device containing 96 Registers, six Dedicated Input pins, three Dedicated Clock Input pins, two dedi- cated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2096VL fea- tures in-system programmability through the Boundary Scan Test Access Port (TAP) and is 100% IEEE 1149.1 Boundary Scan Testable. The ispLSI 2096VL offers non- volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 2096VL device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. C7 (see Figure 1). There are a total of 24 GLBs in the ispLSI 2096VL device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. The devices also have 96 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, output or bi-directional I/O pin with 3-state control, and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching Global Routing Pool (GRP) Output Routing Pool (ORP) Output Routing Pool (ORP) 0919/2096VL C 7 C 4C 5C 6 A4 A7A6A5 GLB Logic Array DQ DQ DQ DQ Output Routing Pool (ORP) Output Routing Pool (ORP) C 3 C 0C 1C 2 B0 B3B2B1 Output Routing Pool (ORP) Output Routing Pool (ORP) Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com Functional Block Diagram
Specifications ispLSI 2096VL Absolute Maximum Ratings 1 Max. Junction Temp. (T J) with Power Applied ... 150°C 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). Table 2-0008/2096VL PARAMETER MINIMUM MAXIMUM UNITS Erase/Reprogram Cycles 10,000 — Cycles C SYMBOL Table 2-0006/2096VL C PARAMETER I/O Capacitance 6 UNITSTYPICAL TEST CONDITIONS 8Dedicated Input Capacitance pf pf V = 2.5V, V = 0.0V V = 2.5V, V = 0.0VCC CC I/O IN C Clock and Global Output Enable Capacitance 103 pf V = 2.5V, V = 0.0VCC Y TA = 0°C to + 70°C TA = -40°C to + 85°C SYMBOL Table 2-0005/2096VL VCC VIH VIL PARAMETER Supply Voltage Input High Voltage Input Low Voltage MIN. MAX. UNITS 2.3 2.3 1.7 -0.3 2.7 2.7 3.6 0.7 V V V V Commercial Industrial DC Recommended Operating Condition Capacitance (TA =25°C, f=1.0 MHz) Erase Reprogram Specifications
*C L includes Test Fixture and Probe Capacitance. Figure 2. Test Load
- One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test
problems by tester ground degradation. Characterized but not 100% tested.
- Measured using six 16-bit counters.
- Maximum ICC varies widely with specific device configuration and operating frequency. Refer to Power Consumption
- With no pull-up resistors.
Specifications ispLSI 2096VL External Timing Parameters Over Recommended Operating Conditions tpd1 UNITS -135 MIN. TEST COND. 1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock. 2. Standard 16-bit counter using GRP feedback. 3. Reference Switching Test Conditions section. Table 2-0030/2096VL tsu2 + tco1( ) -100 MIN.MAX. MAX.DESCRIPTION#PARAMETER A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass — 7.5 — 10.0 ns tpd2 A 2 Data Propagation Delay —— ns fmax A 3 Clock Frequency with Internal Feedback 135 — 100 — MHz fmax (Ext.) — 4 Clock Frequency with External Feedback —— MHz fmax (Tog.) — 5 Clock Frequency, Max. Toggle —— MHz tsu1 — 6 GLB Reg. Setup Time before Clock, 4 PT Bypass —— ns tco1 A 7 GLB Reg. Clock to Output Delay, ORP Bypass —— ns th1 — 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 — ns tsu2 — 9 GLB Reg. Setup Time before Clock 6.0 — ns tco2 A 10 GLB Reg. Clock to Output Delay —— ns th2 — 11 GLB Reg. Hold Time after Clock 0.0 — ns tr1 A 12 Ext. Reset Pin to Output Delay, ORP Bypass —— ns trw1 — 13 Ext. Reset Pulse Duration 5.5 — ns tptoeen B 14 Input to Output Enable —— ns tptoedis C 15 Input to Output Disable —— ns tgoeen B 16 Global OE Output Enable —— ns tgoedis C 17 Global OE Output Disable —— ns twh — 18 External Synchronous Clock Pulse Duration, High 3.5 —— ns twl — 19 External Synchronous Clock Pulse Duration, Low 3.5 —— ns 143 5.0 4.5 5.5 8.0 12.0 12.0 7.0 7.0 10.0 100 6.5 0.0 8.0 0.0 6.5 5.0 5.0 13.0 5.0 6.0 13.5 15.0 15.0 9.0 9.0 -165 MIN. MAX. — 5.5 165 — 0.0 4.5 0.0 5.0 3.0 — 3.0 — 118 166 3.5 4.0 5.0 6.0 10.0 10.0 6.0 6.0 8.0
Specifications ispLSI 2096VL Internal Timing Parameters1 Over Recommended Operating Conditions tio 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Table 2-0036/2096VL Inputs UNITS -135-165 MIN. -100
20 Input Buffer Delay ns
tdin 21 Dedicated Input Delay ns tgrp 22 GRP Delay ns GLB t1ptxor 25 1 Product Term/XOR Path Delay ns t20ptxor 26 20 Product Term/XOR Path Delay ns txoradj 27 XOR Adjacent Path Delay ns tgbp 28 GLB Register Bypass Delay ns tgsu 29 GLB Register Setup Time before Clock ns tgh 30 GLB Register Hold Time after Clock ns tgco 31 GLB Register Clock to Output Delay ns tgro 32 GLB Register Reset to Output Delay ns tptre 33 GLB Product Term Reset to Register Delay ns tptoe 34 GLB Product Term Output Enable to I/O Cell Delay ns tptck 35 GLB Product Term Clock Delay ns ORP tob 38 Output Buffer Delay ns tsl 39 Output Slew Limited Delay Adder ns GRP t4ptbpc 23 4 Product Term Bypass Path Delay (Combinatorial) ns t4ptbpr 24 4 Product Term Bypass Path Delay (Registered) ns torp 36 ORP Delay ns torpbp 37 ORP Bypass Delay ns Outputs toen 40 I/O Cell OE to Output Enabled ns todis 41 I/O Cell OE to Output Disabled ns tgoe 42 Global Output Enable ns tgy0 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) ns tgy1/2 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line ns Clocks tgr 45 Global Reset to GLB 0.5 1.6 1.1 3.4 3.4 3.4 0.0 0.3 0.6 4.8 4.9 4.1 1.6 2.0 1.9 2.4 1.4 0.4 3.5 3.5 2.5 1.7 1.9 3.4 1.2 2.3 1.1 1.7 1.9 1.0 2.2 1.2 4.2 4.2 4.2 0.5 0.3 1.1 6.6 5.8 4.5 1.6 2.0 3.2 3.2 1.5 0.5 4.0 4.0 3.0 2.1 2.3 4.8 1.7 3.3 2.1 2.1 2.3 0.9 2.7 1.8 6.2 6.2 6.2 1.0 0.3 4.3 8.9 7.4 4.8 1.6 2.0 5.2 4.7 1.5 0.5 4.9 4.9 4.1 2.6 2.8 7.1 1.7 4.8 2.8 2.6 2.8 — ns Global Reset
Specifications ispLSI 2096VL ispLSI 2096VL Timing Model GLB Reg Delay I/O Pin (Output) ORP Delay Feedback Reg 4 PT Bypass 20 PT XOR Delays Control PTs I/O Pin (Input) Y0,1,2 GRP GLB Reg Bypass ORP Bypass DQ RST RE OE CK I/O Delay I/O CellORPGLBGRPI/O Cell #24 #25, 26, 27 #33, 34, #43, 44 #36 Reset Ded. In #21 #20 #28 #29, 30, 31, 32 #38, GOE 0 #42 #40, 41 #22 Comb 4 PT Bypass #23 #37 #45 Derivations of tsu, th and tco from the Product Term Clock tsu Logic + Reg su - Clock (min) (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min)) th Clock (max) + Reg h - Logic (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor) tco Clock (max) + Reg co + Output (tio + tgrp + tptck(max)) + (tgco) + (torp + tob) Table 2-0042/2096VL Note: Calculations are based on timing specifications for the ispLSI 2096VL-165L. 3.5ns 3.0ns 9.0ns
Figure 3. Typical Device Power Consumption vs fmax operating conditions and the program in the device, the actual ICC should be verified.
Specifications ispLSI 2096VL Pin Description Input/Output Pins - These are the general purpose I/O pins used by the logic array. NAME Table 2-0002-2096VL TQFP PIN NUMBERS DESCRIPTION 21, 27, 35, 41, 51, 57, 64, 71, 85, 91, 99, 105, 115, 121, 128, 112 22, 28, 36, 42, 52, 58, 65, 72, 86, 92, 100, 106, 116, 122, 80, 17 23, 29, 37, 43, 53, 59, 67, 73, 87, 93, 101, 107, 117, 123, I/O 0 - I/O 5 I/O 6 - I/O 11 I/O 12 - I/O 17 I/O 18 - I/O 23 I/O 24 - I/O 29 I/O 30 - I/O 35 I/O 36 - I/O 41 I/O 42 - I/O 47 I/O 48 - I/O 53 I/O 54 - I/O 59 I/O 60 - I/O 65 I/O 66 - I/O 71 I/O 72 - I/O 77 I/O 78 - I/O 83 I/O 84 - I/O 89 I/O 90 - I/O 95 24, 30, 38, 44, 54, 60, 68, 74, 88, 94, 102, 108, 118, 124, 10, 25, 32, 39, 45, 55, 61, 69, 75, 89, 96, 103, 109, 119, 125, 11, 104 110 120 126 18, 111, 34, 127 50, 63, 95, 16, 114 31, 47, 66, 81, 79, 98, Global Output Enables input pins.GOE 0, GOE 1 GND VVCC CC Ground (GND) Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs on the device. Active Low (0) Reset pin which resets all of the registers in the device.RESET Y0, Y1, Y2 13, 49, 82 No Connect.NC 1 TDI/IN 0 BSCAN TMS/IN 1 11384, 7883, Dedicated input pins to the device.IN 4, IN 5 TDO/IN 2 TCK/IN 3 Output/Input This pin performs two functions. When BSCAN is logic low, it functions as an output pin to read serial shift register data. When BSCAN is high, it functions as a dedicated input pin. Input Dedicated in-system programming Boundary Scan enable input pin. This pin is brought low to enable the programming mode. The TMS, TDI, TDO and TCK controls become active. Input This pin performs two functions. When BSCAN is logic low, it functions as a serial data input pin to load programming data into the device. When BSCAN is high, it functions as a dedicated input pin. Input This pin performs two functions. When BSCAN is logic low, it functions as a mode control pin for the Boundary Scan state machine. When BSCAN is high, it functions as a dedicated input pin. Input This pin performs two functions. When BSCAN is logic low, it functions as a clock pin for the Boundary Scan state machine. When BSCAN is high, it functions as a dedicated input pin. 1. NC pins are not to be connected to any active signal, VCC or GND.
Specifications ispLSI 2096VL Pin Configuration ispLSI 2096VL 128-Pin TQFP Pinout Diagram VCC I/O 85 I/O 86 I/O 87 I/O 88 I/O 89 I/O 90 I/O 91 I/O 92 I/O 93 I/O 94 I/O 95 1NC RESET VCC GOE 1 GND BSCAN I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 VCC I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 IN 4 NC VCC GOE 0 TCK/IN 3 I/O 47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 I/O 38 VCC I/O 84 GND I/O 83 I/O 82 I/O 81 I/O 80 I/O 79 I/O 78 I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 IN 5 GND I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 I/O 65 I/O 64 I/O 63 I/O 62 I/O 61 I/O 60 GND I/O 59 I/O 10 GND I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 TMS/IN 1 1NC GND I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 I/O 35 GND ispLSI 2096VL Top View VCC TDI/IN 0 I/O 58 TDO/IN 2 GND I/O 37 I/O 11 VCC 128 127 126 125 124 123 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 9764 122 I/O 36 VCC 1. NC pins are not to be connected to any active signals, VCC or GND. 0124-2096VL
Specifications ispLSI 2096VL Part Number Description ispLSI 2096VL Ordering Information Table 2-0041A/2096VL FAMILY fmax (MHz) 165 135 ORDERING NUMBER PACKAGE 128-Pin TQFP tpd (ns) 5.5 7.5ispLSI ispLSI 2096VL-165LT128 128-Pin TQFPispLSI 2096VL-135LT128 100 128-Pin TQFP10 ispLSI 2096VL-100LT128 COMMERCIAL Device Number ispLSI 2096VL XX X XXXX Grade X Speed 165 = 165 MHz fmax 135 = 135 MHz fmax 100 = 100 MHz fmax Power L = Low Package Device Family 0212/2096VL T128 = 128-Pin TQFP Blank = Commercial I = Industrial Table 2-0041A/2032VL ispLSI 135 44-Pin TQFP7.5 ispLSI 2032VL-135LT44I FAMILY f max (MHz) ORDERING NUMBER PACKAGEtpd (ns) INDUSTRIAL